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1/*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <dt-bindings/reset/altr,rst-mgr.h>
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 ethernet1 = &gmac1;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 timer0 = &timer0;
30 timer1 = &timer1;
31 timer2 = &timer2;
32 timer3 = &timer3;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "altr,socfpga-smp";
39
40 cpu0: cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 };
46 cpu1: cpu@1 {
47 compatible = "arm,cortex-a9";
48 device_type = "cpu";
49 reg = <1>;
50 next-level-cache = <&L2>;
51 };
52 };
53
54 pmu: pmu@ff111000 {
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&intc>;
57 interrupts = <0 176 4>, <0 177 4>;
58 interrupt-affinity = <&cpu0>, <&cpu1>;
59 reg = <0xff111000 0x1000>,
60 <0xff113000 0x1000>;
61 };
62
63 intc: intc@fffed000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
66 interrupt-controller;
67 reg = <0xfffed000 0x1000>,
68 <0xfffec100 0x100>;
69 };
70
71 soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "simple-bus";
75 device_type = "soc";
76 interrupt-parent = <&intc>;
77 ranges;
78
79 amba {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84
85 pdma: pdma@ffe01000 {
86 compatible = "arm,pl330", "arm,primecell";
87 reg = <0xffe01000 0x1000>;
88 interrupts = <0 104 4>,
89 <0 105 4>,
90 <0 106 4>,
91 <0 107 4>,
92 <0 108 4>,
93 <0 109 4>,
94 <0 110 4>,
95 <0 111 4>;
96 #dma-cells = <1>;
97 #dma-channels = <8>;
98 #dma-requests = <32>;
99 clocks = <&l4_main_clk>;
100 clock-names = "apb_pclk";
101 };
102 };
103
104 base_fpga_region {
105 compatible = "fpga-region";
106 fpga-mgr = <&fpgamgr0>;
107
108 #address-cells = <0x1>;
109 #size-cells = <0x1>;
110 };
111
112 can0: can@ffc00000 {
113 compatible = "bosch,d_can";
114 reg = <0xffc00000 0x1000>;
115 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
116 clocks = <&can0_clk>;
117 status = "disabled";
118 };
119
120 can1: can@ffc01000 {
121 compatible = "bosch,d_can";
122 reg = <0xffc01000 0x1000>;
123 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
124 clocks = <&can1_clk>;
125 status = "disabled";
126 };
127
128 clkmgr@ffd04000 {
129 compatible = "altr,clk-mgr";
130 reg = <0xffd04000 0x1000>;
131
132 clocks {
133 #address-cells = <1>;
134 #size-cells = <0>;
135
136 osc1: osc1 {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 };
140
141 osc2: osc2 {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 };
145
146 f2s_periph_ref_clk: f2s_periph_ref_clk {
147 #clock-cells = <0>;
148 compatible = "fixed-clock";
149 };
150
151 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
152 #clock-cells = <0>;
153 compatible = "fixed-clock";
154 };
155
156 main_pll: main_pll@40 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-pll-clock";
161 clocks = <&osc1>;
162 reg = <0x40>;
163
164 mpuclk: mpuclk@48 {
165 #clock-cells = <0>;
166 compatible = "altr,socfpga-perip-clk";
167 clocks = <&main_pll>;
168 div-reg = <0xe0 0 9>;
169 reg = <0x48>;
170 };
171
172 mainclk: mainclk@4c {
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-perip-clk";
175 clocks = <&main_pll>;
176 div-reg = <0xe4 0 9>;
177 reg = <0x4C>;
178 };
179
180 dbg_base_clk: dbg_base_clk@50 {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&main_pll>, <&osc1>;
184 div-reg = <0xe8 0 9>;
185 reg = <0x50>;
186 };
187
188 main_qspi_clk: main_qspi_clk@54 {
189 #clock-cells = <0>;
190 compatible = "altr,socfpga-perip-clk";
191 clocks = <&main_pll>;
192 reg = <0x54>;
193 };
194
195 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
196 #clock-cells = <0>;
197 compatible = "altr,socfpga-perip-clk";
198 clocks = <&main_pll>;
199 reg = <0x58>;
200 };
201
202 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-perip-clk";
205 clocks = <&main_pll>;
206 reg = <0x5C>;
207 };
208 };
209
210 periph_pll: periph_pll@80 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 #clock-cells = <0>;
214 compatible = "altr,socfpga-pll-clock";
215 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
216 reg = <0x80>;
217
218 emac0_clk: emac0_clk@88 {
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-perip-clk";
221 clocks = <&periph_pll>;
222 reg = <0x88>;
223 };
224
225 emac1_clk: emac1_clk@8c {
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-perip-clk";
228 clocks = <&periph_pll>;
229 reg = <0x8C>;
230 };
231
232 per_qspi_clk: per_qsi_clk@90 {
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-perip-clk";
235 clocks = <&periph_pll>;
236 reg = <0x90>;
237 };
238
239 per_nand_mmc_clk: per_nand_mmc_clk@94 {
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-perip-clk";
242 clocks = <&periph_pll>;
243 reg = <0x94>;
244 };
245
246 per_base_clk: per_base_clk@98 {
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-perip-clk";
249 clocks = <&periph_pll>;
250 reg = <0x98>;
251 };
252
253 h2f_usr1_clk: h2f_usr1_clk@9c {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-perip-clk";
256 clocks = <&periph_pll>;
257 reg = <0x9C>;
258 };
259 };
260
261 sdram_pll: sdram_pll@c0 {
262 #address-cells = <1>;
263 #size-cells = <0>;
264 #clock-cells = <0>;
265 compatible = "altr,socfpga-pll-clock";
266 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
267 reg = <0xC0>;
268
269 ddr_dqs_clk: ddr_dqs_clk@c8 {
270 #clock-cells = <0>;
271 compatible = "altr,socfpga-perip-clk";
272 clocks = <&sdram_pll>;
273 reg = <0xC8>;
274 };
275
276 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
277 #clock-cells = <0>;
278 compatible = "altr,socfpga-perip-clk";
279 clocks = <&sdram_pll>;
280 reg = <0xCC>;
281 };
282
283 ddr_dq_clk: ddr_dq_clk@d0 {
284 #clock-cells = <0>;
285 compatible = "altr,socfpga-perip-clk";
286 clocks = <&sdram_pll>;
287 reg = <0xD0>;
288 };
289
290 h2f_usr2_clk: h2f_usr2_clk@d4 {
291 #clock-cells = <0>;
292 compatible = "altr,socfpga-perip-clk";
293 clocks = <&sdram_pll>;
294 reg = <0xD4>;
295 };
296 };
297
298 mpu_periph_clk: mpu_periph_clk {
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-perip-clk";
301 clocks = <&mpuclk>;
302 fixed-divider = <4>;
303 };
304
305 mpu_l2_ram_clk: mpu_l2_ram_clk {
306 #clock-cells = <0>;
307 compatible = "altr,socfpga-perip-clk";
308 clocks = <&mpuclk>;
309 fixed-divider = <2>;
310 };
311
312 l4_main_clk: l4_main_clk {
313 #clock-cells = <0>;
314 compatible = "altr,socfpga-gate-clk";
315 clocks = <&mainclk>;
316 clk-gate = <0x60 0>;
317 };
318
319 l3_main_clk: l3_main_clk {
320 #clock-cells = <0>;
321 compatible = "altr,socfpga-perip-clk";
322 clocks = <&mainclk>;
323 fixed-divider = <1>;
324 };
325
326 l3_mp_clk: l3_mp_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-gate-clk";
329 clocks = <&mainclk>;
330 div-reg = <0x64 0 2>;
331 clk-gate = <0x60 1>;
332 };
333
334 l3_sp_clk: l3_sp_clk {
335 #clock-cells = <0>;
336 compatible = "altr,socfpga-gate-clk";
337 clocks = <&l3_mp_clk>;
338 div-reg = <0x64 2 2>;
339 };
340
341 l4_mp_clk: l4_mp_clk {
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-gate-clk";
344 clocks = <&mainclk>, <&per_base_clk>;
345 div-reg = <0x64 4 3>;
346 clk-gate = <0x60 2>;
347 };
348
349 l4_sp_clk: l4_sp_clk {
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-gate-clk";
352 clocks = <&mainclk>, <&per_base_clk>;
353 div-reg = <0x64 7 3>;
354 clk-gate = <0x60 3>;
355 };
356
357 dbg_at_clk: dbg_at_clk {
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-gate-clk";
360 clocks = <&dbg_base_clk>;
361 div-reg = <0x68 0 2>;
362 clk-gate = <0x60 4>;
363 };
364
365 dbg_clk: dbg_clk {
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-gate-clk";
368 clocks = <&dbg_at_clk>;
369 div-reg = <0x68 2 2>;
370 clk-gate = <0x60 5>;
371 };
372
373 dbg_trace_clk: dbg_trace_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-gate-clk";
376 clocks = <&dbg_base_clk>;
377 div-reg = <0x6C 0 3>;
378 clk-gate = <0x60 6>;
379 };
380
381 dbg_timer_clk: dbg_timer_clk {
382 #clock-cells = <0>;
383 compatible = "altr,socfpga-gate-clk";
384 clocks = <&dbg_base_clk>;
385 clk-gate = <0x60 7>;
386 };
387
388 cfg_clk: cfg_clk {
389 #clock-cells = <0>;
390 compatible = "altr,socfpga-gate-clk";
391 clocks = <&cfg_h2f_usr0_clk>;
392 clk-gate = <0x60 8>;
393 };
394
395 h2f_user0_clk: h2f_user0_clk {
396 #clock-cells = <0>;
397 compatible = "altr,socfpga-gate-clk";
398 clocks = <&cfg_h2f_usr0_clk>;
399 clk-gate = <0x60 9>;
400 };
401
402 emac_0_clk: emac_0_clk {
403 #clock-cells = <0>;
404 compatible = "altr,socfpga-gate-clk";
405 clocks = <&emac0_clk>;
406 clk-gate = <0xa0 0>;
407 };
408
409 emac_1_clk: emac_1_clk {
410 #clock-cells = <0>;
411 compatible = "altr,socfpga-gate-clk";
412 clocks = <&emac1_clk>;
413 clk-gate = <0xa0 1>;
414 };
415
416 usb_mp_clk: usb_mp_clk {
417 #clock-cells = <0>;
418 compatible = "altr,socfpga-gate-clk";
419 clocks = <&per_base_clk>;
420 clk-gate = <0xa0 2>;
421 div-reg = <0xa4 0 3>;
422 };
423
424 spi_m_clk: spi_m_clk {
425 #clock-cells = <0>;
426 compatible = "altr,socfpga-gate-clk";
427 clocks = <&per_base_clk>;
428 clk-gate = <0xa0 3>;
429 div-reg = <0xa4 3 3>;
430 };
431
432 can0_clk: can0_clk {
433 #clock-cells = <0>;
434 compatible = "altr,socfpga-gate-clk";
435 clocks = <&per_base_clk>;
436 clk-gate = <0xa0 4>;
437 div-reg = <0xa4 6 3>;
438 };
439
440 can1_clk: can1_clk {
441 #clock-cells = <0>;
442 compatible = "altr,socfpga-gate-clk";
443 clocks = <&per_base_clk>;
444 clk-gate = <0xa0 5>;
445 div-reg = <0xa4 9 3>;
446 };
447
448 gpio_db_clk: gpio_db_clk {
449 #clock-cells = <0>;
450 compatible = "altr,socfpga-gate-clk";
451 clocks = <&per_base_clk>;
452 clk-gate = <0xa0 6>;
453 div-reg = <0xa8 0 24>;
454 };
455
456 h2f_user1_clk: h2f_user1_clk {
457 #clock-cells = <0>;
458 compatible = "altr,socfpga-gate-clk";
459 clocks = <&h2f_usr1_clk>;
460 clk-gate = <0xa0 7>;
461 };
462
463 sdmmc_clk: sdmmc_clk {
464 #clock-cells = <0>;
465 compatible = "altr,socfpga-gate-clk";
466 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
467 clk-gate = <0xa0 8>;
468 clk-phase = <0 135>;
469 };
470
471 sdmmc_clk_divided: sdmmc_clk_divided {
472 #clock-cells = <0>;
473 compatible = "altr,socfpga-gate-clk";
474 clocks = <&sdmmc_clk>;
475 clk-gate = <0xa0 8>;
476 fixed-divider = <4>;
477 };
478
479 nand_x_clk: nand_x_clk {
480 #clock-cells = <0>;
481 compatible = "altr,socfpga-gate-clk";
482 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
483 clk-gate = <0xa0 9>;
484 };
485
486 nand_clk: nand_clk {
487 #clock-cells = <0>;
488 compatible = "altr,socfpga-gate-clk";
489 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
490 clk-gate = <0xa0 10>;
491 fixed-divider = <4>;
492 };
493
494 qspi_clk: qspi_clk {
495 #clock-cells = <0>;
496 compatible = "altr,socfpga-gate-clk";
497 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
498 clk-gate = <0xa0 11>;
499 };
500
501 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
502 #clock-cells = <0>;
503 compatible = "altr,socfpga-gate-clk";
504 clocks = <&ddr_dqs_clk>;
505 clk-gate = <0xd8 0>;
506 };
507
508 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
509 #clock-cells = <0>;
510 compatible = "altr,socfpga-gate-clk";
511 clocks = <&ddr_2x_dqs_clk>;
512 clk-gate = <0xd8 1>;
513 };
514
515 ddr_dq_clk_gate: ddr_dq_clk_gate {
516 #clock-cells = <0>;
517 compatible = "altr,socfpga-gate-clk";
518 clocks = <&ddr_dq_clk>;
519 clk-gate = <0xd8 2>;
520 };
521
522 h2f_user2_clk: h2f_user2_clk {
523 #clock-cells = <0>;
524 compatible = "altr,socfpga-gate-clk";
525 clocks = <&h2f_usr2_clk>;
526 clk-gate = <0xd8 3>;
527 };
528
529 };
530 };
531
532 fpga_bridge0: fpga_bridge@ff400000 {
533 compatible = "altr,socfpga-lwhps2fpga-bridge";
534 reg = <0xff400000 0x100000>;
535 resets = <&rst LWHPS2FPGA_RESET>;
536 clocks = <&l4_main_clk>;
537 };
538
539 fpga_bridge1: fpga_bridge@ff500000 {
540 compatible = "altr,socfpga-hps2fpga-bridge";
541 reg = <0xff500000 0x10000>;
542 resets = <&rst HPS2FPGA_RESET>;
543 clocks = <&l4_main_clk>;
544 };
545
546 fpgamgr0: fpgamgr@ff706000 {
547 compatible = "altr,socfpga-fpga-mgr";
548 reg = <0xff706000 0x1000
549 0xffb90000 0x4>;
550 interrupts = <0 175 4>;
551 };
552
553 gmac0: ethernet@ff700000 {
554 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
555 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
556 reg = <0xff700000 0x2000>;
557 interrupts = <0 115 4>;
558 interrupt-names = "macirq";
559 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
560 clocks = <&emac_0_clk>;
561 clock-names = "stmmaceth";
562 resets = <&rst EMAC0_RESET>;
563 reset-names = "stmmaceth";
564 snps,multicast-filter-bins = <256>;
565 snps,perfect-filter-entries = <128>;
566 tx-fifo-depth = <4096>;
567 rx-fifo-depth = <4096>;
568 status = "disabled";
569 };
570
571 gmac1: ethernet@ff702000 {
572 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
573 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
574 reg = <0xff702000 0x2000>;
575 interrupts = <0 120 4>;
576 interrupt-names = "macirq";
577 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
578 clocks = <&emac_1_clk>;
579 clock-names = "stmmaceth";
580 resets = <&rst EMAC1_RESET>;
581 reset-names = "stmmaceth";
582 snps,multicast-filter-bins = <256>;
583 snps,perfect-filter-entries = <128>;
584 tx-fifo-depth = <4096>;
585 rx-fifo-depth = <4096>;
586 status = "disabled";
587 };
588
589 gpio0: gpio@ff708000 {
590 #address-cells = <1>;
591 #size-cells = <0>;
592 compatible = "snps,dw-apb-gpio";
593 reg = <0xff708000 0x1000>;
594 clocks = <&l4_mp_clk>;
595 status = "disabled";
596
597 porta: gpio-controller@0 {
598 compatible = "snps,dw-apb-gpio-port";
599 gpio-controller;
600 #gpio-cells = <2>;
601 snps,nr-gpios = <29>;
602 reg = <0>;
603 interrupt-controller;
604 #interrupt-cells = <2>;
605 interrupts = <0 164 4>;
606 };
607 };
608
609 gpio1: gpio@ff709000 {
610 #address-cells = <1>;
611 #size-cells = <0>;
612 compatible = "snps,dw-apb-gpio";
613 reg = <0xff709000 0x1000>;
614 clocks = <&l4_mp_clk>;
615 status = "disabled";
616
617 portb: gpio-controller@0 {
618 compatible = "snps,dw-apb-gpio-port";
619 gpio-controller;
620 #gpio-cells = <2>;
621 snps,nr-gpios = <29>;
622 reg = <0>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
625 interrupts = <0 165 4>;
626 };
627 };
628
629 gpio2: gpio@ff70a000 {
630 #address-cells = <1>;
631 #size-cells = <0>;
632 compatible = "snps,dw-apb-gpio";
633 reg = <0xff70a000 0x1000>;
634 clocks = <&l4_mp_clk>;
635 status = "disabled";
636
637 portc: gpio-controller@0 {
638 compatible = "snps,dw-apb-gpio-port";
639 gpio-controller;
640 #gpio-cells = <2>;
641 snps,nr-gpios = <27>;
642 reg = <0>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 interrupts = <0 166 4>;
646 };
647 };
648
649 i2c0: i2c@ffc04000 {
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "snps,designware-i2c";
653 reg = <0xffc04000 0x1000>;
654 resets = <&rst I2C0_RESET>;
655 clocks = <&l4_sp_clk>;
656 interrupts = <0 158 0x4>;
657 status = "disabled";
658 };
659
660 i2c1: i2c@ffc05000 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 compatible = "snps,designware-i2c";
664 reg = <0xffc05000 0x1000>;
665 resets = <&rst I2C1_RESET>;
666 clocks = <&l4_sp_clk>;
667 interrupts = <0 159 0x4>;
668 status = "disabled";
669 };
670
671 i2c2: i2c@ffc06000 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 compatible = "snps,designware-i2c";
675 reg = <0xffc06000 0x1000>;
676 resets = <&rst I2C2_RESET>;
677 clocks = <&l4_sp_clk>;
678 interrupts = <0 160 0x4>;
679 status = "disabled";
680 };
681
682 i2c3: i2c@ffc07000 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 compatible = "snps,designware-i2c";
686 reg = <0xffc07000 0x1000>;
687 resets = <&rst I2C3_RESET>;
688 clocks = <&l4_sp_clk>;
689 interrupts = <0 161 0x4>;
690 status = "disabled";
691 };
692
693 eccmgr: eccmgr {
694 compatible = "altr,socfpga-ecc-manager";
695 #address-cells = <1>;
696 #size-cells = <1>;
697 ranges;
698
699 l2-ecc@ffd08140 {
700 compatible = "altr,socfpga-l2-ecc";
701 reg = <0xffd08140 0x4>;
702 interrupts = <0 36 1>, <0 37 1>;
703 };
704
705 ocram-ecc@ffd08144 {
706 compatible = "altr,socfpga-ocram-ecc";
707 reg = <0xffd08144 0x4>;
708 iram = <&ocram>;
709 interrupts = <0 178 1>, <0 179 1>;
710 };
711 };
712
713 L2: l2-cache@fffef000 {
714 compatible = "arm,pl310-cache";
715 reg = <0xfffef000 0x1000>;
716 interrupts = <0 38 0x04>;
717 cache-unified;
718 cache-level = <2>;
719 arm,tag-latency = <1 1 1>;
720 arm,data-latency = <2 1 1>;
721 prefetch-data = <1>;
722 prefetch-instr = <1>;
723 arm,shared-override;
724 arm,double-linefill = <1>;
725 arm,double-linefill-incr = <0>;
726 arm,double-linefill-wrap = <1>;
727 arm,prefetch-drop = <0>;
728 arm,prefetch-offset = <7>;
729 };
730
731 l3regs@0xff800000 {
732 compatible = "altr,l3regs", "syscon";
733 reg = <0xff800000 0x1000>;
734 };
735
736 mmc: dwmmc0@ff704000 {
737 compatible = "altr,socfpga-dw-mshc";
738 reg = <0xff704000 0x1000>;
739 interrupts = <0 139 4>;
740 fifo-depth = <0x400>;
741 #address-cells = <1>;
742 #size-cells = <0>;
743 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
744 clock-names = "biu", "ciu";
745 status = "disabled";
746 };
747
748 nand0: nand@ff900000 {
749 #address-cells = <0x1>;
750 #size-cells = <0x1>;
751 compatible = "denali,denali-nand-dt";
752 reg = <0xff900000 0x100000>,
753 <0xffb80000 0x10000>;
754 reg-names = "nand_data", "denali_reg";
755 interrupts = <0x0 0x90 0x4>;
756 dma-mask = <0xffffffff>;
757 clocks = <&nand_clk>;
758 status = "disabled";
759 };
760
761 ocram: sram@ffff0000 {
762 compatible = "mmio-sram";
763 reg = <0xffff0000 0x10000>;
764 };
765
766 qspi: spi@ff705000 {
767 compatible = "cdns,qspi-nor";
768 #address-cells = <1>;
769 #size-cells = <0>;
770 reg = <0xff705000 0x1000>,
771 <0xffa00000 0x1000>;
772 interrupts = <0 151 4>;
773 cdns,fifo-depth = <128>;
774 cdns,fifo-width = <4>;
775 cdns,trigger-address = <0x00000000>;
776 clocks = <&qspi_clk>;
777 status = "disabled";
778 };
779
780 rst: rstmgr@ffd05000 {
781 #reset-cells = <1>;
782 compatible = "altr,rst-mgr";
783 reg = <0xffd05000 0x1000>;
784 altr,modrst-offset = <0x10>;
785 };
786
787 scu: snoop-control-unit@fffec000 {
788 compatible = "arm,cortex-a9-scu";
789 reg = <0xfffec000 0x100>;
790 };
791
792 sdr: sdr@ffc25000 {
793 compatible = "altr,sdr-ctl", "syscon";
794 reg = <0xffc25000 0x1000>;
795 };
796
797 sdramedac {
798 compatible = "altr,sdram-edac";
799 altr,sdr-syscon = <&sdr>;
800 interrupts = <0 39 4>;
801 };
802
803 spi0: spi@fff00000 {
804 compatible = "snps,dw-apb-ssi";
805 #address-cells = <1>;
806 #size-cells = <0>;
807 reg = <0xfff00000 0x1000>;
808 interrupts = <0 154 4>;
809 num-cs = <4>;
810 clocks = <&spi_m_clk>;
811 status = "disabled";
812 };
813
814 spi1: spi@fff01000 {
815 compatible = "snps,dw-apb-ssi";
816 #address-cells = <1>;
817 #size-cells = <0>;
818 reg = <0xfff01000 0x1000>;
819 interrupts = <0 155 4>;
820 num-cs = <4>;
821 clocks = <&spi_m_clk>;
822 status = "disabled";
823 };
824
825 sysmgr: sysmgr@ffd08000 {
826 compatible = "altr,sys-mgr", "syscon";
827 reg = <0xffd08000 0x4000>;
828 };
829
830 /* Local timer */
831 timer@fffec600 {
832 compatible = "arm,cortex-a9-twd-timer";
833 reg = <0xfffec600 0x100>;
834 interrupts = <1 13 0xf01>;
835 clocks = <&mpu_periph_clk>;
836 };
837
838 timer0: timer0@ffc08000 {
839 compatible = "snps,dw-apb-timer";
840 interrupts = <0 167 4>;
841 reg = <0xffc08000 0x1000>;
842 clocks = <&l4_sp_clk>;
843 clock-names = "timer";
844 };
845
846 timer1: timer1@ffc09000 {
847 compatible = "snps,dw-apb-timer";
848 interrupts = <0 168 4>;
849 reg = <0xffc09000 0x1000>;
850 clocks = <&l4_sp_clk>;
851 clock-names = "timer";
852 };
853
854 timer2: timer2@ffd00000 {
855 compatible = "snps,dw-apb-timer";
856 interrupts = <0 169 4>;
857 reg = <0xffd00000 0x1000>;
858 clocks = <&osc1>;
859 clock-names = "timer";
860 };
861
862 timer3: timer3@ffd01000 {
863 compatible = "snps,dw-apb-timer";
864 interrupts = <0 170 4>;
865 reg = <0xffd01000 0x1000>;
866 clocks = <&osc1>;
867 clock-names = "timer";
868 };
869
870 uart0: serial0@ffc02000 {
871 compatible = "snps,dw-apb-uart";
872 reg = <0xffc02000 0x1000>;
873 interrupts = <0 162 4>;
874 reg-shift = <2>;
875 reg-io-width = <4>;
876 clocks = <&l4_sp_clk>;
877 dmas = <&pdma 28>,
878 <&pdma 29>;
879 dma-names = "tx", "rx";
880 };
881
882 uart1: serial1@ffc03000 {
883 compatible = "snps,dw-apb-uart";
884 reg = <0xffc03000 0x1000>;
885 interrupts = <0 163 4>;
886 reg-shift = <2>;
887 reg-io-width = <4>;
888 clocks = <&l4_sp_clk>;
889 dmas = <&pdma 30>,
890 <&pdma 31>;
891 dma-names = "tx", "rx";
892 };
893
894 usbphy0: usbphy {
895 #phy-cells = <0>;
896 compatible = "usb-nop-xceiv";
897 status = "okay";
898 };
899
900 usb0: usb@ffb00000 {
901 compatible = "snps,dwc2";
902 reg = <0xffb00000 0xffff>;
903 interrupts = <0 125 4>;
904 clocks = <&usb_mp_clk>;
905 clock-names = "otg";
906 resets = <&rst USB0_RESET>;
907 reset-names = "dwc2";
908 phys = <&usbphy0>;
909 phy-names = "usb2-phy";
910 status = "disabled";
911 };
912
913 usb1: usb@ffb40000 {
914 compatible = "snps,dwc2";
915 reg = <0xffb40000 0xffff>;
916 interrupts = <0 128 4>;
917 clocks = <&usb_mp_clk>;
918 clock-names = "otg";
919 resets = <&rst USB1_RESET>;
920 reset-names = "dwc2";
921 phys = <&usbphy0>;
922 phy-names = "usb2-phy";
923 status = "disabled";
924 };
925
926 watchdog0: watchdog@ffd02000 {
927 compatible = "snps,dw-wdt";
928 reg = <0xffd02000 0x1000>;
929 interrupts = <0 171 4>;
930 clocks = <&osc1>;
931 status = "disabled";
932 };
933
934 watchdog1: watchdog@ffd03000 {
935 compatible = "snps,dw-wdt";
936 reg = <0xffd03000 0x1000>;
937 interrupts = <0 172 4>;
938 clocks = <&osc1>;
939 status = "disabled";
940 };
941 };
942};
1/*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "skeleton.dtsi"
19#include <dt-bindings/reset/altr,rst-mgr.h>
20
21/ {
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 ethernet0 = &gmac0;
27 ethernet1 = &gmac1;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 timer0 = &timer0;
31 timer1 = &timer1;
32 timer2 = &timer2;
33 timer3 = &timer3;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 enable-method = "altr,socfpga-smp";
40
41 cpu@0 {
42 compatible = "arm,cortex-a9";
43 device_type = "cpu";
44 reg = <0>;
45 next-level-cache = <&L2>;
46 };
47 cpu@1 {
48 compatible = "arm,cortex-a9";
49 device_type = "cpu";
50 reg = <1>;
51 next-level-cache = <&L2>;
52 };
53 };
54
55 intc: intc@fffed000 {
56 compatible = "arm,cortex-a9-gic";
57 #interrupt-cells = <3>;
58 interrupt-controller;
59 reg = <0xfffed000 0x1000>,
60 <0xfffec100 0x100>;
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 device_type = "soc";
68 interrupt-parent = <&intc>;
69 ranges;
70
71 amba {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 pdma: pdma@ffe01000 {
78 compatible = "arm,pl330", "arm,primecell";
79 reg = <0xffe01000 0x1000>;
80 interrupts = <0 104 4>,
81 <0 105 4>,
82 <0 106 4>,
83 <0 107 4>,
84 <0 108 4>,
85 <0 109 4>,
86 <0 110 4>,
87 <0 111 4>;
88 #dma-cells = <1>;
89 #dma-channels = <8>;
90 #dma-requests = <32>;
91 clocks = <&l4_main_clk>;
92 clock-names = "apb_pclk";
93 };
94 };
95
96 can0: can@ffc00000 {
97 compatible = "bosch,d_can";
98 reg = <0xffc00000 0x1000>;
99 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
100 clocks = <&can0_clk>;
101 status = "disabled";
102 };
103
104 can1: can@ffc01000 {
105 compatible = "bosch,d_can";
106 reg = <0xffc01000 0x1000>;
107 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
108 clocks = <&can1_clk>;
109 status = "disabled";
110 };
111
112 clkmgr@ffd04000 {
113 compatible = "altr,clk-mgr";
114 reg = <0xffd04000 0x1000>;
115
116 clocks {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 osc1: osc1 {
121 #clock-cells = <0>;
122 compatible = "fixed-clock";
123 };
124
125 osc2: osc2 {
126 #clock-cells = <0>;
127 compatible = "fixed-clock";
128 };
129
130 f2s_periph_ref_clk: f2s_periph_ref_clk {
131 #clock-cells = <0>;
132 compatible = "fixed-clock";
133 };
134
135 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
136 #clock-cells = <0>;
137 compatible = "fixed-clock";
138 };
139
140 main_pll: main_pll {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 #clock-cells = <0>;
144 compatible = "altr,socfpga-pll-clock";
145 clocks = <&osc1>;
146 reg = <0x40>;
147
148 mpuclk: mpuclk {
149 #clock-cells = <0>;
150 compatible = "altr,socfpga-perip-clk";
151 clocks = <&main_pll>;
152 div-reg = <0xe0 0 9>;
153 reg = <0x48>;
154 };
155
156 mainclk: mainclk {
157 #clock-cells = <0>;
158 compatible = "altr,socfpga-perip-clk";
159 clocks = <&main_pll>;
160 div-reg = <0xe4 0 9>;
161 reg = <0x4C>;
162 };
163
164 dbg_base_clk: dbg_base_clk {
165 #clock-cells = <0>;
166 compatible = "altr,socfpga-perip-clk";
167 clocks = <&main_pll>, <&osc1>;
168 div-reg = <0xe8 0 9>;
169 reg = <0x50>;
170 };
171
172 main_qspi_clk: main_qspi_clk {
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-perip-clk";
175 clocks = <&main_pll>;
176 reg = <0x54>;
177 };
178
179 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
180 #clock-cells = <0>;
181 compatible = "altr,socfpga-perip-clk";
182 clocks = <&main_pll>;
183 reg = <0x58>;
184 };
185
186 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
187 #clock-cells = <0>;
188 compatible = "altr,socfpga-perip-clk";
189 clocks = <&main_pll>;
190 reg = <0x5C>;
191 };
192 };
193
194 periph_pll: periph_pll {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 #clock-cells = <0>;
198 compatible = "altr,socfpga-pll-clock";
199 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
200 reg = <0x80>;
201
202 emac0_clk: emac0_clk {
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-perip-clk";
205 clocks = <&periph_pll>;
206 reg = <0x88>;
207 };
208
209 emac1_clk: emac1_clk {
210 #clock-cells = <0>;
211 compatible = "altr,socfpga-perip-clk";
212 clocks = <&periph_pll>;
213 reg = <0x8C>;
214 };
215
216 per_qspi_clk: per_qsi_clk {
217 #clock-cells = <0>;
218 compatible = "altr,socfpga-perip-clk";
219 clocks = <&periph_pll>;
220 reg = <0x90>;
221 };
222
223 per_nand_mmc_clk: per_nand_mmc_clk {
224 #clock-cells = <0>;
225 compatible = "altr,socfpga-perip-clk";
226 clocks = <&periph_pll>;
227 reg = <0x94>;
228 };
229
230 per_base_clk: per_base_clk {
231 #clock-cells = <0>;
232 compatible = "altr,socfpga-perip-clk";
233 clocks = <&periph_pll>;
234 reg = <0x98>;
235 };
236
237 h2f_usr1_clk: h2f_usr1_clk {
238 #clock-cells = <0>;
239 compatible = "altr,socfpga-perip-clk";
240 clocks = <&periph_pll>;
241 reg = <0x9C>;
242 };
243 };
244
245 sdram_pll: sdram_pll {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 #clock-cells = <0>;
249 compatible = "altr,socfpga-pll-clock";
250 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
251 reg = <0xC0>;
252
253 ddr_dqs_clk: ddr_dqs_clk {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-perip-clk";
256 clocks = <&sdram_pll>;
257 reg = <0xC8>;
258 };
259
260 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
261 #clock-cells = <0>;
262 compatible = "altr,socfpga-perip-clk";
263 clocks = <&sdram_pll>;
264 reg = <0xCC>;
265 };
266
267 ddr_dq_clk: ddr_dq_clk {
268 #clock-cells = <0>;
269 compatible = "altr,socfpga-perip-clk";
270 clocks = <&sdram_pll>;
271 reg = <0xD0>;
272 };
273
274 h2f_usr2_clk: h2f_usr2_clk {
275 #clock-cells = <0>;
276 compatible = "altr,socfpga-perip-clk";
277 clocks = <&sdram_pll>;
278 reg = <0xD4>;
279 };
280 };
281
282 mpu_periph_clk: mpu_periph_clk {
283 #clock-cells = <0>;
284 compatible = "altr,socfpga-perip-clk";
285 clocks = <&mpuclk>;
286 fixed-divider = <4>;
287 };
288
289 mpu_l2_ram_clk: mpu_l2_ram_clk {
290 #clock-cells = <0>;
291 compatible = "altr,socfpga-perip-clk";
292 clocks = <&mpuclk>;
293 fixed-divider = <2>;
294 };
295
296 l4_main_clk: l4_main_clk {
297 #clock-cells = <0>;
298 compatible = "altr,socfpga-gate-clk";
299 clocks = <&mainclk>;
300 clk-gate = <0x60 0>;
301 };
302
303 l3_main_clk: l3_main_clk {
304 #clock-cells = <0>;
305 compatible = "altr,socfpga-perip-clk";
306 clocks = <&mainclk>;
307 fixed-divider = <1>;
308 };
309
310 l3_mp_clk: l3_mp_clk {
311 #clock-cells = <0>;
312 compatible = "altr,socfpga-gate-clk";
313 clocks = <&mainclk>;
314 div-reg = <0x64 0 2>;
315 clk-gate = <0x60 1>;
316 };
317
318 l3_sp_clk: l3_sp_clk {
319 #clock-cells = <0>;
320 compatible = "altr,socfpga-gate-clk";
321 clocks = <&l3_mp_clk>;
322 div-reg = <0x64 2 2>;
323 };
324
325 l4_mp_clk: l4_mp_clk {
326 #clock-cells = <0>;
327 compatible = "altr,socfpga-gate-clk";
328 clocks = <&mainclk>, <&per_base_clk>;
329 div-reg = <0x64 4 3>;
330 clk-gate = <0x60 2>;
331 };
332
333 l4_sp_clk: l4_sp_clk {
334 #clock-cells = <0>;
335 compatible = "altr,socfpga-gate-clk";
336 clocks = <&mainclk>, <&per_base_clk>;
337 div-reg = <0x64 7 3>;
338 clk-gate = <0x60 3>;
339 };
340
341 dbg_at_clk: dbg_at_clk {
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-gate-clk";
344 clocks = <&dbg_base_clk>;
345 div-reg = <0x68 0 2>;
346 clk-gate = <0x60 4>;
347 };
348
349 dbg_clk: dbg_clk {
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-gate-clk";
352 clocks = <&dbg_at_clk>;
353 div-reg = <0x68 2 2>;
354 clk-gate = <0x60 5>;
355 };
356
357 dbg_trace_clk: dbg_trace_clk {
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-gate-clk";
360 clocks = <&dbg_base_clk>;
361 div-reg = <0x6C 0 3>;
362 clk-gate = <0x60 6>;
363 };
364
365 dbg_timer_clk: dbg_timer_clk {
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-gate-clk";
368 clocks = <&dbg_base_clk>;
369 clk-gate = <0x60 7>;
370 };
371
372 cfg_clk: cfg_clk {
373 #clock-cells = <0>;
374 compatible = "altr,socfpga-gate-clk";
375 clocks = <&cfg_h2f_usr0_clk>;
376 clk-gate = <0x60 8>;
377 };
378
379 h2f_user0_clk: h2f_user0_clk {
380 #clock-cells = <0>;
381 compatible = "altr,socfpga-gate-clk";
382 clocks = <&cfg_h2f_usr0_clk>;
383 clk-gate = <0x60 9>;
384 };
385
386 emac_0_clk: emac_0_clk {
387 #clock-cells = <0>;
388 compatible = "altr,socfpga-gate-clk";
389 clocks = <&emac0_clk>;
390 clk-gate = <0xa0 0>;
391 };
392
393 emac_1_clk: emac_1_clk {
394 #clock-cells = <0>;
395 compatible = "altr,socfpga-gate-clk";
396 clocks = <&emac1_clk>;
397 clk-gate = <0xa0 1>;
398 };
399
400 usb_mp_clk: usb_mp_clk {
401 #clock-cells = <0>;
402 compatible = "altr,socfpga-gate-clk";
403 clocks = <&per_base_clk>;
404 clk-gate = <0xa0 2>;
405 div-reg = <0xa4 0 3>;
406 };
407
408 spi_m_clk: spi_m_clk {
409 #clock-cells = <0>;
410 compatible = "altr,socfpga-gate-clk";
411 clocks = <&per_base_clk>;
412 clk-gate = <0xa0 3>;
413 div-reg = <0xa4 3 3>;
414 };
415
416 can0_clk: can0_clk {
417 #clock-cells = <0>;
418 compatible = "altr,socfpga-gate-clk";
419 clocks = <&per_base_clk>;
420 clk-gate = <0xa0 4>;
421 div-reg = <0xa4 6 3>;
422 };
423
424 can1_clk: can1_clk {
425 #clock-cells = <0>;
426 compatible = "altr,socfpga-gate-clk";
427 clocks = <&per_base_clk>;
428 clk-gate = <0xa0 5>;
429 div-reg = <0xa4 9 3>;
430 };
431
432 gpio_db_clk: gpio_db_clk {
433 #clock-cells = <0>;
434 compatible = "altr,socfpga-gate-clk";
435 clocks = <&per_base_clk>;
436 clk-gate = <0xa0 6>;
437 div-reg = <0xa8 0 24>;
438 };
439
440 h2f_user1_clk: h2f_user1_clk {
441 #clock-cells = <0>;
442 compatible = "altr,socfpga-gate-clk";
443 clocks = <&h2f_usr1_clk>;
444 clk-gate = <0xa0 7>;
445 };
446
447 sdmmc_clk: sdmmc_clk {
448 #clock-cells = <0>;
449 compatible = "altr,socfpga-gate-clk";
450 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
451 clk-gate = <0xa0 8>;
452 clk-phase = <0 135>;
453 };
454
455 sdmmc_clk_divided: sdmmc_clk_divided {
456 #clock-cells = <0>;
457 compatible = "altr,socfpga-gate-clk";
458 clocks = <&sdmmc_clk>;
459 clk-gate = <0xa0 8>;
460 fixed-divider = <4>;
461 };
462
463 nand_x_clk: nand_x_clk {
464 #clock-cells = <0>;
465 compatible = "altr,socfpga-gate-clk";
466 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
467 clk-gate = <0xa0 9>;
468 };
469
470 nand_clk: nand_clk {
471 #clock-cells = <0>;
472 compatible = "altr,socfpga-gate-clk";
473 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
474 clk-gate = <0xa0 10>;
475 fixed-divider = <4>;
476 };
477
478 qspi_clk: qspi_clk {
479 #clock-cells = <0>;
480 compatible = "altr,socfpga-gate-clk";
481 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
482 clk-gate = <0xa0 11>;
483 };
484
485 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
486 #clock-cells = <0>;
487 compatible = "altr,socfpga-gate-clk";
488 clocks = <&ddr_dqs_clk>;
489 clk-gate = <0xd8 0>;
490 };
491
492 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
493 #clock-cells = <0>;
494 compatible = "altr,socfpga-gate-clk";
495 clocks = <&ddr_2x_dqs_clk>;
496 clk-gate = <0xd8 1>;
497 };
498
499 ddr_dq_clk_gate: ddr_dq_clk_gate {
500 #clock-cells = <0>;
501 compatible = "altr,socfpga-gate-clk";
502 clocks = <&ddr_dq_clk>;
503 clk-gate = <0xd8 2>;
504 };
505
506 h2f_user2_clk: h2f_user2_clk {
507 #clock-cells = <0>;
508 compatible = "altr,socfpga-gate-clk";
509 clocks = <&h2f_usr2_clk>;
510 clk-gate = <0xd8 3>;
511 };
512
513 };
514 };
515
516 fpgamgr0: fpgamgr@ff706000 {
517 compatible = "altr,socfpga-fpga-mgr";
518 reg = <0xff706000 0x1000
519 0xffb90000 0x1000>;
520 interrupts = <0 175 4>;
521 };
522
523 gmac0: ethernet@ff700000 {
524 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
525 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
526 reg = <0xff700000 0x2000>;
527 interrupts = <0 115 4>;
528 interrupt-names = "macirq";
529 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
530 clocks = <&emac0_clk>;
531 clock-names = "stmmaceth";
532 resets = <&rst EMAC0_RESET>;
533 reset-names = "stmmaceth";
534 snps,multicast-filter-bins = <256>;
535 snps,perfect-filter-entries = <128>;
536 tx-fifo-depth = <4096>;
537 rx-fifo-depth = <4096>;
538 status = "disabled";
539 };
540
541 gmac1: ethernet@ff702000 {
542 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
543 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
544 reg = <0xff702000 0x2000>;
545 interrupts = <0 120 4>;
546 interrupt-names = "macirq";
547 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
548 clocks = <&emac1_clk>;
549 clock-names = "stmmaceth";
550 resets = <&rst EMAC1_RESET>;
551 reset-names = "stmmaceth";
552 snps,multicast-filter-bins = <256>;
553 snps,perfect-filter-entries = <128>;
554 tx-fifo-depth = <4096>;
555 rx-fifo-depth = <4096>;
556 status = "disabled";
557 };
558
559 gpio0: gpio@ff708000 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "snps,dw-apb-gpio";
563 reg = <0xff708000 0x1000>;
564 clocks = <&l4_mp_clk>;
565 status = "disabled";
566
567 porta: gpio-controller@0 {
568 compatible = "snps,dw-apb-gpio-port";
569 gpio-controller;
570 #gpio-cells = <2>;
571 snps,nr-gpios = <29>;
572 reg = <0>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 interrupts = <0 164 4>;
576 };
577 };
578
579 gpio1: gpio@ff709000 {
580 #address-cells = <1>;
581 #size-cells = <0>;
582 compatible = "snps,dw-apb-gpio";
583 reg = <0xff709000 0x1000>;
584 clocks = <&l4_mp_clk>;
585 status = "disabled";
586
587 portb: gpio-controller@0 {
588 compatible = "snps,dw-apb-gpio-port";
589 gpio-controller;
590 #gpio-cells = <2>;
591 snps,nr-gpios = <29>;
592 reg = <0>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 interrupts = <0 165 4>;
596 };
597 };
598
599 gpio2: gpio@ff70a000 {
600 #address-cells = <1>;
601 #size-cells = <0>;
602 compatible = "snps,dw-apb-gpio";
603 reg = <0xff70a000 0x1000>;
604 clocks = <&l4_mp_clk>;
605 status = "disabled";
606
607 portc: gpio-controller@0 {
608 compatible = "snps,dw-apb-gpio-port";
609 gpio-controller;
610 #gpio-cells = <2>;
611 snps,nr-gpios = <27>;
612 reg = <0>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 interrupts = <0 166 4>;
616 };
617 };
618
619 i2c0: i2c@ffc04000 {
620 #address-cells = <1>;
621 #size-cells = <0>;
622 compatible = "snps,designware-i2c";
623 reg = <0xffc04000 0x1000>;
624 clocks = <&l4_sp_clk>;
625 interrupts = <0 158 0x4>;
626 status = "disabled";
627 };
628
629 i2c1: i2c@ffc05000 {
630 #address-cells = <1>;
631 #size-cells = <0>;
632 compatible = "snps,designware-i2c";
633 reg = <0xffc05000 0x1000>;
634 clocks = <&l4_sp_clk>;
635 interrupts = <0 159 0x4>;
636 status = "disabled";
637 };
638
639 i2c2: i2c@ffc06000 {
640 #address-cells = <1>;
641 #size-cells = <0>;
642 compatible = "snps,designware-i2c";
643 reg = <0xffc06000 0x1000>;
644 clocks = <&l4_sp_clk>;
645 interrupts = <0 160 0x4>;
646 status = "disabled";
647 };
648
649 i2c3: i2c@ffc07000 {
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "snps,designware-i2c";
653 reg = <0xffc07000 0x1000>;
654 clocks = <&l4_sp_clk>;
655 interrupts = <0 161 0x4>;
656 status = "disabled";
657 };
658
659 eccmgr: eccmgr@ffd08140 {
660 compatible = "altr,socfpga-ecc-manager";
661 #address-cells = <1>;
662 #size-cells = <1>;
663 ranges;
664
665 l2-ecc@ffd08140 {
666 compatible = "altr,socfpga-l2-ecc";
667 reg = <0xffd08140 0x4>;
668 interrupts = <0 36 1>, <0 37 1>;
669 };
670
671 ocram-ecc@ffd08144 {
672 compatible = "altr,socfpga-ocram-ecc";
673 reg = <0xffd08144 0x4>;
674 iram = <&ocram>;
675 interrupts = <0 178 1>, <0 179 1>;
676 };
677 };
678
679 L2: l2-cache@fffef000 {
680 compatible = "arm,pl310-cache";
681 reg = <0xfffef000 0x1000>;
682 interrupts = <0 38 0x04>;
683 cache-unified;
684 cache-level = <2>;
685 arm,tag-latency = <1 1 1>;
686 arm,data-latency = <2 1 1>;
687 prefetch-data = <1>;
688 prefetch-instr = <1>;
689 arm,shared-override;
690 arm,double-linefill = <1>;
691 arm,double-linefill-incr = <0>;
692 arm,double-linefill-wrap = <1>;
693 arm,prefetch-drop = <0>;
694 arm,prefetch-offset = <7>;
695 };
696
697 mmc: dwmmc0@ff704000 {
698 compatible = "altr,socfpga-dw-mshc";
699 reg = <0xff704000 0x1000>;
700 interrupts = <0 139 4>;
701 fifo-depth = <0x400>;
702 #address-cells = <1>;
703 #size-cells = <0>;
704 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
705 clock-names = "biu", "ciu";
706 status = "disabled";
707 };
708
709 nand0: nand@ff900000 {
710 #address-cells = <0x1>;
711 #size-cells = <0x1>;
712 compatible = "denali,denali-nand-dt";
713 reg = <0xff900000 0x100000>,
714 <0xffb80000 0x10000>;
715 reg-names = "nand_data", "denali_reg";
716 interrupts = <0x0 0x90 0x4>;
717 dma-mask = <0xffffffff>;
718 clocks = <&nand_clk>;
719 status = "disabled";
720 };
721
722 ocram: sram@ffff0000 {
723 compatible = "mmio-sram";
724 reg = <0xffff0000 0x10000>;
725 };
726
727 qspi: spi@ff705000 {
728 compatible = "cdns,qspi-nor";
729 #address-cells = <1>;
730 #size-cells = <0>;
731 reg = <0xff705000 0x1000>,
732 <0xffa00000 0x1000>;
733 interrupts = <0 151 4>;
734 cdns,fifo-depth = <128>;
735 cdns,fifo-width = <4>;
736 cdns,trigger-address = <0x00000000>;
737 clocks = <&qspi_clk>;
738 status = "disabled";
739 };
740
741 rst: rstmgr@ffd05000 {
742 #reset-cells = <1>;
743 compatible = "altr,rst-mgr";
744 reg = <0xffd05000 0x1000>;
745 altr,modrst-offset = <0x10>;
746 };
747
748 scu: snoop-control-unit@fffec000 {
749 compatible = "arm,cortex-a9-scu";
750 reg = <0xfffec000 0x100>;
751 };
752
753 sdr: sdr@ffc25000 {
754 compatible = "syscon";
755 reg = <0xffc25000 0x1000>;
756 };
757
758 sdramedac {
759 compatible = "altr,sdram-edac";
760 altr,sdr-syscon = <&sdr>;
761 interrupts = <0 39 4>;
762 };
763
764 spi0: spi@fff00000 {
765 compatible = "snps,dw-apb-ssi";
766 #address-cells = <1>;
767 #size-cells = <0>;
768 reg = <0xfff00000 0x1000>;
769 interrupts = <0 154 4>;
770 num-cs = <4>;
771 clocks = <&spi_m_clk>;
772 status = "disabled";
773 };
774
775 spi1: spi@fff01000 {
776 compatible = "snps,dw-apb-ssi";
777 #address-cells = <1>;
778 #size-cells = <0>;
779 reg = <0xfff01000 0x1000>;
780 interrupts = <0 155 4>;
781 num-cs = <4>;
782 clocks = <&spi_m_clk>;
783 status = "disabled";
784 };
785
786 sysmgr: sysmgr@ffd08000 {
787 compatible = "altr,sys-mgr", "syscon";
788 reg = <0xffd08000 0x4000>;
789 };
790
791 /* Local timer */
792 timer@fffec600 {
793 compatible = "arm,cortex-a9-twd-timer";
794 reg = <0xfffec600 0x100>;
795 interrupts = <1 13 0xf04>;
796 clocks = <&mpu_periph_clk>;
797 };
798
799 timer0: timer0@ffc08000 {
800 compatible = "snps,dw-apb-timer";
801 interrupts = <0 167 4>;
802 reg = <0xffc08000 0x1000>;
803 clocks = <&l4_sp_clk>;
804 clock-names = "timer";
805 };
806
807 timer1: timer1@ffc09000 {
808 compatible = "snps,dw-apb-timer";
809 interrupts = <0 168 4>;
810 reg = <0xffc09000 0x1000>;
811 clocks = <&l4_sp_clk>;
812 clock-names = "timer";
813 };
814
815 timer2: timer2@ffd00000 {
816 compatible = "snps,dw-apb-timer";
817 interrupts = <0 169 4>;
818 reg = <0xffd00000 0x1000>;
819 clocks = <&osc1>;
820 clock-names = "timer";
821 };
822
823 timer3: timer3@ffd01000 {
824 compatible = "snps,dw-apb-timer";
825 interrupts = <0 170 4>;
826 reg = <0xffd01000 0x1000>;
827 clocks = <&osc1>;
828 clock-names = "timer";
829 };
830
831 uart0: serial0@ffc02000 {
832 compatible = "snps,dw-apb-uart";
833 reg = <0xffc02000 0x1000>;
834 interrupts = <0 162 4>;
835 reg-shift = <2>;
836 reg-io-width = <4>;
837 clocks = <&l4_sp_clk>;
838 dmas = <&pdma 28>,
839 <&pdma 29>;
840 dma-names = "tx", "rx";
841 };
842
843 uart1: serial1@ffc03000 {
844 compatible = "snps,dw-apb-uart";
845 reg = <0xffc03000 0x1000>;
846 interrupts = <0 163 4>;
847 reg-shift = <2>;
848 reg-io-width = <4>;
849 clocks = <&l4_sp_clk>;
850 dmas = <&pdma 30>,
851 <&pdma 31>;
852 dma-names = "tx", "rx";
853 };
854
855 usbphy0: usbphy@0 {
856 #phy-cells = <0>;
857 compatible = "usb-nop-xceiv";
858 status = "okay";
859 };
860
861 usb0: usb@ffb00000 {
862 compatible = "snps,dwc2";
863 reg = <0xffb00000 0xffff>;
864 interrupts = <0 125 4>;
865 clocks = <&usb_mp_clk>;
866 clock-names = "otg";
867 resets = <&rst USB0_RESET>;
868 reset-names = "dwc2";
869 phys = <&usbphy0>;
870 phy-names = "usb2-phy";
871 status = "disabled";
872 };
873
874 usb1: usb@ffb40000 {
875 compatible = "snps,dwc2";
876 reg = <0xffb40000 0xffff>;
877 interrupts = <0 128 4>;
878 clocks = <&usb_mp_clk>;
879 clock-names = "otg";
880 resets = <&rst USB1_RESET>;
881 reset-names = "dwc2";
882 phys = <&usbphy0>;
883 phy-names = "usb2-phy";
884 status = "disabled";
885 };
886
887 watchdog0: watchdog@ffd02000 {
888 compatible = "snps,dw-wdt";
889 reg = <0xffd02000 0x1000>;
890 interrupts = <0 171 4>;
891 clocks = <&osc1>;
892 status = "disabled";
893 };
894
895 watchdog1: watchdog@ffd03000 {
896 compatible = "snps,dw-wdt";
897 reg = <0xffd03000 0x1000>;
898 interrupts = <0 172 4>;
899 clocks = <&osc1>;
900 status = "disabled";
901 };
902 };
903};