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1/*
2 * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include "pxa2xx.dtsi"
12#include "dt-bindings/clock/pxa-clock.h"
13
14/ {
15 model = "Marvell PXA25x family SoC";
16 compatible = "marvell,pxa250";
17
18 clocks {
19 /*
20 * The muxing of external clocks/internal dividers for osc* clock
21 * sources has been hidden under the carpet by now.
22 */
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 clks: pxa2xx_clks@41300004 {
28 compatible = "marvell,pxa250-core-clocks";
29 #clock-cells = <1>;
30 status = "okay";
31 };
32
33 /* timer oscillator */
34 clktimer: oscillator {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <3686400>;
38 clock-output-names = "ostimer";
39 };
40 };
41
42 pxabus {
43 pdma: dma-controller@40000000 {
44 compatible = "marvell,pdma-1.0";
45 reg = <0x40000000 0x10000>;
46 interrupts = <25>;
47 #dma-channels = <16>;
48 #dma-cells = <2>;
49 #dma-requests = <40>;
50 status = "okay";
51 };
52
53 pxairq: interrupt-controller@40d00000 {
54 marvell,intc-priority;
55 marvell,intc-nr-irqs = <32>;
56 };
57
58 pinctrl: pinctrl@40e00000 {
59 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
60 0x40f00020 0x10>;
61 compatible = "marvell,pxa25x-pinctrl";
62 };
63
64 gpio: gpio@40e00000 {
65 compatible = "intel,pxa25x-gpio";
66 gpio-ranges = <&pinctrl 0 0 84>;
67 clocks = <&clks CLK_NONE>;
68 };
69
70 pwm0: pwm@40b00000 {
71 compatible = "marvell,pxa250-pwm";
72 reg = <0x40b00000 0x10>;
73 #pwm-cells = <1>;
74 clocks = <&clks CLK_PWM0>;
75 };
76
77 pwm1: pwm@40b00010 {
78 compatible = "marvell,pxa250-pwm";
79 reg = <0x40b00010 0x10>;
80 #pwm-cells = <1>;
81 clocks = <&clks CLK_PWM1>;
82 };
83 };
84
85 timer@40a00000 {
86 compatible = "marvell,pxa-timer";
87 reg = <0x40a00000 0x20>;
88 interrupts = <26>;
89 clocks = <&clktimer>;
90 status = "okay";
91 };
92
93 pxa250_opp_table: opp_table0 {
94 compatible = "operating-points-v2";
95
96 opp-99532800 {
97 opp-hz = /bits/ 64 <99532800>;
98 opp-microvolt = <1000000 950000 1650000>;
99 clock-latency-ns = <20>;
100 };
101 opp-199065600 {
102 opp-hz = /bits/ 64 <199065600>;
103 opp-microvolt = <1000000 950000 1650000>;
104 clock-latency-ns = <20>;
105 };
106 opp-298598400 {
107 opp-hz = /bits/ 64 <298598400>;
108 opp-microvolt = <1100000 1045000 1650000>;
109 clock-latency-ns = <20>;
110 };
111 opp-398131200 {
112 opp-hz = /bits/ 64 <398131200>;
113 opp-microvolt = <1300000 1235000 1650000>;
114 clock-latency-ns = <20>;
115 };
116 };
117};
1/*
2 * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include "pxa2xx.dtsi"
12#include "dt-bindings/clock/pxa-clock.h"
13
14/ {
15 model = "Marvell PXA25x family SoC";
16 compatible = "marvell,pxa250";
17
18 clocks {
19 /*
20 * The muxing of external clocks/internal dividers for osc* clock
21 * sources has been hidden under the carpet by now.
22 */
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 clks: pxa2xx_clks@41300004 {
28 compatible = "marvell,pxa250-core-clocks";
29 #clock-cells = <1>;
30 status = "okay";
31 };
32
33 /* timer oscillator */
34 clktimer: oscillator {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <3686400>;
38 clock-output-names = "ostimer";
39 };
40 };
41
42 pxabus {
43 pdma: dma-controller@40000000 {
44 compatible = "marvell,pdma-1.0";
45 reg = <0x40000000 0x10000>;
46 interrupts = <25>;
47 #dma-channels = <16>;
48 #dma-cells = <2>;
49 #dma-requests = <40>;
50 status = "okay";
51 };
52
53 pxairq: interrupt-controller@40d00000 {
54 marvell,intc-priority;
55 marvell,intc-nr-irqs = <32>;
56 };
57
58 pinctrl: pinctrl@40e00000 {
59 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
60 0x40f00020 0x10>;
61 compatible = "marvell,pxa25x-pinctrl";
62 };
63
64 gpio: gpio@40e00000 {
65 compatible = "intel,pxa25x-gpio";
66 gpio-ranges = <&pinctrl 0 0 84>;
67 clocks = <&clks CLK_NONE>;
68 };
69
70 pwm0: pwm@40b00000 {
71 compatible = "marvell,pxa250-pwm";
72 reg = <0x40b00000 0x10>;
73 #pwm-cells = <1>;
74 clocks = <&clks CLK_PWM0>;
75 };
76
77 pwm1: pwm@40b00010 {
78 compatible = "marvell,pxa250-pwm";
79 reg = <0x40b00010 0x10>;
80 #pwm-cells = <1>;
81 clocks = <&clks CLK_PWM1>;
82 };
83 };
84
85 timer@40a00000 {
86 compatible = "marvell,pxa-timer";
87 reg = <0x40a00000 0x20>;
88 interrupts = <26>;
89 clocks = <&clktimer>;
90 status = "okay";
91 };
92
93 pxa250_opp_table: opp_table0 {
94 compatible = "operating-points-v2";
95
96 opp@99532800 {
97 opp-hz = /bits/ 64 <99532800>;
98 opp-microvolt = <1000000 950000 1650000>;
99 clock-latency-ns = <20>;
100 };
101 opp@199065600 {
102 opp-hz = /bits/ 64 <199065600>;
103 opp-microvolt = <1000000 950000 1650000>;
104 clock-latency-ns = <20>;
105 };
106 opp@298598400 {
107 opp-hz = /bits/ 64 <298598400>;
108 opp-microvolt = <1100000 1045000 1650000>;
109 clock-latency-ns = <20>;
110 };
111 opp@398131200 {
112 opp-hz = /bits/ 64 <398131200>;
113 opp-microvolt = <1300000 1235000 1650000>;
114 clock-latency-ns = <20>;
115 };
116 };
117};