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1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/pinctrl/omap.h>
14
15/ {
16 compatible = "ti,omap3430", "ti,omap3";
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a8";
37 device_type = "cpu";
38 reg = <0x0>;
39
40 clocks = <&dpll1_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
44 };
45 };
46
47 pmu@54000000 {
48 compatible = "arm,cortex-a8-pmu";
49 reg = <0x54000000 0x800000>;
50 interrupts = <3>;
51 ti,hwmods = "debugss";
52 };
53
54 /*
55 * The soc node represents the soc top level view. It is used for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
57 */
58 soc {
59 compatible = "ti,omap-infra";
60 mpu {
61 compatible = "ti,omap3-mpu";
62 ti,hwmods = "mpu";
63 };
64
65 iva: iva {
66 compatible = "ti,iva2.2";
67 ti,hwmods = "iva";
68
69 dsp {
70 compatible = "ti,omap3-c64";
71 };
72 };
73 };
74
75 /*
76 * XXX: Use a flat representation of the OMAP3 interconnect.
77 * The real OMAP interconnect network is quite complex.
78 * Since it will not bring real advantage to represent that in DT for
79 * the moment, just use a fake OCP bus entry to represent the whole bus
80 * hierarchy.
81 */
82 ocp@68000000 {
83 compatible = "ti,omap3-l3-smx", "simple-bus";
84 reg = <0x68000000 0x10000>;
85 interrupts = <9 10>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 ti,hwmods = "l3_main";
90
91 l4_core: l4@48000000 {
92 compatible = "ti,omap3-l4-core", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x48000000 0x1000000>;
96
97 scm: scm@2000 {
98 compatible = "ti,omap3-scm", "simple-bus";
99 reg = <0x2000 0x2000>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 0x2000 0x2000>;
103
104 omap3_pmx_core: pinmux@30 {
105 compatible = "ti,omap3-padconf",
106 "pinctrl-single";
107 reg = <0x30 0x238>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 #pinctrl-cells = <1>;
111 #interrupt-cells = <1>;
112 interrupt-controller;
113 pinctrl-single,register-width = <16>;
114 pinctrl-single,function-mask = <0xff1f>;
115 };
116
117 scm_conf: scm_conf@270 {
118 compatible = "syscon", "simple-bus";
119 reg = <0x270 0x330>;
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0 0x270 0x330>;
123
124 pbias_regulator: pbias_regulator@2b0 {
125 compatible = "ti,pbias-omap3", "ti,pbias-omap";
126 reg = <0x2b0 0x4>;
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap2430 {
129 regulator-name = "pbias_mmc_omap2430";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
132 };
133 };
134
135 scm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139 };
140
141 scm_clockdomains: clockdomains {
142 };
143
144 omap3_pmx_wkup: pinmux@a00 {
145 compatible = "ti,omap3-padconf",
146 "pinctrl-single";
147 reg = <0xa00 0x5c>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 #pinctrl-cells = <1>;
151 #interrupt-cells = <1>;
152 interrupt-controller;
153 pinctrl-single,register-width = <16>;
154 pinctrl-single,function-mask = <0xff1f>;
155 };
156 };
157 };
158
159 aes: aes@480c5000 {
160 compatible = "ti,omap3-aes";
161 ti,hwmods = "aes";
162 reg = <0x480c5000 0x50>;
163 interrupts = <0>;
164 dmas = <&sdma 65 &sdma 66>;
165 dma-names = "tx", "rx";
166 };
167
168 prm: prm@48306000 {
169 compatible = "ti,omap3-prm";
170 reg = <0x48306000 0x4000>;
171 interrupts = <11>;
172
173 prm_clocks: clocks {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 };
177
178 prm_clockdomains: clockdomains {
179 };
180 };
181
182 cm: cm@48004000 {
183 compatible = "ti,omap3-cm";
184 reg = <0x48004000 0x4000>;
185
186 cm_clocks: clocks {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 };
190
191 cm_clockdomains: clockdomains {
192 };
193 };
194
195 counter32k: counter@48320000 {
196 compatible = "ti,omap-counter32k";
197 reg = <0x48320000 0x20>;
198 ti,hwmods = "counter_32k";
199 };
200
201 intc: interrupt-controller@48200000 {
202 compatible = "ti,omap3-intc";
203 interrupt-controller;
204 #interrupt-cells = <1>;
205 reg = <0x48200000 0x1000>;
206 };
207
208 sdma: dma-controller@48056000 {
209 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
210 reg = <0x48056000 0x1000>;
211 interrupts = <12>,
212 <13>,
213 <14>,
214 <15>;
215 #dma-cells = <1>;
216 dma-channels = <32>;
217 dma-requests = <96>;
218 ti,hwmods = "dma";
219 };
220
221 gpio1: gpio@48310000 {
222 compatible = "ti,omap3-gpio";
223 reg = <0x48310000 0x200>;
224 interrupts = <29>;
225 ti,hwmods = "gpio1";
226 ti,gpio-always-on;
227 gpio-controller;
228 #gpio-cells = <2>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 };
232
233 gpio2: gpio@49050000 {
234 compatible = "ti,omap3-gpio";
235 reg = <0x49050000 0x200>;
236 interrupts = <30>;
237 ti,hwmods = "gpio2";
238 gpio-controller;
239 #gpio-cells = <2>;
240 interrupt-controller;
241 #interrupt-cells = <2>;
242 };
243
244 gpio3: gpio@49052000 {
245 compatible = "ti,omap3-gpio";
246 reg = <0x49052000 0x200>;
247 interrupts = <31>;
248 ti,hwmods = "gpio3";
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 };
254
255 gpio4: gpio@49054000 {
256 compatible = "ti,omap3-gpio";
257 reg = <0x49054000 0x200>;
258 interrupts = <32>;
259 ti,hwmods = "gpio4";
260 gpio-controller;
261 #gpio-cells = <2>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 };
265
266 gpio5: gpio@49056000 {
267 compatible = "ti,omap3-gpio";
268 reg = <0x49056000 0x200>;
269 interrupts = <33>;
270 ti,hwmods = "gpio5";
271 gpio-controller;
272 #gpio-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276
277 gpio6: gpio@49058000 {
278 compatible = "ti,omap3-gpio";
279 reg = <0x49058000 0x200>;
280 interrupts = <34>;
281 ti,hwmods = "gpio6";
282 gpio-controller;
283 #gpio-cells = <2>;
284 interrupt-controller;
285 #interrupt-cells = <2>;
286 };
287
288 uart1: serial@4806a000 {
289 compatible = "ti,omap3-uart";
290 reg = <0x4806a000 0x2000>;
291 interrupts-extended = <&intc 72>;
292 dmas = <&sdma 49 &sdma 50>;
293 dma-names = "tx", "rx";
294 ti,hwmods = "uart1";
295 clock-frequency = <48000000>;
296 };
297
298 uart2: serial@4806c000 {
299 compatible = "ti,omap3-uart";
300 reg = <0x4806c000 0x400>;
301 interrupts-extended = <&intc 73>;
302 dmas = <&sdma 51 &sdma 52>;
303 dma-names = "tx", "rx";
304 ti,hwmods = "uart2";
305 clock-frequency = <48000000>;
306 };
307
308 uart3: serial@49020000 {
309 compatible = "ti,omap3-uart";
310 reg = <0x49020000 0x400>;
311 interrupts-extended = <&intc 74>;
312 dmas = <&sdma 53 &sdma 54>;
313 dma-names = "tx", "rx";
314 ti,hwmods = "uart3";
315 clock-frequency = <48000000>;
316 };
317
318 i2c1: i2c@48070000 {
319 compatible = "ti,omap3-i2c";
320 reg = <0x48070000 0x80>;
321 interrupts = <56>;
322 dmas = <&sdma 27 &sdma 28>;
323 dma-names = "tx", "rx";
324 #address-cells = <1>;
325 #size-cells = <0>;
326 ti,hwmods = "i2c1";
327 };
328
329 i2c2: i2c@48072000 {
330 compatible = "ti,omap3-i2c";
331 reg = <0x48072000 0x80>;
332 interrupts = <57>;
333 dmas = <&sdma 29 &sdma 30>;
334 dma-names = "tx", "rx";
335 #address-cells = <1>;
336 #size-cells = <0>;
337 ti,hwmods = "i2c2";
338 };
339
340 i2c3: i2c@48060000 {
341 compatible = "ti,omap3-i2c";
342 reg = <0x48060000 0x80>;
343 interrupts = <61>;
344 dmas = <&sdma 25 &sdma 26>;
345 dma-names = "tx", "rx";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 ti,hwmods = "i2c3";
349 };
350
351 mailbox: mailbox@48094000 {
352 compatible = "ti,omap3-mailbox";
353 ti,hwmods = "mailbox";
354 reg = <0x48094000 0x200>;
355 interrupts = <26>;
356 #mbox-cells = <1>;
357 ti,mbox-num-users = <2>;
358 ti,mbox-num-fifos = <2>;
359 mbox_dsp: dsp {
360 ti,mbox-tx = <0 0 0>;
361 ti,mbox-rx = <1 0 0>;
362 };
363 };
364
365 mcspi1: spi@48098000 {
366 compatible = "ti,omap2-mcspi";
367 reg = <0x48098000 0x100>;
368 interrupts = <65>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 ti,hwmods = "mcspi1";
372 ti,spi-num-cs = <4>;
373 dmas = <&sdma 35>,
374 <&sdma 36>,
375 <&sdma 37>,
376 <&sdma 38>,
377 <&sdma 39>,
378 <&sdma 40>,
379 <&sdma 41>,
380 <&sdma 42>;
381 dma-names = "tx0", "rx0", "tx1", "rx1",
382 "tx2", "rx2", "tx3", "rx3";
383 };
384
385 mcspi2: spi@4809a000 {
386 compatible = "ti,omap2-mcspi";
387 reg = <0x4809a000 0x100>;
388 interrupts = <66>;
389 #address-cells = <1>;
390 #size-cells = <0>;
391 ti,hwmods = "mcspi2";
392 ti,spi-num-cs = <2>;
393 dmas = <&sdma 43>,
394 <&sdma 44>,
395 <&sdma 45>,
396 <&sdma 46>;
397 dma-names = "tx0", "rx0", "tx1", "rx1";
398 };
399
400 mcspi3: spi@480b8000 {
401 compatible = "ti,omap2-mcspi";
402 reg = <0x480b8000 0x100>;
403 interrupts = <91>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 ti,hwmods = "mcspi3";
407 ti,spi-num-cs = <2>;
408 dmas = <&sdma 15>,
409 <&sdma 16>,
410 <&sdma 23>,
411 <&sdma 24>;
412 dma-names = "tx0", "rx0", "tx1", "rx1";
413 };
414
415 mcspi4: spi@480ba000 {
416 compatible = "ti,omap2-mcspi";
417 reg = <0x480ba000 0x100>;
418 interrupts = <48>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 ti,hwmods = "mcspi4";
422 ti,spi-num-cs = <1>;
423 dmas = <&sdma 70>, <&sdma 71>;
424 dma-names = "tx0", "rx0";
425 };
426
427 hdqw1w: 1w@480b2000 {
428 compatible = "ti,omap3-1w";
429 reg = <0x480b2000 0x1000>;
430 interrupts = <58>;
431 ti,hwmods = "hdq1w";
432 };
433
434 mmc1: mmc@4809c000 {
435 compatible = "ti,omap3-hsmmc";
436 reg = <0x4809c000 0x200>;
437 interrupts = <83>;
438 ti,hwmods = "mmc1";
439 ti,dual-volt;
440 dmas = <&sdma 61>, <&sdma 62>;
441 dma-names = "tx", "rx";
442 pbias-supply = <&pbias_mmc_reg>;
443 };
444
445 mmc2: mmc@480b4000 {
446 compatible = "ti,omap3-hsmmc";
447 reg = <0x480b4000 0x200>;
448 interrupts = <86>;
449 ti,hwmods = "mmc2";
450 dmas = <&sdma 47>, <&sdma 48>;
451 dma-names = "tx", "rx";
452 };
453
454 mmc3: mmc@480ad000 {
455 compatible = "ti,omap3-hsmmc";
456 reg = <0x480ad000 0x200>;
457 interrupts = <94>;
458 ti,hwmods = "mmc3";
459 dmas = <&sdma 77>, <&sdma 78>;
460 dma-names = "tx", "rx";
461 };
462
463 mmu_isp: mmu@480bd400 {
464 #iommu-cells = <0>;
465 compatible = "ti,omap2-iommu";
466 reg = <0x480bd400 0x80>;
467 interrupts = <24>;
468 ti,hwmods = "mmu_isp";
469 ti,#tlb-entries = <8>;
470 };
471
472 mmu_iva: mmu@5d000000 {
473 #iommu-cells = <0>;
474 compatible = "ti,omap2-iommu";
475 reg = <0x5d000000 0x80>;
476 interrupts = <28>;
477 ti,hwmods = "mmu_iva";
478 status = "disabled";
479 };
480
481 wdt2: wdt@48314000 {
482 compatible = "ti,omap3-wdt";
483 reg = <0x48314000 0x80>;
484 ti,hwmods = "wd_timer2";
485 };
486
487 mcbsp1: mcbsp@48074000 {
488 compatible = "ti,omap3-mcbsp";
489 reg = <0x48074000 0xff>;
490 reg-names = "mpu";
491 interrupts = <16>, /* OCP compliant interrupt */
492 <59>, /* TX interrupt */
493 <60>; /* RX interrupt */
494 interrupt-names = "common", "tx", "rx";
495 ti,buffer-size = <128>;
496 ti,hwmods = "mcbsp1";
497 dmas = <&sdma 31>,
498 <&sdma 32>;
499 dma-names = "tx", "rx";
500 clocks = <&mcbsp1_fck>;
501 clock-names = "fck";
502 status = "disabled";
503 };
504
505 mcbsp2: mcbsp@49022000 {
506 compatible = "ti,omap3-mcbsp";
507 reg = <0x49022000 0xff>,
508 <0x49028000 0xff>;
509 reg-names = "mpu", "sidetone";
510 interrupts = <17>, /* OCP compliant interrupt */
511 <62>, /* TX interrupt */
512 <63>, /* RX interrupt */
513 <4>; /* Sidetone */
514 interrupt-names = "common", "tx", "rx", "sidetone";
515 ti,buffer-size = <1280>;
516 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
517 dmas = <&sdma 33>,
518 <&sdma 34>;
519 dma-names = "tx", "rx";
520 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
521 clock-names = "fck", "ick";
522 status = "disabled";
523 };
524
525 mcbsp3: mcbsp@49024000 {
526 compatible = "ti,omap3-mcbsp";
527 reg = <0x49024000 0xff>,
528 <0x4902a000 0xff>;
529 reg-names = "mpu", "sidetone";
530 interrupts = <22>, /* OCP compliant interrupt */
531 <89>, /* TX interrupt */
532 <90>, /* RX interrupt */
533 <5>; /* Sidetone */
534 interrupt-names = "common", "tx", "rx", "sidetone";
535 ti,buffer-size = <128>;
536 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
537 dmas = <&sdma 17>,
538 <&sdma 18>;
539 dma-names = "tx", "rx";
540 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
541 clock-names = "fck", "ick";
542 status = "disabled";
543 };
544
545 mcbsp4: mcbsp@49026000 {
546 compatible = "ti,omap3-mcbsp";
547 reg = <0x49026000 0xff>;
548 reg-names = "mpu";
549 interrupts = <23>, /* OCP compliant interrupt */
550 <54>, /* TX interrupt */
551 <55>; /* RX interrupt */
552 interrupt-names = "common", "tx", "rx";
553 ti,buffer-size = <128>;
554 ti,hwmods = "mcbsp4";
555 dmas = <&sdma 19>,
556 <&sdma 20>;
557 dma-names = "tx", "rx";
558 clocks = <&mcbsp4_fck>;
559 clock-names = "fck";
560 #sound-dai-cells = <0>;
561 status = "disabled";
562 };
563
564 mcbsp5: mcbsp@48096000 {
565 compatible = "ti,omap3-mcbsp";
566 reg = <0x48096000 0xff>;
567 reg-names = "mpu";
568 interrupts = <27>, /* OCP compliant interrupt */
569 <81>, /* TX interrupt */
570 <82>; /* RX interrupt */
571 interrupt-names = "common", "tx", "rx";
572 ti,buffer-size = <128>;
573 ti,hwmods = "mcbsp5";
574 dmas = <&sdma 21>,
575 <&sdma 22>;
576 dma-names = "tx", "rx";
577 clocks = <&mcbsp5_fck>;
578 clock-names = "fck";
579 status = "disabled";
580 };
581
582 sham: sham@480c3000 {
583 compatible = "ti,omap3-sham";
584 ti,hwmods = "sham";
585 reg = <0x480c3000 0x64>;
586 interrupts = <49>;
587 dmas = <&sdma 69>;
588 dma-names = "rx";
589 };
590
591 timer1: timer@48318000 {
592 compatible = "ti,omap3430-timer";
593 reg = <0x48318000 0x400>;
594 interrupts = <37>;
595 ti,hwmods = "timer1";
596 ti,timer-alwon;
597 };
598
599 timer2: timer@49032000 {
600 compatible = "ti,omap3430-timer";
601 reg = <0x49032000 0x400>;
602 interrupts = <38>;
603 ti,hwmods = "timer2";
604 };
605
606 timer3: timer@49034000 {
607 compatible = "ti,omap3430-timer";
608 reg = <0x49034000 0x400>;
609 interrupts = <39>;
610 ti,hwmods = "timer3";
611 };
612
613 timer4: timer@49036000 {
614 compatible = "ti,omap3430-timer";
615 reg = <0x49036000 0x400>;
616 interrupts = <40>;
617 ti,hwmods = "timer4";
618 };
619
620 timer5: timer@49038000 {
621 compatible = "ti,omap3430-timer";
622 reg = <0x49038000 0x400>;
623 interrupts = <41>;
624 ti,hwmods = "timer5";
625 ti,timer-dsp;
626 };
627
628 timer6: timer@4903a000 {
629 compatible = "ti,omap3430-timer";
630 reg = <0x4903a000 0x400>;
631 interrupts = <42>;
632 ti,hwmods = "timer6";
633 ti,timer-dsp;
634 };
635
636 timer7: timer@4903c000 {
637 compatible = "ti,omap3430-timer";
638 reg = <0x4903c000 0x400>;
639 interrupts = <43>;
640 ti,hwmods = "timer7";
641 ti,timer-dsp;
642 };
643
644 timer8: timer@4903e000 {
645 compatible = "ti,omap3430-timer";
646 reg = <0x4903e000 0x400>;
647 interrupts = <44>;
648 ti,hwmods = "timer8";
649 ti,timer-pwm;
650 ti,timer-dsp;
651 };
652
653 timer9: timer@49040000 {
654 compatible = "ti,omap3430-timer";
655 reg = <0x49040000 0x400>;
656 interrupts = <45>;
657 ti,hwmods = "timer9";
658 ti,timer-pwm;
659 };
660
661 timer10: timer@48086000 {
662 compatible = "ti,omap3430-timer";
663 reg = <0x48086000 0x400>;
664 interrupts = <46>;
665 ti,hwmods = "timer10";
666 ti,timer-pwm;
667 };
668
669 timer11: timer@48088000 {
670 compatible = "ti,omap3430-timer";
671 reg = <0x48088000 0x400>;
672 interrupts = <47>;
673 ti,hwmods = "timer11";
674 ti,timer-pwm;
675 };
676
677 timer12: timer@48304000 {
678 compatible = "ti,omap3430-timer";
679 reg = <0x48304000 0x400>;
680 interrupts = <95>;
681 ti,hwmods = "timer12";
682 ti,timer-alwon;
683 ti,timer-secure;
684 };
685
686 usbhstll: usbhstll@48062000 {
687 compatible = "ti,usbhs-tll";
688 reg = <0x48062000 0x1000>;
689 interrupts = <78>;
690 ti,hwmods = "usb_tll_hs";
691 };
692
693 usbhshost: usbhshost@48064000 {
694 compatible = "ti,usbhs-host";
695 reg = <0x48064000 0x400>;
696 ti,hwmods = "usb_host_hs";
697 #address-cells = <1>;
698 #size-cells = <1>;
699 ranges;
700
701 usbhsohci: ohci@48064400 {
702 compatible = "ti,ohci-omap3";
703 reg = <0x48064400 0x400>;
704 interrupts = <76>;
705 remote-wakeup-connected;
706 };
707
708 usbhsehci: ehci@48064800 {
709 compatible = "ti,ehci-omap";
710 reg = <0x48064800 0x400>;
711 interrupts = <77>;
712 };
713 };
714
715 gpmc: gpmc@6e000000 {
716 compatible = "ti,omap3430-gpmc";
717 ti,hwmods = "gpmc";
718 reg = <0x6e000000 0x02d0>;
719 interrupts = <20>;
720 dmas = <&sdma 4>;
721 dma-names = "rxtx";
722 gpmc,num-cs = <8>;
723 gpmc,num-waitpins = <4>;
724 #address-cells = <2>;
725 #size-cells = <1>;
726 interrupt-controller;
727 #interrupt-cells = <2>;
728 gpio-controller;
729 #gpio-cells = <2>;
730 };
731
732 usb_otg_hs: usb_otg_hs@480ab000 {
733 compatible = "ti,omap3-musb";
734 reg = <0x480ab000 0x1000>;
735 interrupts = <92>, <93>;
736 interrupt-names = "mc", "dma";
737 ti,hwmods = "usb_otg_hs";
738 multipoint = <1>;
739 num-eps = <16>;
740 ram-bits = <12>;
741 };
742
743 dss: dss@48050000 {
744 compatible = "ti,omap3-dss";
745 reg = <0x48050000 0x200>;
746 status = "disabled";
747 ti,hwmods = "dss_core";
748 clocks = <&dss1_alwon_fck>;
749 clock-names = "fck";
750 #address-cells = <1>;
751 #size-cells = <1>;
752 ranges;
753
754 dispc@48050400 {
755 compatible = "ti,omap3-dispc";
756 reg = <0x48050400 0x400>;
757 interrupts = <25>;
758 ti,hwmods = "dss_dispc";
759 clocks = <&dss1_alwon_fck>;
760 clock-names = "fck";
761 };
762
763 dsi: encoder@4804fc00 {
764 compatible = "ti,omap3-dsi";
765 reg = <0x4804fc00 0x200>,
766 <0x4804fe00 0x40>,
767 <0x4804ff00 0x20>;
768 reg-names = "proto", "phy", "pll";
769 interrupts = <25>;
770 status = "disabled";
771 ti,hwmods = "dss_dsi1";
772 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
773 clock-names = "fck", "sys_clk";
774 };
775
776 rfbi: encoder@48050800 {
777 compatible = "ti,omap3-rfbi";
778 reg = <0x48050800 0x100>;
779 status = "disabled";
780 ti,hwmods = "dss_rfbi";
781 clocks = <&dss1_alwon_fck>, <&dss_ick>;
782 clock-names = "fck", "ick";
783 };
784
785 venc: encoder@48050c00 {
786 compatible = "ti,omap3-venc";
787 reg = <0x48050c00 0x100>;
788 status = "disabled";
789 ti,hwmods = "dss_venc";
790 clocks = <&dss_tv_fck>;
791 clock-names = "fck";
792 };
793 };
794
795 ssi: ssi-controller@48058000 {
796 compatible = "ti,omap3-ssi";
797 ti,hwmods = "ssi";
798
799 status = "disabled";
800
801 reg = <0x48058000 0x1000>,
802 <0x48059000 0x1000>;
803 reg-names = "sys",
804 "gdd";
805
806 interrupts = <71>;
807 interrupt-names = "gdd_mpu";
808
809 #address-cells = <1>;
810 #size-cells = <1>;
811 ranges;
812
813 ssi_port1: ssi-port@4805a000 {
814 compatible = "ti,omap3-ssi-port";
815
816 reg = <0x4805a000 0x800>,
817 <0x4805a800 0x800>;
818 reg-names = "tx",
819 "rx";
820
821 interrupts = <67>,
822 <68>;
823 };
824
825 ssi_port2: ssi-port@4805b000 {
826 compatible = "ti,omap3-ssi-port";
827
828 reg = <0x4805b000 0x800>,
829 <0x4805b800 0x800>;
830 reg-names = "tx",
831 "rx";
832
833 interrupts = <69>,
834 <70>;
835 };
836 };
837 };
838};
839
840/include/ "omap3xxx-clocks.dtsi"
1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/pinctrl/omap.h>
14
15/ {
16 compatible = "ti,omap3430", "ti,omap3";
17 interrupt-parent = <&intc>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a8";
37 device_type = "cpu";
38 reg = <0x0>;
39
40 clocks = <&dpll1_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
44 };
45 };
46
47 pmu@54000000 {
48 compatible = "arm,cortex-a8-pmu";
49 reg = <0x54000000 0x800000>;
50 interrupts = <3>;
51 ti,hwmods = "debugss";
52 };
53
54 /*
55 * The soc node represents the soc top level view. It is used for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
57 */
58 soc {
59 compatible = "ti,omap-infra";
60 mpu {
61 compatible = "ti,omap3-mpu";
62 ti,hwmods = "mpu";
63 };
64
65 iva: iva {
66 compatible = "ti,iva2.2";
67 ti,hwmods = "iva";
68
69 dsp {
70 compatible = "ti,omap3-c64";
71 };
72 };
73 };
74
75 /*
76 * XXX: Use a flat representation of the OMAP3 interconnect.
77 * The real OMAP interconnect network is quite complex.
78 * Since it will not bring real advantage to represent that in DT for
79 * the moment, just use a fake OCP bus entry to represent the whole bus
80 * hierarchy.
81 */
82 ocp@68000000 {
83 compatible = "ti,omap3-l3-smx", "simple-bus";
84 reg = <0x68000000 0x10000>;
85 interrupts = <9 10>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 ti,hwmods = "l3_main";
90
91 l4_core: l4@48000000 {
92 compatible = "ti,omap3-l4-core", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x48000000 0x1000000>;
96
97 scm: scm@2000 {
98 compatible = "ti,omap3-scm", "simple-bus";
99 reg = <0x2000 0x2000>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 0x2000 0x2000>;
103
104 omap3_pmx_core: pinmux@30 {
105 compatible = "ti,omap3-padconf",
106 "pinctrl-single";
107 reg = <0x30 0x238>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 #pinctrl-cells = <1>;
111 #interrupt-cells = <1>;
112 interrupt-controller;
113 pinctrl-single,register-width = <16>;
114 pinctrl-single,function-mask = <0xff1f>;
115 };
116
117 scm_conf: scm_conf@270 {
118 compatible = "syscon", "simple-bus";
119 reg = <0x270 0x330>;
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0 0x270 0x330>;
123
124 pbias_regulator: pbias_regulator@2b0 {
125 compatible = "ti,pbias-omap3", "ti,pbias-omap";
126 reg = <0x2b0 0x4>;
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap2430 {
129 regulator-name = "pbias_mmc_omap2430";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
132 };
133 };
134
135 scm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139 };
140
141 scm_clockdomains: clockdomains {
142 };
143
144 omap3_pmx_wkup: pinmux@a00 {
145 compatible = "ti,omap3-padconf",
146 "pinctrl-single";
147 reg = <0xa00 0x5c>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 #pinctrl-cells = <1>;
151 #interrupt-cells = <1>;
152 interrupt-controller;
153 pinctrl-single,register-width = <16>;
154 pinctrl-single,function-mask = <0xff1f>;
155 };
156 };
157 };
158
159 aes: aes@480c5000 {
160 compatible = "ti,omap3-aes";
161 ti,hwmods = "aes";
162 reg = <0x480c5000 0x50>;
163 interrupts = <0>;
164 dmas = <&sdma 65 &sdma 66>;
165 dma-names = "tx", "rx";
166 };
167
168 prm: prm@48306000 {
169 compatible = "ti,omap3-prm";
170 reg = <0x48306000 0x4000>;
171 interrupts = <11>;
172
173 prm_clocks: clocks {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 };
177
178 prm_clockdomains: clockdomains {
179 };
180 };
181
182 cm: cm@48004000 {
183 compatible = "ti,omap3-cm";
184 reg = <0x48004000 0x4000>;
185
186 cm_clocks: clocks {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 };
190
191 cm_clockdomains: clockdomains {
192 };
193 };
194
195 counter32k: counter@48320000 {
196 compatible = "ti,omap-counter32k";
197 reg = <0x48320000 0x20>;
198 ti,hwmods = "counter_32k";
199 };
200
201 intc: interrupt-controller@48200000 {
202 compatible = "ti,omap3-intc";
203 interrupt-controller;
204 #interrupt-cells = <1>;
205 reg = <0x48200000 0x1000>;
206 };
207
208 sdma: dma-controller@48056000 {
209 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
210 reg = <0x48056000 0x1000>;
211 interrupts = <12>,
212 <13>,
213 <14>,
214 <15>;
215 #dma-cells = <1>;
216 dma-channels = <32>;
217 dma-requests = <96>;
218 };
219
220 gpio1: gpio@48310000 {
221 compatible = "ti,omap3-gpio";
222 reg = <0x48310000 0x200>;
223 interrupts = <29>;
224 ti,hwmods = "gpio1";
225 ti,gpio-always-on;
226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 };
231
232 gpio2: gpio@49050000 {
233 compatible = "ti,omap3-gpio";
234 reg = <0x49050000 0x200>;
235 interrupts = <30>;
236 ti,hwmods = "gpio2";
237 gpio-controller;
238 #gpio-cells = <2>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 };
242
243 gpio3: gpio@49052000 {
244 compatible = "ti,omap3-gpio";
245 reg = <0x49052000 0x200>;
246 interrupts = <31>;
247 ti,hwmods = "gpio3";
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 };
253
254 gpio4: gpio@49054000 {
255 compatible = "ti,omap3-gpio";
256 reg = <0x49054000 0x200>;
257 interrupts = <32>;
258 ti,hwmods = "gpio4";
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
264
265 gpio5: gpio@49056000 {
266 compatible = "ti,omap3-gpio";
267 reg = <0x49056000 0x200>;
268 interrupts = <33>;
269 ti,hwmods = "gpio5";
270 gpio-controller;
271 #gpio-cells = <2>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 };
275
276 gpio6: gpio@49058000 {
277 compatible = "ti,omap3-gpio";
278 reg = <0x49058000 0x200>;
279 interrupts = <34>;
280 ti,hwmods = "gpio6";
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
286
287 uart1: serial@4806a000 {
288 compatible = "ti,omap3-uart";
289 reg = <0x4806a000 0x2000>;
290 interrupts-extended = <&intc 72>;
291 dmas = <&sdma 49 &sdma 50>;
292 dma-names = "tx", "rx";
293 ti,hwmods = "uart1";
294 clock-frequency = <48000000>;
295 };
296
297 uart2: serial@4806c000 {
298 compatible = "ti,omap3-uart";
299 reg = <0x4806c000 0x400>;
300 interrupts-extended = <&intc 73>;
301 dmas = <&sdma 51 &sdma 52>;
302 dma-names = "tx", "rx";
303 ti,hwmods = "uart2";
304 clock-frequency = <48000000>;
305 };
306
307 uart3: serial@49020000 {
308 compatible = "ti,omap3-uart";
309 reg = <0x49020000 0x400>;
310 interrupts-extended = <&intc 74>;
311 dmas = <&sdma 53 &sdma 54>;
312 dma-names = "tx", "rx";
313 ti,hwmods = "uart3";
314 clock-frequency = <48000000>;
315 };
316
317 i2c1: i2c@48070000 {
318 compatible = "ti,omap3-i2c";
319 reg = <0x48070000 0x80>;
320 interrupts = <56>;
321 dmas = <&sdma 27 &sdma 28>;
322 dma-names = "tx", "rx";
323 #address-cells = <1>;
324 #size-cells = <0>;
325 ti,hwmods = "i2c1";
326 };
327
328 i2c2: i2c@48072000 {
329 compatible = "ti,omap3-i2c";
330 reg = <0x48072000 0x80>;
331 interrupts = <57>;
332 dmas = <&sdma 29 &sdma 30>;
333 dma-names = "tx", "rx";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 ti,hwmods = "i2c2";
337 };
338
339 i2c3: i2c@48060000 {
340 compatible = "ti,omap3-i2c";
341 reg = <0x48060000 0x80>;
342 interrupts = <61>;
343 dmas = <&sdma 25 &sdma 26>;
344 dma-names = "tx", "rx";
345 #address-cells = <1>;
346 #size-cells = <0>;
347 ti,hwmods = "i2c3";
348 };
349
350 mailbox: mailbox@48094000 {
351 compatible = "ti,omap3-mailbox";
352 ti,hwmods = "mailbox";
353 reg = <0x48094000 0x200>;
354 interrupts = <26>;
355 #mbox-cells = <1>;
356 ti,mbox-num-users = <2>;
357 ti,mbox-num-fifos = <2>;
358 mbox_dsp: dsp {
359 ti,mbox-tx = <0 0 0>;
360 ti,mbox-rx = <1 0 0>;
361 };
362 };
363
364 mcspi1: spi@48098000 {
365 compatible = "ti,omap2-mcspi";
366 reg = <0x48098000 0x100>;
367 interrupts = <65>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 ti,hwmods = "mcspi1";
371 ti,spi-num-cs = <4>;
372 dmas = <&sdma 35>,
373 <&sdma 36>,
374 <&sdma 37>,
375 <&sdma 38>,
376 <&sdma 39>,
377 <&sdma 40>,
378 <&sdma 41>,
379 <&sdma 42>;
380 dma-names = "tx0", "rx0", "tx1", "rx1",
381 "tx2", "rx2", "tx3", "rx3";
382 };
383
384 mcspi2: spi@4809a000 {
385 compatible = "ti,omap2-mcspi";
386 reg = <0x4809a000 0x100>;
387 interrupts = <66>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390 ti,hwmods = "mcspi2";
391 ti,spi-num-cs = <2>;
392 dmas = <&sdma 43>,
393 <&sdma 44>,
394 <&sdma 45>,
395 <&sdma 46>;
396 dma-names = "tx0", "rx0", "tx1", "rx1";
397 };
398
399 mcspi3: spi@480b8000 {
400 compatible = "ti,omap2-mcspi";
401 reg = <0x480b8000 0x100>;
402 interrupts = <91>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 ti,hwmods = "mcspi3";
406 ti,spi-num-cs = <2>;
407 dmas = <&sdma 15>,
408 <&sdma 16>,
409 <&sdma 23>,
410 <&sdma 24>;
411 dma-names = "tx0", "rx0", "tx1", "rx1";
412 };
413
414 mcspi4: spi@480ba000 {
415 compatible = "ti,omap2-mcspi";
416 reg = <0x480ba000 0x100>;
417 interrupts = <48>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 ti,hwmods = "mcspi4";
421 ti,spi-num-cs = <1>;
422 dmas = <&sdma 70>, <&sdma 71>;
423 dma-names = "tx0", "rx0";
424 };
425
426 hdqw1w: 1w@480b2000 {
427 compatible = "ti,omap3-1w";
428 reg = <0x480b2000 0x1000>;
429 interrupts = <58>;
430 ti,hwmods = "hdq1w";
431 };
432
433 mmc1: mmc@4809c000 {
434 compatible = "ti,omap3-hsmmc";
435 reg = <0x4809c000 0x200>;
436 interrupts = <83>;
437 ti,hwmods = "mmc1";
438 ti,dual-volt;
439 dmas = <&sdma 61>, <&sdma 62>;
440 dma-names = "tx", "rx";
441 pbias-supply = <&pbias_mmc_reg>;
442 };
443
444 mmc2: mmc@480b4000 {
445 compatible = "ti,omap3-hsmmc";
446 reg = <0x480b4000 0x200>;
447 interrupts = <86>;
448 ti,hwmods = "mmc2";
449 dmas = <&sdma 47>, <&sdma 48>;
450 dma-names = "tx", "rx";
451 };
452
453 mmc3: mmc@480ad000 {
454 compatible = "ti,omap3-hsmmc";
455 reg = <0x480ad000 0x200>;
456 interrupts = <94>;
457 ti,hwmods = "mmc3";
458 dmas = <&sdma 77>, <&sdma 78>;
459 dma-names = "tx", "rx";
460 };
461
462 mmu_isp: mmu@480bd400 {
463 #iommu-cells = <0>;
464 compatible = "ti,omap2-iommu";
465 reg = <0x480bd400 0x80>;
466 interrupts = <24>;
467 ti,hwmods = "mmu_isp";
468 ti,#tlb-entries = <8>;
469 };
470
471 mmu_iva: mmu@5d000000 {
472 #iommu-cells = <0>;
473 compatible = "ti,omap2-iommu";
474 reg = <0x5d000000 0x80>;
475 interrupts = <28>;
476 ti,hwmods = "mmu_iva";
477 status = "disabled";
478 };
479
480 wdt2: wdt@48314000 {
481 compatible = "ti,omap3-wdt";
482 reg = <0x48314000 0x80>;
483 ti,hwmods = "wd_timer2";
484 };
485
486 mcbsp1: mcbsp@48074000 {
487 compatible = "ti,omap3-mcbsp";
488 reg = <0x48074000 0xff>;
489 reg-names = "mpu";
490 interrupts = <16>, /* OCP compliant interrupt */
491 <59>, /* TX interrupt */
492 <60>; /* RX interrupt */
493 interrupt-names = "common", "tx", "rx";
494 ti,buffer-size = <128>;
495 ti,hwmods = "mcbsp1";
496 dmas = <&sdma 31>,
497 <&sdma 32>;
498 dma-names = "tx", "rx";
499 clocks = <&mcbsp1_fck>;
500 clock-names = "fck";
501 status = "disabled";
502 };
503
504 mcbsp2: mcbsp@49022000 {
505 compatible = "ti,omap3-mcbsp";
506 reg = <0x49022000 0xff>,
507 <0x49028000 0xff>;
508 reg-names = "mpu", "sidetone";
509 interrupts = <17>, /* OCP compliant interrupt */
510 <62>, /* TX interrupt */
511 <63>, /* RX interrupt */
512 <4>; /* Sidetone */
513 interrupt-names = "common", "tx", "rx", "sidetone";
514 ti,buffer-size = <1280>;
515 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
516 dmas = <&sdma 33>,
517 <&sdma 34>;
518 dma-names = "tx", "rx";
519 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
520 clock-names = "fck", "ick";
521 status = "disabled";
522 };
523
524 mcbsp3: mcbsp@49024000 {
525 compatible = "ti,omap3-mcbsp";
526 reg = <0x49024000 0xff>,
527 <0x4902a000 0xff>;
528 reg-names = "mpu", "sidetone";
529 interrupts = <22>, /* OCP compliant interrupt */
530 <89>, /* TX interrupt */
531 <90>, /* RX interrupt */
532 <5>; /* Sidetone */
533 interrupt-names = "common", "tx", "rx", "sidetone";
534 ti,buffer-size = <128>;
535 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
536 dmas = <&sdma 17>,
537 <&sdma 18>;
538 dma-names = "tx", "rx";
539 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
540 clock-names = "fck", "ick";
541 status = "disabled";
542 };
543
544 mcbsp4: mcbsp@49026000 {
545 compatible = "ti,omap3-mcbsp";
546 reg = <0x49026000 0xff>;
547 reg-names = "mpu";
548 interrupts = <23>, /* OCP compliant interrupt */
549 <54>, /* TX interrupt */
550 <55>; /* RX interrupt */
551 interrupt-names = "common", "tx", "rx";
552 ti,buffer-size = <128>;
553 ti,hwmods = "mcbsp4";
554 dmas = <&sdma 19>,
555 <&sdma 20>;
556 dma-names = "tx", "rx";
557 clocks = <&mcbsp4_fck>;
558 clock-names = "fck";
559 status = "disabled";
560 };
561
562 mcbsp5: mcbsp@48096000 {
563 compatible = "ti,omap3-mcbsp";
564 reg = <0x48096000 0xff>;
565 reg-names = "mpu";
566 interrupts = <27>, /* OCP compliant interrupt */
567 <81>, /* TX interrupt */
568 <82>; /* RX interrupt */
569 interrupt-names = "common", "tx", "rx";
570 ti,buffer-size = <128>;
571 ti,hwmods = "mcbsp5";
572 dmas = <&sdma 21>,
573 <&sdma 22>;
574 dma-names = "tx", "rx";
575 clocks = <&mcbsp5_fck>;
576 clock-names = "fck";
577 status = "disabled";
578 };
579
580 sham: sham@480c3000 {
581 compatible = "ti,omap3-sham";
582 ti,hwmods = "sham";
583 reg = <0x480c3000 0x64>;
584 interrupts = <49>;
585 dmas = <&sdma 69>;
586 dma-names = "rx";
587 };
588
589 smartreflex_core: smartreflex@480cb000 {
590 compatible = "ti,omap3-smartreflex-core";
591 ti,hwmods = "smartreflex_core";
592 reg = <0x480cb000 0x400>;
593 interrupts = <19>;
594 };
595
596 smartreflex_mpu_iva: smartreflex@480c9000 {
597 compatible = "ti,omap3-smartreflex-iva";
598 ti,hwmods = "smartreflex_mpu_iva";
599 reg = <0x480c9000 0x400>;
600 interrupts = <18>;
601 };
602
603 timer1: timer@48318000 {
604 compatible = "ti,omap3430-timer";
605 reg = <0x48318000 0x400>;
606 interrupts = <37>;
607 ti,hwmods = "timer1";
608 ti,timer-alwon;
609 };
610
611 timer2: timer@49032000 {
612 compatible = "ti,omap3430-timer";
613 reg = <0x49032000 0x400>;
614 interrupts = <38>;
615 ti,hwmods = "timer2";
616 };
617
618 timer3: timer@49034000 {
619 compatible = "ti,omap3430-timer";
620 reg = <0x49034000 0x400>;
621 interrupts = <39>;
622 ti,hwmods = "timer3";
623 };
624
625 timer4: timer@49036000 {
626 compatible = "ti,omap3430-timer";
627 reg = <0x49036000 0x400>;
628 interrupts = <40>;
629 ti,hwmods = "timer4";
630 };
631
632 timer5: timer@49038000 {
633 compatible = "ti,omap3430-timer";
634 reg = <0x49038000 0x400>;
635 interrupts = <41>;
636 ti,hwmods = "timer5";
637 ti,timer-dsp;
638 };
639
640 timer6: timer@4903a000 {
641 compatible = "ti,omap3430-timer";
642 reg = <0x4903a000 0x400>;
643 interrupts = <42>;
644 ti,hwmods = "timer6";
645 ti,timer-dsp;
646 };
647
648 timer7: timer@4903c000 {
649 compatible = "ti,omap3430-timer";
650 reg = <0x4903c000 0x400>;
651 interrupts = <43>;
652 ti,hwmods = "timer7";
653 ti,timer-dsp;
654 };
655
656 timer8: timer@4903e000 {
657 compatible = "ti,omap3430-timer";
658 reg = <0x4903e000 0x400>;
659 interrupts = <44>;
660 ti,hwmods = "timer8";
661 ti,timer-pwm;
662 ti,timer-dsp;
663 };
664
665 timer9: timer@49040000 {
666 compatible = "ti,omap3430-timer";
667 reg = <0x49040000 0x400>;
668 interrupts = <45>;
669 ti,hwmods = "timer9";
670 ti,timer-pwm;
671 };
672
673 timer10: timer@48086000 {
674 compatible = "ti,omap3430-timer";
675 reg = <0x48086000 0x400>;
676 interrupts = <46>;
677 ti,hwmods = "timer10";
678 ti,timer-pwm;
679 };
680
681 timer11: timer@48088000 {
682 compatible = "ti,omap3430-timer";
683 reg = <0x48088000 0x400>;
684 interrupts = <47>;
685 ti,hwmods = "timer11";
686 ti,timer-pwm;
687 };
688
689 timer12: timer@48304000 {
690 compatible = "ti,omap3430-timer";
691 reg = <0x48304000 0x400>;
692 interrupts = <95>;
693 ti,hwmods = "timer12";
694 ti,timer-alwon;
695 ti,timer-secure;
696 };
697
698 usbhstll: usbhstll@48062000 {
699 compatible = "ti,usbhs-tll";
700 reg = <0x48062000 0x1000>;
701 interrupts = <78>;
702 ti,hwmods = "usb_tll_hs";
703 };
704
705 usbhshost: usbhshost@48064000 {
706 compatible = "ti,usbhs-host";
707 reg = <0x48064000 0x400>;
708 ti,hwmods = "usb_host_hs";
709 #address-cells = <1>;
710 #size-cells = <1>;
711 ranges;
712
713 usbhsohci: ohci@48064400 {
714 compatible = "ti,ohci-omap3";
715 reg = <0x48064400 0x400>;
716 interrupt-parent = <&intc>;
717 interrupts = <76>;
718 };
719
720 usbhsehci: ehci@48064800 {
721 compatible = "ti,ehci-omap";
722 reg = <0x48064800 0x400>;
723 interrupt-parent = <&intc>;
724 interrupts = <77>;
725 };
726 };
727
728 gpmc: gpmc@6e000000 {
729 compatible = "ti,omap3430-gpmc";
730 ti,hwmods = "gpmc";
731 reg = <0x6e000000 0x02d0>;
732 interrupts = <20>;
733 dmas = <&sdma 4>;
734 dma-names = "rxtx";
735 gpmc,num-cs = <8>;
736 gpmc,num-waitpins = <4>;
737 #address-cells = <2>;
738 #size-cells = <1>;
739 interrupt-controller;
740 #interrupt-cells = <2>;
741 gpio-controller;
742 #gpio-cells = <2>;
743 };
744
745 usb_otg_hs: usb_otg_hs@480ab000 {
746 compatible = "ti,omap3-musb";
747 reg = <0x480ab000 0x1000>;
748 interrupts = <92>, <93>;
749 interrupt-names = "mc", "dma";
750 ti,hwmods = "usb_otg_hs";
751 multipoint = <1>;
752 num-eps = <16>;
753 ram-bits = <12>;
754 };
755
756 dss: dss@48050000 {
757 compatible = "ti,omap3-dss";
758 reg = <0x48050000 0x200>;
759 status = "disabled";
760 ti,hwmods = "dss_core";
761 clocks = <&dss1_alwon_fck>;
762 clock-names = "fck";
763 #address-cells = <1>;
764 #size-cells = <1>;
765 ranges;
766
767 dispc@48050400 {
768 compatible = "ti,omap3-dispc";
769 reg = <0x48050400 0x400>;
770 interrupts = <25>;
771 ti,hwmods = "dss_dispc";
772 clocks = <&dss1_alwon_fck>;
773 clock-names = "fck";
774 };
775
776 dsi: encoder@4804fc00 {
777 compatible = "ti,omap3-dsi";
778 reg = <0x4804fc00 0x200>,
779 <0x4804fe00 0x40>,
780 <0x4804ff00 0x20>;
781 reg-names = "proto", "phy", "pll";
782 interrupts = <25>;
783 status = "disabled";
784 ti,hwmods = "dss_dsi1";
785 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
786 clock-names = "fck", "sys_clk";
787 };
788
789 rfbi: encoder@48050800 {
790 compatible = "ti,omap3-rfbi";
791 reg = <0x48050800 0x100>;
792 status = "disabled";
793 ti,hwmods = "dss_rfbi";
794 clocks = <&dss1_alwon_fck>, <&dss_ick>;
795 clock-names = "fck", "ick";
796 };
797
798 venc: encoder@48050c00 {
799 compatible = "ti,omap3-venc";
800 reg = <0x48050c00 0x100>;
801 status = "disabled";
802 ti,hwmods = "dss_venc";
803 clocks = <&dss_tv_fck>;
804 clock-names = "fck";
805 };
806 };
807
808 ssi: ssi-controller@48058000 {
809 compatible = "ti,omap3-ssi";
810 ti,hwmods = "ssi";
811
812 status = "disabled";
813
814 reg = <0x48058000 0x1000>,
815 <0x48059000 0x1000>;
816 reg-names = "sys",
817 "gdd";
818
819 interrupts = <71>;
820 interrupt-names = "gdd_mpu";
821
822 #address-cells = <1>;
823 #size-cells = <1>;
824 ranges;
825
826 ssi_port1: ssi-port@4805a000 {
827 compatible = "ti,omap3-ssi-port";
828
829 reg = <0x4805a000 0x800>,
830 <0x4805a800 0x800>;
831 reg-names = "tx",
832 "rx";
833
834 interrupt-parent = <&intc>;
835 interrupts = <67>,
836 <68>;
837 };
838
839 ssi_port2: ssi-port@4805b000 {
840 compatible = "ti,omap3-ssi-port";
841
842 reg = <0x4805b000 0x800>,
843 <0x4805b800 0x800>;
844 reg-names = "tx",
845 "rx";
846
847 interrupt-parent = <&intc>;
848 interrupts = <69>,
849 <70>;
850 };
851 };
852 };
853};
854
855/include/ "omap3xxx-clocks.dtsi"