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1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; };
26
27 aliases {
28 ethernet0 = &fec1;
29 ethernet1 = &fec2;
30 gpio0 = &gpio1;
31 gpio1 = &gpio2;
32 gpio2 = &gpio3;
33 gpio3 = &gpio4;
34 gpio4 = &gpio5;
35 i2c0 = &i2c1;
36 i2c1 = &i2c2;
37 i2c2 = &i2c3;
38 i2c3 = &i2c4;
39 mmc0 = &usdhc1;
40 mmc1 = &usdhc2;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 serial6 = &uart7;
48 serial7 = &uart8;
49 sai1 = &sai1;
50 sai2 = &sai2;
51 sai3 = &sai3;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &ecspi3;
55 spi3 = &ecspi4;
56 usbphy0 = &usbphy1;
57 usbphy1 = &usbphy2;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 cpu0: cpu@0 {
65 compatible = "arm,cortex-a7";
66 device_type = "cpu";
67 reg = <0>;
68 clock-latency = <61036>; /* two CLK32 periods */
69 operating-points = <
70 /* kHz uV */
71 696000 1275000
72 528000 1175000
73 396000 1025000
74 198000 950000
75 >;
76 fsl,soc-operating-points = <
77 /* KHz uV */
78 696000 1275000
79 528000 1175000
80 396000 1175000
81 198000 1175000
82 >;
83 clocks = <&clks IMX6UL_CLK_ARM>,
84 <&clks IMX6UL_CLK_PLL2_BUS>,
85 <&clks IMX6UL_CLK_PLL2_PFD2>,
86 <&clks IMX6UL_CA7_SECONDARY_SEL>,
87 <&clks IMX6UL_CLK_STEP>,
88 <&clks IMX6UL_CLK_PLL1_SW>,
89 <&clks IMX6UL_CLK_PLL1_SYS>;
90 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
91 "secondary_sel", "step", "pll1_sw",
92 "pll1_sys";
93 arm-supply = <®_arm>;
94 soc-supply = <®_soc>;
95 };
96 };
97
98 intc: interrupt-controller@a01000 {
99 compatible = "arm,gic-400", "arm,cortex-a7-gic";
100 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
101 #interrupt-cells = <3>;
102 interrupt-controller;
103 interrupt-parent = <&intc>;
104 reg = <0x00a01000 0x1000>,
105 <0x00a02000 0x2000>,
106 <0x00a04000 0x2000>,
107 <0x00a06000 0x2000>;
108 };
109
110 timer {
111 compatible = "arm,armv7-timer";
112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
116 interrupt-parent = <&intc>;
117 status = "disabled";
118 };
119
120 ckil: clock-cli {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <32768>;
124 clock-output-names = "ckil";
125 };
126
127 osc: clock-osc {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <24000000>;
131 clock-output-names = "osc";
132 };
133
134 ipp_di0: clock-di0 {
135 compatible = "fixed-clock";
136 #clock-cells = <0>;
137 clock-frequency = <0>;
138 clock-output-names = "ipp_di0";
139 };
140
141 ipp_di1: clock-di1 {
142 compatible = "fixed-clock";
143 #clock-cells = <0>;
144 clock-frequency = <0>;
145 clock-output-names = "ipp_di1";
146 };
147
148 tempmon: tempmon {
149 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
150 interrupt-parent = <&gpc>;
151 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
152 fsl,tempmon = <&anatop>;
153 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
154 nvmem-cell-names = "calib", "temp_grade";
155 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
156 };
157
158 pmu {
159 compatible = "arm,cortex-a7-pmu";
160 interrupt-parent = <&gpc>;
161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
162 status = "disabled";
163 };
164
165 soc {
166 #address-cells = <1>;
167 #size-cells = <1>;
168 compatible = "simple-bus";
169 interrupt-parent = <&gpc>;
170 ranges;
171
172 ocram: sram@900000 {
173 compatible = "mmio-sram";
174 reg = <0x00900000 0x20000>;
175 };
176
177 dma_apbh: dma-apbh@1804000 {
178 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
179 reg = <0x01804000 0x2000>;
180 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
181 <0 13 IRQ_TYPE_LEVEL_HIGH>,
182 <0 13 IRQ_TYPE_LEVEL_HIGH>,
183 <0 13 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
185 #dma-cells = <1>;
186 dma-channels = <4>;
187 clocks = <&clks IMX6UL_CLK_APBHDMA>;
188 };
189
190 gpmi: gpmi-nand@1806000 {
191 compatible = "fsl,imx6q-gpmi-nand";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
195 reg-names = "gpmi-nand", "bch";
196 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
197 interrupt-names = "bch";
198 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
199 <&clks IMX6UL_CLK_GPMI_APB>,
200 <&clks IMX6UL_CLK_GPMI_BCH>,
201 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
202 <&clks IMX6UL_CLK_PER_BCH>;
203 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
204 "gpmi_bch_apb", "per1_bch";
205 dmas = <&dma_apbh 0>;
206 dma-names = "rx-tx";
207 status = "disabled";
208 };
209
210 aips1: aips-bus@2000000 {
211 compatible = "fsl,aips-bus", "simple-bus";
212 #address-cells = <1>;
213 #size-cells = <1>;
214 reg = <0x02000000 0x100000>;
215 ranges;
216
217 spba-bus@2000000 {
218 compatible = "fsl,spba-bus", "simple-bus";
219 #address-cells = <1>;
220 #size-cells = <1>;
221 reg = <0x02000000 0x40000>;
222 ranges;
223
224 ecspi1: ecspi@2008000 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
228 reg = <0x02008000 0x4000>;
229 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clks IMX6UL_CLK_ECSPI1>,
231 <&clks IMX6UL_CLK_ECSPI1>;
232 clock-names = "ipg", "per";
233 status = "disabled";
234 };
235
236 ecspi2: ecspi@200c000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
240 reg = <0x0200c000 0x4000>;
241 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clks IMX6UL_CLK_ECSPI2>,
243 <&clks IMX6UL_CLK_ECSPI2>;
244 clock-names = "ipg", "per";
245 status = "disabled";
246 };
247
248 ecspi3: ecspi@2010000 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
252 reg = <0x02010000 0x4000>;
253 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clks IMX6UL_CLK_ECSPI3>,
255 <&clks IMX6UL_CLK_ECSPI3>;
256 clock-names = "ipg", "per";
257 status = "disabled";
258 };
259
260 ecspi4: ecspi@2014000 {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
264 reg = <0x02014000 0x4000>;
265 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clks IMX6UL_CLK_ECSPI4>,
267 <&clks IMX6UL_CLK_ECSPI4>;
268 clock-names = "ipg", "per";
269 status = "disabled";
270 };
271
272 uart7: serial@2018000 {
273 compatible = "fsl,imx6ul-uart",
274 "fsl,imx6q-uart";
275 reg = <0x02018000 0x4000>;
276 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
278 <&clks IMX6UL_CLK_UART7_SERIAL>;
279 clock-names = "ipg", "per";
280 status = "disabled";
281 };
282
283 uart1: serial@2020000 {
284 compatible = "fsl,imx6ul-uart",
285 "fsl,imx6q-uart";
286 reg = <0x02020000 0x4000>;
287 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
289 <&clks IMX6UL_CLK_UART1_SERIAL>;
290 clock-names = "ipg", "per";
291 status = "disabled";
292 };
293
294 uart8: serial@2024000 {
295 compatible = "fsl,imx6ul-uart",
296 "fsl,imx6q-uart";
297 reg = <0x02024000 0x4000>;
298 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
300 <&clks IMX6UL_CLK_UART8_SERIAL>;
301 clock-names = "ipg", "per";
302 status = "disabled";
303 };
304
305 sai1: sai@2028000 {
306 #sound-dai-cells = <0>;
307 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
308 reg = <0x02028000 0x4000>;
309 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
311 <&clks IMX6UL_CLK_SAI1>,
312 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
313 clock-names = "bus", "mclk1", "mclk2", "mclk3";
314 dmas = <&sdma 35 24 0>,
315 <&sdma 36 24 0>;
316 dma-names = "rx", "tx";
317 status = "disabled";
318 };
319
320 sai2: sai@202c000 {
321 #sound-dai-cells = <0>;
322 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
323 reg = <0x0202c000 0x4000>;
324 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
326 <&clks IMX6UL_CLK_SAI2>,
327 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
328 clock-names = "bus", "mclk1", "mclk2", "mclk3";
329 dmas = <&sdma 37 24 0>,
330 <&sdma 38 24 0>;
331 dma-names = "rx", "tx";
332 status = "disabled";
333 };
334
335 sai3: sai@2030000 {
336 #sound-dai-cells = <0>;
337 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
338 reg = <0x02030000 0x4000>;
339 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
341 <&clks IMX6UL_CLK_SAI3>,
342 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
343 clock-names = "bus", "mclk1", "mclk2", "mclk3";
344 dmas = <&sdma 39 24 0>,
345 <&sdma 40 24 0>;
346 dma-names = "rx", "tx";
347 status = "disabled";
348 };
349 };
350
351 tsc: tsc@2040000 {
352 compatible = "fsl,imx6ul-tsc";
353 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
354 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clks IMX6UL_CLK_IPG>,
357 <&clks IMX6UL_CLK_ADC2>;
358 clock-names = "tsc", "adc";
359 status = "disabled";
360 };
361
362 pwm1: pwm@2080000 {
363 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
364 reg = <0x02080000 0x4000>;
365 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clks IMX6UL_CLK_PWM1>,
367 <&clks IMX6UL_CLK_PWM1>;
368 clock-names = "ipg", "per";
369 #pwm-cells = <2>;
370 status = "disabled";
371 };
372
373 pwm2: pwm@2084000 {
374 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
375 reg = <0x02084000 0x4000>;
376 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6UL_CLK_PWM2>,
378 <&clks IMX6UL_CLK_PWM2>;
379 clock-names = "ipg", "per";
380 #pwm-cells = <2>;
381 status = "disabled";
382 };
383
384 pwm3: pwm@2088000 {
385 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
386 reg = <0x02088000 0x4000>;
387 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks IMX6UL_CLK_PWM3>,
389 <&clks IMX6UL_CLK_PWM3>;
390 clock-names = "ipg", "per";
391 #pwm-cells = <2>;
392 status = "disabled";
393 };
394
395 pwm4: pwm@208c000 {
396 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
397 reg = <0x0208c000 0x4000>;
398 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clks IMX6UL_CLK_PWM4>,
400 <&clks IMX6UL_CLK_PWM4>;
401 clock-names = "ipg", "per";
402 #pwm-cells = <2>;
403 status = "disabled";
404 };
405
406 can1: flexcan@2090000 {
407 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
408 reg = <0x02090000 0x4000>;
409 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
411 <&clks IMX6UL_CLK_CAN1_SERIAL>;
412 clock-names = "ipg", "per";
413 status = "disabled";
414 };
415
416 can2: flexcan@2094000 {
417 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
418 reg = <0x02094000 0x4000>;
419 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
421 <&clks IMX6UL_CLK_CAN2_SERIAL>;
422 clock-names = "ipg", "per";
423 status = "disabled";
424 };
425
426 gpt1: gpt@2098000 {
427 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
428 reg = <0x02098000 0x4000>;
429 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
431 <&clks IMX6UL_CLK_GPT1_SERIAL>;
432 clock-names = "ipg", "per";
433 };
434
435 gpio1: gpio@209c000 {
436 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
437 reg = <0x0209c000 0x4000>;
438 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
445 <&iomuxc 16 33 16>;
446 };
447
448 gpio2: gpio@20a0000 {
449 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
450 reg = <0x020a0000 0x4000>;
451 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
453 gpio-controller;
454 #gpio-cells = <2>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
458 };
459
460 gpio3: gpio@20a4000 {
461 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
462 reg = <0x020a4000 0x4000>;
463 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
465 gpio-controller;
466 #gpio-cells = <2>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 gpio-ranges = <&iomuxc 0 65 29>;
470 };
471
472 gpio4: gpio@20a8000 {
473 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
474 reg = <0x020a8000 0x4000>;
475 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
482 };
483
484 gpio5: gpio@20ac000 {
485 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
486 reg = <0x020ac000 0x4000>;
487 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
489 gpio-controller;
490 #gpio-cells = <2>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
494 };
495
496 fec2: ethernet@20b4000 {
497 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
498 reg = <0x020b4000 0x4000>;
499 interrupt-names = "int0", "pps";
500 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clks IMX6UL_CLK_ENET>,
503 <&clks IMX6UL_CLK_ENET_AHB>,
504 <&clks IMX6UL_CLK_ENET_PTP>,
505 <&clks IMX6UL_CLK_ENET2_REF_125M>,
506 <&clks IMX6UL_CLK_ENET2_REF_125M>;
507 clock-names = "ipg", "ahb", "ptp",
508 "enet_clk_ref", "enet_out";
509 fsl,num-tx-queues=<1>;
510 fsl,num-rx-queues=<1>;
511 status = "disabled";
512 };
513
514 kpp: kpp@20b8000 {
515 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
516 reg = <0x020b8000 0x4000>;
517 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6UL_CLK_KPP>;
519 status = "disabled";
520 };
521
522 wdog1: wdog@20bc000 {
523 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
524 reg = <0x020bc000 0x4000>;
525 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clks IMX6UL_CLK_WDOG1>;
527 };
528
529 wdog2: wdog@20c0000 {
530 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
531 reg = <0x020c0000 0x4000>;
532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&clks IMX6UL_CLK_WDOG2>;
534 status = "disabled";
535 };
536
537 clks: ccm@20c4000 {
538 compatible = "fsl,imx6ul-ccm";
539 reg = <0x020c4000 0x4000>;
540 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
542 #clock-cells = <1>;
543 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
544 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
545 };
546
547 anatop: anatop@20c8000 {
548 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
549 "syscon", "simple-bus";
550 reg = <0x020c8000 0x1000>;
551 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556
557 reg_3p0: regulator-3p0@20c8110 {
558 reg = <0x20c8110>;
559 compatible = "fsl,anatop-regulator";
560 regulator-name = "vdd3p0";
561 regulator-min-microvolt = <2625000>;
562 regulator-max-microvolt = <3400000>;
563 anatop-reg-offset = <0x120>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2625000>;
568 anatop-max-voltage = <3400000>;
569 anatop-enable-bit = <0>;
570 };
571
572 reg_arm: regulator-vddcore@20c8140 {
573 reg = <0x20c8140>;
574 compatible = "fsl,anatop-regulator";
575 regulator-name = "cpu";
576 regulator-min-microvolt = <725000>;
577 regulator-max-microvolt = <1450000>;
578 regulator-always-on;
579 anatop-reg-offset = <0x140>;
580 anatop-vol-bit-shift = <0>;
581 anatop-vol-bit-width = <5>;
582 anatop-delay-reg-offset = <0x170>;
583 anatop-delay-bit-shift = <24>;
584 anatop-delay-bit-width = <2>;
585 anatop-min-bit-val = <1>;
586 anatop-min-voltage = <725000>;
587 anatop-max-voltage = <1450000>;
588 };
589
590 reg_soc: regulator-vddsoc@20c8140 {
591 reg = <0x20c8140>;
592 compatible = "fsl,anatop-regulator";
593 regulator-name = "vddsoc";
594 regulator-min-microvolt = <725000>;
595 regulator-max-microvolt = <1450000>;
596 regulator-always-on;
597 anatop-reg-offset = <0x140>;
598 anatop-vol-bit-shift = <18>;
599 anatop-vol-bit-width = <5>;
600 anatop-delay-reg-offset = <0x170>;
601 anatop-delay-bit-shift = <28>;
602 anatop-delay-bit-width = <2>;
603 anatop-min-bit-val = <1>;
604 anatop-min-voltage = <725000>;
605 anatop-max-voltage = <1450000>;
606 };
607 };
608
609 usbphy1: usbphy@20c9000 {
610 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
611 reg = <0x020c9000 0x1000>;
612 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&clks IMX6UL_CLK_USBPHY1>;
614 phy-3p0-supply = <®_3p0>;
615 fsl,anatop = <&anatop>;
616 };
617
618 usbphy2: usbphy@20ca000 {
619 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
620 reg = <0x020ca000 0x1000>;
621 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&clks IMX6UL_CLK_USBPHY2>;
623 phy-3p0-supply = <®_3p0>;
624 fsl,anatop = <&anatop>;
625 };
626
627 snvs: snvs@20cc000 {
628 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
629 reg = <0x020cc000 0x4000>;
630
631 snvs_rtc: snvs-rtc-lp {
632 compatible = "fsl,sec-v4.0-mon-rtc-lp";
633 regmap = <&snvs>;
634 offset = <0x34>;
635 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
637 };
638
639 snvs_poweroff: snvs-poweroff {
640 compatible = "syscon-poweroff";
641 regmap = <&snvs>;
642 offset = <0x38>;
643 value = <0x60>;
644 mask = <0x60>;
645 status = "disabled";
646 };
647
648 snvs_pwrkey: snvs-powerkey {
649 compatible = "fsl,sec-v4.0-pwrkey";
650 regmap = <&snvs>;
651 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
652 linux,keycode = <KEY_POWER>;
653 wakeup-source;
654 };
655
656 snvs_lpgpr: snvs-lpgpr {
657 compatible = "fsl,imx6ul-snvs-lpgpr";
658 };
659 };
660
661 epit1: epit@20d0000 {
662 reg = <0x020d0000 0x4000>;
663 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
664 };
665
666 epit2: epit@20d4000 {
667 reg = <0x020d4000 0x4000>;
668 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
669 };
670
671 src: src@20d8000 {
672 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
673 reg = <0x020d8000 0x4000>;
674 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
676 #reset-cells = <1>;
677 };
678
679 gpc: gpc@20dc000 {
680 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
681 reg = <0x020dc000 0x4000>;
682 interrupt-controller;
683 #interrupt-cells = <3>;
684 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
685 interrupt-parent = <&intc>;
686 };
687
688 iomuxc: iomuxc@20e0000 {
689 compatible = "fsl,imx6ul-iomuxc";
690 reg = <0x020e0000 0x4000>;
691 };
692
693 gpr: iomuxc-gpr@20e4000 {
694 compatible = "fsl,imx6ul-iomuxc-gpr",
695 "fsl,imx6q-iomuxc-gpr", "syscon";
696 reg = <0x020e4000 0x4000>;
697 };
698
699 gpt2: gpt@20e8000 {
700 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
701 reg = <0x020e8000 0x4000>;
702 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
704 <&clks IMX6UL_CLK_GPT2_SERIAL>;
705 clock-names = "ipg", "per";
706 };
707
708 sdma: sdma@20ec000 {
709 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
710 "fsl,imx35-sdma";
711 reg = <0x020ec000 0x4000>;
712 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX6UL_CLK_SDMA>,
714 <&clks IMX6UL_CLK_SDMA>;
715 clock-names = "ipg", "ahb";
716 #dma-cells = <3>;
717 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
718 };
719
720 pwm5: pwm@20f0000 {
721 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
722 reg = <0x020f0000 0x4000>;
723 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&clks IMX6UL_CLK_PWM5>,
725 <&clks IMX6UL_CLK_PWM5>;
726 clock-names = "ipg", "per";
727 #pwm-cells = <2>;
728 status = "disabled";
729 };
730
731 pwm6: pwm@20f4000 {
732 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
733 reg = <0x020f4000 0x4000>;
734 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clks IMX6UL_CLK_PWM6>,
736 <&clks IMX6UL_CLK_PWM6>;
737 clock-names = "ipg", "per";
738 #pwm-cells = <2>;
739 status = "disabled";
740 };
741
742 pwm7: pwm@20f8000 {
743 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
744 reg = <0x020f8000 0x4000>;
745 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&clks IMX6UL_CLK_PWM7>,
747 <&clks IMX6UL_CLK_PWM7>;
748 clock-names = "ipg", "per";
749 #pwm-cells = <2>;
750 status = "disabled";
751 };
752
753 pwm8: pwm@20fc000 {
754 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
755 reg = <0x020fc000 0x4000>;
756 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&clks IMX6UL_CLK_PWM8>,
758 <&clks IMX6UL_CLK_PWM8>;
759 clock-names = "ipg", "per";
760 #pwm-cells = <2>;
761 status = "disabled";
762 };
763 };
764
765 aips2: aips-bus@2100000 {
766 compatible = "fsl,aips-bus", "simple-bus";
767 #address-cells = <1>;
768 #size-cells = <1>;
769 reg = <0x02100000 0x100000>;
770 ranges;
771
772 usbotg1: usb@2184000 {
773 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
774 reg = <0x02184000 0x200>;
775 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&clks IMX6UL_CLK_USBOH3>;
777 fsl,usbphy = <&usbphy1>;
778 fsl,usbmisc = <&usbmisc 0>;
779 fsl,anatop = <&anatop>;
780 ahb-burst-config = <0x0>;
781 tx-burst-size-dword = <0x10>;
782 rx-burst-size-dword = <0x10>;
783 status = "disabled";
784 };
785
786 usbotg2: usb@2184200 {
787 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
788 reg = <0x02184200 0x200>;
789 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clks IMX6UL_CLK_USBOH3>;
791 fsl,usbphy = <&usbphy2>;
792 fsl,usbmisc = <&usbmisc 1>;
793 ahb-burst-config = <0x0>;
794 tx-burst-size-dword = <0x10>;
795 rx-burst-size-dword = <0x10>;
796 status = "disabled";
797 };
798
799 usbmisc: usbmisc@2184800 {
800 #index-cells = <1>;
801 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
802 reg = <0x02184800 0x200>;
803 };
804
805 fec1: ethernet@2188000 {
806 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
807 reg = <0x02188000 0x4000>;
808 interrupt-names = "int0", "pps";
809 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6UL_CLK_ENET>,
812 <&clks IMX6UL_CLK_ENET_AHB>,
813 <&clks IMX6UL_CLK_ENET_PTP>,
814 <&clks IMX6UL_CLK_ENET_REF>,
815 <&clks IMX6UL_CLK_ENET_REF>;
816 clock-names = "ipg", "ahb", "ptp",
817 "enet_clk_ref", "enet_out";
818 fsl,num-tx-queues=<1>;
819 fsl,num-rx-queues=<1>;
820 status = "disabled";
821 };
822
823 usdhc1: usdhc@2190000 {
824 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
825 reg = <0x02190000 0x4000>;
826 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&clks IMX6UL_CLK_USDHC1>,
828 <&clks IMX6UL_CLK_USDHC1>,
829 <&clks IMX6UL_CLK_USDHC1>;
830 clock-names = "ipg", "ahb", "per";
831 bus-width = <4>;
832 status = "disabled";
833 };
834
835 usdhc2: usdhc@2194000 {
836 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
837 reg = <0x02194000 0x4000>;
838 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX6UL_CLK_USDHC2>,
840 <&clks IMX6UL_CLK_USDHC2>,
841 <&clks IMX6UL_CLK_USDHC2>;
842 clock-names = "ipg", "ahb", "per";
843 bus-width = <4>;
844 status = "disabled";
845 };
846
847 adc1: adc@2198000 {
848 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
849 reg = <0x02198000 0x4000>;
850 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6UL_CLK_ADC1>;
852 num-channels = <2>;
853 clock-names = "adc";
854 fsl,adck-max-frequency = <30000000>, <40000000>,
855 <20000000>;
856 status = "disabled";
857 };
858
859 i2c1: i2c@21a0000 {
860 #address-cells = <1>;
861 #size-cells = <0>;
862 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
863 reg = <0x021a0000 0x4000>;
864 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6UL_CLK_I2C1>;
866 status = "disabled";
867 };
868
869 i2c2: i2c@21a4000 {
870 #address-cells = <1>;
871 #size-cells = <0>;
872 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
873 reg = <0x021a4000 0x4000>;
874 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clks IMX6UL_CLK_I2C2>;
876 status = "disabled";
877 };
878
879 i2c3: i2c@21a8000 {
880 #address-cells = <1>;
881 #size-cells = <0>;
882 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
883 reg = <0x021a8000 0x4000>;
884 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6UL_CLK_I2C3>;
886 status = "disabled";
887 };
888
889 mmdc: mmdc@21b0000 {
890 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
891 reg = <0x021b0000 0x4000>;
892 };
893
894 ocotp: ocotp-ctrl@21bc000 {
895 #address-cells = <1>;
896 #size-cells = <1>;
897 compatible = "fsl,imx6ul-ocotp", "syscon";
898 reg = <0x021bc000 0x4000>;
899 clocks = <&clks IMX6UL_CLK_OCOTP>;
900
901 tempmon_calib: calib@38 {
902 reg = <0x38 4>;
903 };
904
905 tempmon_temp_grade: temp-grade@20 {
906 reg = <0x20 4>;
907 };
908 };
909
910 lcdif: lcdif@21c8000 {
911 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
912 reg = <0x021c8000 0x4000>;
913 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
915 <&clks IMX6UL_CLK_LCDIF_APB>,
916 <&clks IMX6UL_CLK_DUMMY>;
917 clock-names = "pix", "axi", "disp_axi";
918 status = "disabled";
919 };
920
921 qspi: qspi@21e0000 {
922 #address-cells = <1>;
923 #size-cells = <0>;
924 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
925 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
926 reg-names = "QuadSPI", "QuadSPI-memory";
927 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX6UL_CLK_QSPI>,
929 <&clks IMX6UL_CLK_QSPI>;
930 clock-names = "qspi_en", "qspi";
931 status = "disabled";
932 };
933
934 wdog3: wdog@21e4000 {
935 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
936 reg = <0x021e4000 0x4000>;
937 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&clks IMX6UL_CLK_WDOG3>;
939 status = "disabled";
940 };
941
942 uart2: serial@21e8000 {
943 compatible = "fsl,imx6ul-uart",
944 "fsl,imx6q-uart";
945 reg = <0x021e8000 0x4000>;
946 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
948 <&clks IMX6UL_CLK_UART2_SERIAL>;
949 clock-names = "ipg", "per";
950 status = "disabled";
951 };
952
953 uart3: serial@21ec000 {
954 compatible = "fsl,imx6ul-uart",
955 "fsl,imx6q-uart";
956 reg = <0x021ec000 0x4000>;
957 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
959 <&clks IMX6UL_CLK_UART3_SERIAL>;
960 clock-names = "ipg", "per";
961 status = "disabled";
962 };
963
964 uart4: serial@21f0000 {
965 compatible = "fsl,imx6ul-uart",
966 "fsl,imx6q-uart";
967 reg = <0x021f0000 0x4000>;
968 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
970 <&clks IMX6UL_CLK_UART4_SERIAL>;
971 clock-names = "ipg", "per";
972 status = "disabled";
973 };
974
975 uart5: serial@21f4000 {
976 compatible = "fsl,imx6ul-uart",
977 "fsl,imx6q-uart";
978 reg = <0x021f4000 0x4000>;
979 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
981 <&clks IMX6UL_CLK_UART5_SERIAL>;
982 clock-names = "ipg", "per";
983 status = "disabled";
984 };
985
986 i2c4: i2c@21f8000 {
987 #address-cells = <1>;
988 #size-cells = <0>;
989 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
990 reg = <0x021f8000 0x4000>;
991 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clks IMX6UL_CLK_I2C4>;
993 status = "disabled";
994 };
995
996 uart6: serial@21fc000 {
997 compatible = "fsl,imx6ul-uart",
998 "fsl,imx6q-uart";
999 reg = <0x021fc000 0x4000>;
1000 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1002 <&clks IMX6UL_CLK_UART6_SERIAL>;
1003 clock-names = "ipg", "per";
1004 status = "disabled";
1005 };
1006 };
1007 };
1008};
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; reg = <0 0>; };
26
27 aliases {
28 ethernet0 = &fec1;
29 ethernet1 = &fec2;
30 gpio0 = &gpio1;
31 gpio1 = &gpio2;
32 gpio2 = &gpio3;
33 gpio3 = &gpio4;
34 gpio4 = &gpio5;
35 i2c0 = &i2c1;
36 i2c1 = &i2c2;
37 i2c2 = &i2c3;
38 i2c3 = &i2c4;
39 mmc0 = &usdhc1;
40 mmc1 = &usdhc2;
41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
46 serial5 = &uart6;
47 serial6 = &uart7;
48 serial7 = &uart8;
49 sai1 = &sai1;
50 sai2 = &sai2;
51 sai3 = &sai3;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &ecspi3;
55 spi3 = &ecspi4;
56 usbphy0 = &usbphy1;
57 usbphy1 = &usbphy2;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 cpu0: cpu@0 {
65 compatible = "arm,cortex-a7";
66 device_type = "cpu";
67 reg = <0>;
68 clock-latency = <61036>; /* two CLK32 periods */
69 operating-points = <
70 /* kHz uV */
71 528000 1175000
72 396000 1025000
73 198000 950000
74 >;
75 fsl,soc-operating-points = <
76 /* KHz uV */
77 528000 1175000
78 396000 1175000
79 198000 1175000
80 >;
81 clocks = <&clks IMX6UL_CLK_ARM>,
82 <&clks IMX6UL_CLK_PLL2_BUS>,
83 <&clks IMX6UL_CLK_PLL2_PFD2>,
84 <&clks IMX6UL_CA7_SECONDARY_SEL>,
85 <&clks IMX6UL_CLK_STEP>,
86 <&clks IMX6UL_CLK_PLL1_SW>,
87 <&clks IMX6UL_CLK_PLL1_SYS>,
88 <&clks IMX6UL_PLL1_BYPASS>,
89 <&clks IMX6UL_CLK_PLL1>,
90 <&clks IMX6UL_PLL1_BYPASS_SRC>,
91 <&clks IMX6UL_CLK_OSC>;
92 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
93 "secondary_sel", "step", "pll1_sw",
94 "pll1_sys", "pll1_bypass", "pll1",
95 "pll1_bypass_src", "osc";
96 arm-supply = <®_arm>;
97 soc-supply = <®_soc>;
98 };
99 };
100
101 intc: interrupt-controller@00a01000 {
102 compatible = "arm,cortex-a7-gic";
103 #interrupt-cells = <3>;
104 interrupt-controller;
105 reg = <0x00a01000 0x1000>,
106 <0x00a02000 0x1000>,
107 <0x00a04000 0x2000>,
108 <0x00a06000 0x2000>;
109 };
110
111 ckil: clock-cli {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <32768>;
115 clock-output-names = "ckil";
116 };
117
118 osc: clock-osc {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <24000000>;
122 clock-output-names = "osc";
123 };
124
125 ipp_di0: clock-di0 {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <0>;
129 clock-output-names = "ipp_di0";
130 };
131
132 ipp_di1: clock-di1 {
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-frequency = <0>;
136 clock-output-names = "ipp_di1";
137 };
138
139 soc {
140 #address-cells = <1>;
141 #size-cells = <1>;
142 compatible = "simple-bus";
143 interrupt-parent = <&gpc>;
144 ranges;
145
146 pmu {
147 compatible = "arm,cortex-a7-pmu";
148 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
149 status = "disabled";
150 };
151
152 ocram: sram@00900000 {
153 compatible = "mmio-sram";
154 reg = <0x00900000 0x20000>;
155 };
156
157 dma_apbh: dma-apbh@01804000 {
158 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
159 reg = <0x01804000 0x2000>;
160 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
161 <0 13 IRQ_TYPE_LEVEL_HIGH>,
162 <0 13 IRQ_TYPE_LEVEL_HIGH>,
163 <0 13 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
165 #dma-cells = <1>;
166 dma-channels = <4>;
167 clocks = <&clks IMX6UL_CLK_APBHDMA>;
168 };
169
170 gpmi: gpmi-nand@01806000 {
171 compatible = "fsl,imx6q-gpmi-nand";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
175 reg-names = "gpmi-nand", "bch";
176 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "bch";
178 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
179 <&clks IMX6UL_CLK_GPMI_APB>,
180 <&clks IMX6UL_CLK_GPMI_BCH>,
181 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
182 <&clks IMX6UL_CLK_PER_BCH>;
183 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
184 "gpmi_bch_apb", "per1_bch";
185 dmas = <&dma_apbh 0>;
186 dma-names = "rx-tx";
187 status = "disabled";
188 };
189
190 aips1: aips-bus@02000000 {
191 compatible = "fsl,aips-bus", "simple-bus";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 reg = <0x02000000 0x100000>;
195 ranges;
196
197 spba-bus@02000000 {
198 compatible = "fsl,spba-bus", "simple-bus";
199 #address-cells = <1>;
200 #size-cells = <1>;
201 reg = <0x02000000 0x40000>;
202 ranges;
203
204 ecspi1: ecspi@02008000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02008000 0x4000>;
209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6UL_CLK_ECSPI1>,
211 <&clks IMX6UL_CLK_ECSPI1>;
212 clock-names = "ipg", "per";
213 status = "disabled";
214 };
215
216 ecspi2: ecspi@0200c000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
220 reg = <0x0200c000 0x4000>;
221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clks IMX6UL_CLK_ECSPI2>,
223 <&clks IMX6UL_CLK_ECSPI2>;
224 clock-names = "ipg", "per";
225 status = "disabled";
226 };
227
228 ecspi3: ecspi@02010000 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
232 reg = <0x02010000 0x4000>;
233 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6UL_CLK_ECSPI3>,
235 <&clks IMX6UL_CLK_ECSPI3>;
236 clock-names = "ipg", "per";
237 status = "disabled";
238 };
239
240 ecspi4: ecspi@02014000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
244 reg = <0x02014000 0x4000>;
245 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&clks IMX6UL_CLK_ECSPI4>,
247 <&clks IMX6UL_CLK_ECSPI4>;
248 clock-names = "ipg", "per";
249 status = "disabled";
250 };
251
252 uart7: serial@02018000 {
253 compatible = "fsl,imx6ul-uart",
254 "fsl,imx6q-uart";
255 reg = <0x02018000 0x4000>;
256 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
258 <&clks IMX6UL_CLK_UART7_SERIAL>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
262
263 uart1: serial@02020000 {
264 compatible = "fsl,imx6ul-uart",
265 "fsl,imx6q-uart";
266 reg = <0x02020000 0x4000>;
267 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
269 <&clks IMX6UL_CLK_UART1_SERIAL>;
270 clock-names = "ipg", "per";
271 status = "disabled";
272 };
273
274 uart8: serial@02024000 {
275 compatible = "fsl,imx6ul-uart",
276 "fsl,imx6q-uart";
277 reg = <0x02024000 0x4000>;
278 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
280 <&clks IMX6UL_CLK_UART8_SERIAL>;
281 clock-names = "ipg", "per";
282 status = "disabled";
283 };
284
285 sai1: sai@02028000 {
286 #sound-dai-cells = <0>;
287 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
288 reg = <0x02028000 0x4000>;
289 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
291 <&clks IMX6UL_CLK_SAI1>,
292 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
293 clock-names = "bus", "mclk1", "mclk2", "mclk3";
294 dmas = <&sdma 35 24 0>,
295 <&sdma 36 24 0>;
296 dma-names = "rx", "tx";
297 status = "disabled";
298 };
299
300 sai2: sai@0202c000 {
301 #sound-dai-cells = <0>;
302 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
303 reg = <0x0202c000 0x4000>;
304 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
306 <&clks IMX6UL_CLK_SAI2>,
307 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
308 clock-names = "bus", "mclk1", "mclk2", "mclk3";
309 dmas = <&sdma 37 24 0>,
310 <&sdma 38 24 0>;
311 dma-names = "rx", "tx";
312 status = "disabled";
313 };
314
315 sai3: sai@02030000 {
316 #sound-dai-cells = <0>;
317 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
318 reg = <0x02030000 0x4000>;
319 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
321 <&clks IMX6UL_CLK_SAI3>,
322 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
323 clock-names = "bus", "mclk1", "mclk2", "mclk3";
324 dmas = <&sdma 39 24 0>,
325 <&sdma 40 24 0>;
326 dma-names = "rx", "tx";
327 status = "disabled";
328 };
329 };
330
331 tsc: tsc@02040000 {
332 compatible = "fsl,imx6ul-tsc";
333 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&clks IMX6UL_CLK_IPG>,
337 <&clks IMX6UL_CLK_ADC2>;
338 clock-names = "tsc", "adc";
339 status = "disabled";
340 };
341
342 pwm1: pwm@02080000 {
343 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
344 reg = <0x02080000 0x4000>;
345 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clks IMX6UL_CLK_PWM1>,
347 <&clks IMX6UL_CLK_PWM1>;
348 clock-names = "ipg", "per";
349 #pwm-cells = <2>;
350 status = "disabled";
351 };
352
353 pwm2: pwm@02084000 {
354 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
355 reg = <0x02084000 0x4000>;
356 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clks IMX6UL_CLK_PWM2>,
358 <&clks IMX6UL_CLK_PWM2>;
359 clock-names = "ipg", "per";
360 #pwm-cells = <2>;
361 status = "disabled";
362 };
363
364 pwm3: pwm@02088000 {
365 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
366 reg = <0x02088000 0x4000>;
367 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks IMX6UL_CLK_PWM3>,
369 <&clks IMX6UL_CLK_PWM3>;
370 clock-names = "ipg", "per";
371 #pwm-cells = <2>;
372 status = "disabled";
373 };
374
375 pwm4: pwm@0208c000 {
376 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
377 reg = <0x0208c000 0x4000>;
378 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX6UL_CLK_PWM4>,
380 <&clks IMX6UL_CLK_PWM4>;
381 clock-names = "ipg", "per";
382 #pwm-cells = <2>;
383 status = "disabled";
384 };
385
386 can1: flexcan@02090000 {
387 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
388 reg = <0x02090000 0x4000>;
389 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
391 <&clks IMX6UL_CLK_CAN1_SERIAL>;
392 clock-names = "ipg", "per";
393 status = "disabled";
394 };
395
396 can2: flexcan@02094000 {
397 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
398 reg = <0x02094000 0x4000>;
399 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
401 <&clks IMX6UL_CLK_CAN2_SERIAL>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
405
406 gpt1: gpt@02098000 {
407 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
408 reg = <0x02098000 0x4000>;
409 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
411 <&clks IMX6UL_CLK_GPT1_SERIAL>;
412 clock-names = "ipg", "per";
413 };
414
415 gpio1: gpio@0209c000 {
416 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
417 reg = <0x0209c000 0x4000>;
418 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
425 <&iomuxc 16 33 16>;
426 };
427
428 gpio2: gpio@020a0000 {
429 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
430 reg = <0x020a0000 0x4000>;
431 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
438 };
439
440 gpio3: gpio@020a4000 {
441 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
442 reg = <0x020a4000 0x4000>;
443 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
445 gpio-controller;
446 #gpio-cells = <2>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 gpio-ranges = <&iomuxc 0 65 29>;
450 };
451
452 gpio4: gpio@020a8000 {
453 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
454 reg = <0x020a8000 0x4000>;
455 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
462 };
463
464 gpio5: gpio@020ac000 {
465 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
466 reg = <0x020ac000 0x4000>;
467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
474 };
475
476 fec2: ethernet@020b4000 {
477 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
478 reg = <0x020b4000 0x4000>;
479 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX6UL_CLK_ENET>,
482 <&clks IMX6UL_CLK_ENET_AHB>,
483 <&clks IMX6UL_CLK_ENET_PTP>,
484 <&clks IMX6UL_CLK_ENET2_REF_125M>,
485 <&clks IMX6UL_CLK_ENET2_REF_125M>;
486 clock-names = "ipg", "ahb", "ptp",
487 "enet_clk_ref", "enet_out";
488 fsl,num-tx-queues=<1>;
489 fsl,num-rx-queues=<1>;
490 status = "disabled";
491 };
492
493 kpp: kpp@020b8000 {
494 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
495 reg = <0x020b8000 0x4000>;
496 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clks IMX6UL_CLK_KPP>;
498 status = "disabled";
499 };
500
501 wdog1: wdog@020bc000 {
502 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
503 reg = <0x020bc000 0x4000>;
504 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clks IMX6UL_CLK_WDOG1>;
506 };
507
508 wdog2: wdog@020c0000 {
509 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
510 reg = <0x020c0000 0x4000>;
511 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clks IMX6UL_CLK_WDOG2>;
513 status = "disabled";
514 };
515
516 clks: ccm@020c4000 {
517 compatible = "fsl,imx6ul-ccm";
518 reg = <0x020c4000 0x4000>;
519 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
521 #clock-cells = <1>;
522 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
523 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
524 };
525
526 anatop: anatop@020c8000 {
527 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
528 "syscon", "simple-bus";
529 reg = <0x020c8000 0x1000>;
530 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
533
534 reg_3p0: regulator-3p0 {
535 compatible = "fsl,anatop-regulator";
536 regulator-name = "vdd3p0";
537 regulator-min-microvolt = <2625000>;
538 regulator-max-microvolt = <3400000>;
539 anatop-reg-offset = <0x120>;
540 anatop-vol-bit-shift = <8>;
541 anatop-vol-bit-width = <5>;
542 anatop-min-bit-val = <0>;
543 anatop-min-voltage = <2625000>;
544 anatop-max-voltage = <3400000>;
545 anatop-enable-bit = <0>;
546 };
547
548 reg_arm: regulator-vddcore {
549 compatible = "fsl,anatop-regulator";
550 regulator-name = "cpu";
551 regulator-min-microvolt = <725000>;
552 regulator-max-microvolt = <1450000>;
553 regulator-always-on;
554 anatop-reg-offset = <0x140>;
555 anatop-vol-bit-shift = <0>;
556 anatop-vol-bit-width = <5>;
557 anatop-delay-reg-offset = <0x170>;
558 anatop-delay-bit-shift = <24>;
559 anatop-delay-bit-width = <2>;
560 anatop-min-bit-val = <1>;
561 anatop-min-voltage = <725000>;
562 anatop-max-voltage = <1450000>;
563 };
564
565 reg_soc: regulator-vddsoc {
566 compatible = "fsl,anatop-regulator";
567 regulator-name = "vddsoc";
568 regulator-min-microvolt = <725000>;
569 regulator-max-microvolt = <1450000>;
570 regulator-always-on;
571 anatop-reg-offset = <0x140>;
572 anatop-vol-bit-shift = <18>;
573 anatop-vol-bit-width = <5>;
574 anatop-delay-reg-offset = <0x170>;
575 anatop-delay-bit-shift = <28>;
576 anatop-delay-bit-width = <2>;
577 anatop-min-bit-val = <1>;
578 anatop-min-voltage = <725000>;
579 anatop-max-voltage = <1450000>;
580 };
581 };
582
583 usbphy1: usbphy@020c9000 {
584 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
585 reg = <0x020c9000 0x1000>;
586 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&clks IMX6UL_CLK_USBPHY1>;
588 phy-3p0-supply = <®_3p0>;
589 fsl,anatop = <&anatop>;
590 };
591
592 usbphy2: usbphy@020ca000 {
593 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
594 reg = <0x020ca000 0x1000>;
595 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&clks IMX6UL_CLK_USBPHY2>;
597 phy-3p0-supply = <®_3p0>;
598 fsl,anatop = <&anatop>;
599 };
600
601 snvs: snvs@020cc000 {
602 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
603 reg = <0x020cc000 0x4000>;
604
605 snvs_rtc: snvs-rtc-lp {
606 compatible = "fsl,sec-v4.0-mon-rtc-lp";
607 regmap = <&snvs>;
608 offset = <0x34>;
609 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
611 };
612
613 snvs_poweroff: snvs-poweroff {
614 compatible = "syscon-poweroff";
615 regmap = <&snvs>;
616 offset = <0x38>;
617 mask = <0x60>;
618 status = "disabled";
619 };
620
621 snvs_pwrkey: snvs-powerkey {
622 compatible = "fsl,sec-v4.0-pwrkey";
623 regmap = <&snvs>;
624 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
625 linux,keycode = <KEY_POWER>;
626 wakeup-source;
627 };
628 };
629
630 epit1: epit@020d0000 {
631 reg = <0x020d0000 0x4000>;
632 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
633 };
634
635 epit2: epit@020d4000 {
636 reg = <0x020d4000 0x4000>;
637 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
638 };
639
640 src: src@020d8000 {
641 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
642 reg = <0x020d8000 0x4000>;
643 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
645 #reset-cells = <1>;
646 };
647
648 gpc: gpc@020dc000 {
649 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
650 reg = <0x020dc000 0x4000>;
651 interrupt-controller;
652 #interrupt-cells = <3>;
653 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
654 interrupt-parent = <&intc>;
655 };
656
657 iomuxc: iomuxc@020e0000 {
658 compatible = "fsl,imx6ul-iomuxc";
659 reg = <0x020e0000 0x4000>;
660 };
661
662 gpr: iomuxc-gpr@020e4000 {
663 compatible = "fsl,imx6ul-iomuxc-gpr",
664 "fsl,imx6q-iomuxc-gpr", "syscon";
665 reg = <0x020e4000 0x4000>;
666 };
667
668 gpt2: gpt@020e8000 {
669 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
670 reg = <0x020e8000 0x4000>;
671 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
673 <&clks IMX6UL_CLK_GPT2_SERIAL>;
674 clock-names = "ipg", "per";
675 };
676
677 sdma: sdma@020ec000 {
678 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
679 "fsl,imx35-sdma";
680 reg = <0x020ec000 0x4000>;
681 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clks IMX6UL_CLK_SDMA>,
683 <&clks IMX6UL_CLK_SDMA>;
684 clock-names = "ipg", "ahb";
685 #dma-cells = <3>;
686 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
687 };
688
689 pwm5: pwm@020f0000 {
690 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
691 reg = <0x020f0000 0x4000>;
692 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clks IMX6UL_CLK_PWM5>,
694 <&clks IMX6UL_CLK_PWM5>;
695 clock-names = "ipg", "per";
696 #pwm-cells = <2>;
697 status = "disabled";
698 };
699
700 pwm6: pwm@020f4000 {
701 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
702 reg = <0x020f4000 0x4000>;
703 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clks IMX6UL_CLK_PWM6>,
705 <&clks IMX6UL_CLK_PWM6>;
706 clock-names = "ipg", "per";
707 #pwm-cells = <2>;
708 status = "disabled";
709 };
710
711 pwm7: pwm@020f8000 {
712 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
713 reg = <0x020f8000 0x4000>;
714 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clks IMX6UL_CLK_PWM7>,
716 <&clks IMX6UL_CLK_PWM7>;
717 clock-names = "ipg", "per";
718 #pwm-cells = <2>;
719 status = "disabled";
720 };
721
722 pwm8: pwm@020fc000 {
723 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
724 reg = <0x020fc000 0x4000>;
725 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clks IMX6UL_CLK_PWM8>,
727 <&clks IMX6UL_CLK_PWM8>;
728 clock-names = "ipg", "per";
729 #pwm-cells = <2>;
730 status = "disabled";
731 };
732 };
733
734 aips2: aips-bus@02100000 {
735 compatible = "fsl,aips-bus", "simple-bus";
736 #address-cells = <1>;
737 #size-cells = <1>;
738 reg = <0x02100000 0x100000>;
739 ranges;
740
741 usbotg1: usb@02184000 {
742 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
743 reg = <0x02184000 0x200>;
744 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clks IMX6UL_CLK_USBOH3>;
746 fsl,usbphy = <&usbphy1>;
747 fsl,usbmisc = <&usbmisc 0>;
748 fsl,anatop = <&anatop>;
749 ahb-burst-config = <0x0>;
750 tx-burst-size-dword = <0x10>;
751 rx-burst-size-dword = <0x10>;
752 status = "disabled";
753 };
754
755 usbotg2: usb@02184200 {
756 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
757 reg = <0x02184200 0x200>;
758 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clks IMX6UL_CLK_USBOH3>;
760 fsl,usbphy = <&usbphy2>;
761 fsl,usbmisc = <&usbmisc 1>;
762 ahb-burst-config = <0x0>;
763 tx-burst-size-dword = <0x10>;
764 rx-burst-size-dword = <0x10>;
765 status = "disabled";
766 };
767
768 usbmisc: usbmisc@02184800 {
769 #index-cells = <1>;
770 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
771 reg = <0x02184800 0x200>;
772 };
773
774 fec1: ethernet@02188000 {
775 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
776 reg = <0x02188000 0x4000>;
777 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clks IMX6UL_CLK_ENET>,
780 <&clks IMX6UL_CLK_ENET_AHB>,
781 <&clks IMX6UL_CLK_ENET_PTP>,
782 <&clks IMX6UL_CLK_ENET_REF>,
783 <&clks IMX6UL_CLK_ENET_REF>;
784 clock-names = "ipg", "ahb", "ptp",
785 "enet_clk_ref", "enet_out";
786 fsl,num-tx-queues=<1>;
787 fsl,num-rx-queues=<1>;
788 status = "disabled";
789 };
790
791 usdhc1: usdhc@02190000 {
792 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
793 reg = <0x02190000 0x4000>;
794 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clks IMX6UL_CLK_USDHC1>,
796 <&clks IMX6UL_CLK_USDHC1>,
797 <&clks IMX6UL_CLK_USDHC1>;
798 clock-names = "ipg", "ahb", "per";
799 bus-width = <4>;
800 status = "disabled";
801 };
802
803 usdhc2: usdhc@02194000 {
804 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
805 reg = <0x02194000 0x4000>;
806 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clks IMX6UL_CLK_USDHC2>,
808 <&clks IMX6UL_CLK_USDHC2>,
809 <&clks IMX6UL_CLK_USDHC2>;
810 clock-names = "ipg", "ahb", "per";
811 bus-width = <4>;
812 status = "disabled";
813 };
814
815 adc1: adc@02198000 {
816 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
817 reg = <0x02198000 0x4000>;
818 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6UL_CLK_ADC1>;
820 num-channels = <2>;
821 clock-names = "adc";
822 fsl,adck-max-frequency = <30000000>, <40000000>,
823 <20000000>;
824 status = "disabled";
825 };
826
827 i2c1: i2c@021a0000 {
828 #address-cells = <1>;
829 #size-cells = <0>;
830 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
831 reg = <0x021a0000 0x4000>;
832 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clks IMX6UL_CLK_I2C1>;
834 status = "disabled";
835 };
836
837 i2c2: i2c@021a4000 {
838 #address-cells = <1>;
839 #size-cells = <0>;
840 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
841 reg = <0x021a4000 0x4000>;
842 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clks IMX6UL_CLK_I2C2>;
844 status = "disabled";
845 };
846
847 i2c3: i2c@021a8000 {
848 #address-cells = <1>;
849 #size-cells = <0>;
850 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
851 reg = <0x021a8000 0x4000>;
852 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&clks IMX6UL_CLK_I2C3>;
854 status = "disabled";
855 };
856
857 mmdc: mmdc@021b0000 {
858 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
859 reg = <0x021b0000 0x4000>;
860 };
861
862 lcdif: lcdif@021c8000 {
863 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
864 reg = <0x021c8000 0x4000>;
865 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
867 <&clks IMX6UL_CLK_LCDIF_APB>,
868 <&clks IMX6UL_CLK_DUMMY>;
869 clock-names = "pix", "axi", "disp_axi";
870 status = "disabled";
871 };
872
873 qspi: qspi@021e0000 {
874 #address-cells = <1>;
875 #size-cells = <0>;
876 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
877 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
878 reg-names = "QuadSPI", "QuadSPI-memory";
879 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&clks IMX6UL_CLK_QSPI>,
881 <&clks IMX6UL_CLK_QSPI>;
882 clock-names = "qspi_en", "qspi";
883 status = "disabled";
884 };
885
886 uart2: serial@021e8000 {
887 compatible = "fsl,imx6ul-uart",
888 "fsl,imx6q-uart";
889 reg = <0x021e8000 0x4000>;
890 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
892 <&clks IMX6UL_CLK_UART2_SERIAL>;
893 clock-names = "ipg", "per";
894 status = "disabled";
895 };
896
897 uart3: serial@021ec000 {
898 compatible = "fsl,imx6ul-uart",
899 "fsl,imx6q-uart";
900 reg = <0x021ec000 0x4000>;
901 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
903 <&clks IMX6UL_CLK_UART3_SERIAL>;
904 clock-names = "ipg", "per";
905 status = "disabled";
906 };
907
908 uart4: serial@021f0000 {
909 compatible = "fsl,imx6ul-uart",
910 "fsl,imx6q-uart";
911 reg = <0x021f0000 0x4000>;
912 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
914 <&clks IMX6UL_CLK_UART4_SERIAL>;
915 clock-names = "ipg", "per";
916 status = "disabled";
917 };
918
919 uart5: serial@021f4000 {
920 compatible = "fsl,imx6ul-uart",
921 "fsl,imx6q-uart";
922 reg = <0x021f4000 0x4000>;
923 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
925 <&clks IMX6UL_CLK_UART5_SERIAL>;
926 clock-names = "ipg", "per";
927 status = "disabled";
928 };
929
930 i2c4: i2c@021f8000 {
931 #address-cells = <1>;
932 #size-cells = <0>;
933 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
934 reg = <0x021f8000 0x4000>;
935 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6UL_CLK_I2C4>;
937 status = "disabled";
938 };
939
940 uart6: serial@021fc000 {
941 compatible = "fsl,imx6ul-uart",
942 "fsl,imx6q-uart";
943 reg = <0x021fc000 0x4000>;
944 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
946 <&clks IMX6UL_CLK_UART6_SERIAL>;
947 clock-names = "ipg", "per";
948 status = "disabled";
949 };
950 };
951 };
952};