Loading...
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/clock/imx6qdl-clock.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/input/input.h>
16
17/ {
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 memory@10000000 {
23 reg = <0x10000000 0x40000000>;
24 };
25
26 regulators {
27 compatible = "simple-bus";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 reg_usb_otg_vbus: regulator@0 {
32 compatible = "regulator-fixed";
33 reg = <0>;
34 regulator-name = "usb_otg_vbus";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
37 gpio = <&gpio3 22 0>;
38 enable-active-high;
39 vin-supply = <&swbst_reg>;
40 };
41
42 reg_usb_h1_vbus: regulator@1 {
43 compatible = "regulator-fixed";
44 reg = <1>;
45 regulator-name = "usb_h1_vbus";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 gpio = <&gpio1 29 0>;
49 enable-active-high;
50 vin-supply = <&swbst_reg>;
51 };
52
53 reg_audio: regulator@2 {
54 compatible = "regulator-fixed";
55 reg = <2>;
56 regulator-name = "wm8962-supply";
57 gpio = <&gpio4 10 0>;
58 enable-active-high;
59 };
60
61 reg_pcie: regulator@3 {
62 compatible = "regulator-fixed";
63 reg = <3>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_pcie_reg>;
66 regulator-name = "MPCIE_3V3";
67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <3300000>;
69 gpio = <&gpio3 19 0>;
70 enable-active-high;
71 };
72 };
73
74 gpio-keys {
75 compatible = "gpio-keys";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_gpio_keys>;
78
79 power {
80 label = "Power Button";
81 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
82 wakeup-source;
83 linux,code = <KEY_POWER>;
84 };
85
86 volume-up {
87 label = "Volume Up";
88 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
89 wakeup-source;
90 linux,code = <KEY_VOLUMEUP>;
91 };
92
93 volume-down {
94 label = "Volume Down";
95 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
96 wakeup-source;
97 linux,code = <KEY_VOLUMEDOWN>;
98 };
99 };
100
101 sound {
102 compatible = "fsl,imx6q-sabresd-wm8962",
103 "fsl,imx-audio-wm8962";
104 model = "wm8962-audio";
105 ssi-controller = <&ssi2>;
106 audio-codec = <&codec>;
107 audio-routing =
108 "Headphone Jack", "HPOUTL",
109 "Headphone Jack", "HPOUTR",
110 "Ext Spk", "SPKOUTL",
111 "Ext Spk", "SPKOUTR",
112 "AMIC", "MICBIAS",
113 "IN3R", "AMIC";
114 mux-int-port = <2>;
115 mux-ext-port = <3>;
116 };
117
118 backlight_lvds: backlight-lvds {
119 compatible = "pwm-backlight";
120 pwms = <&pwm1 0 5000000>;
121 brightness-levels = <0 4 8 16 32 64 128 255>;
122 default-brightness-level = <7>;
123 status = "okay";
124 };
125
126 leds {
127 compatible = "gpio-leds";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_gpio_leds>;
130
131 red {
132 gpios = <&gpio1 2 0>;
133 default-state = "on";
134 };
135 };
136
137 panel {
138 compatible = "hannstar,hsd100pxn1";
139 backlight = <&backlight_lvds>;
140
141 port {
142 panel_in: endpoint {
143 remote-endpoint = <&lvds0_out>;
144 };
145 };
146 };
147};
148
149&ipu1_csi0_from_ipu1_csi0_mux {
150 bus-width = <8>;
151 data-shift = <12>; /* Lines 19:12 used */
152 hsync-active = <1>;
153 vsync-active = <1>;
154};
155
156&ipu1_csi0_mux_from_parallel_sensor {
157 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
158};
159
160&ipu1_csi0 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_ipu1_csi0>;
163};
164
165&mipi_csi {
166 status = "okay";
167
168 port@0 {
169 reg = <0>;
170
171 mipi_csi2_in: endpoint {
172 remote-endpoint = <&ov5640_to_mipi_csi2>;
173 clock-lanes = <0>;
174 data-lanes = <1 2>;
175 };
176 };
177};
178
179&audmux {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_audmux>;
182 status = "okay";
183};
184
185&clks {
186 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
187 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
188 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
189 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
190};
191
192&ecspi1 {
193 cs-gpios = <&gpio4 9 0>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_ecspi1>;
196 status = "okay";
197
198 flash: m25p80@0 {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 compatible = "st,m25p32", "jedec,spi-nor";
202 spi-max-frequency = <20000000>;
203 reg = <0>;
204 };
205};
206
207&fec {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_enet>;
210 phy-mode = "rgmii";
211 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
212 status = "okay";
213};
214
215&hdmi {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_hdmi_cec>;
218 ddc-i2c-bus = <&i2c2>;
219 status = "okay";
220};
221
222&i2c1 {
223 clock-frequency = <100000>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_i2c1>;
226 status = "okay";
227
228 codec: wm8962@1a {
229 compatible = "wlf,wm8962";
230 reg = <0x1a>;
231 clocks = <&clks IMX6QDL_CLK_CKO>;
232 DCVDD-supply = <®_audio>;
233 DBVDD-supply = <®_audio>;
234 AVDD-supply = <®_audio>;
235 CPVDD-supply = <®_audio>;
236 MICVDD-supply = <®_audio>;
237 PLLVDD-supply = <®_audio>;
238 SPKVDD1-supply = <®_audio>;
239 SPKVDD2-supply = <®_audio>;
240 gpio-cfg = <
241 0x0000 /* 0:Default */
242 0x0000 /* 1:Default */
243 0x0013 /* 2:FN_DMICCLK */
244 0x0000 /* 3:Default */
245 0x8014 /* 4:FN_DMICCDAT */
246 0x0000 /* 5:Default */
247 >;
248 };
249
250 ov5642: camera@3c {
251 compatible = "ovti,ov5642";
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_ov5642>;
254 clocks = <&clks IMX6QDL_CLK_CKO>;
255 clock-names = "xclk";
256 reg = <0x3c>;
257 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
258 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
259 rev B board is VGEN5 */
260 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
261 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
262 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
263 status = "disabled";
264
265 port {
266 ov5642_to_ipu1_csi0_mux: endpoint {
267 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
268 bus-width = <8>;
269 hsync-active = <1>;
270 vsync-active = <1>;
271 };
272 };
273 };
274};
275
276&i2c2 {
277 clock-frequency = <100000>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c2>;
280 status = "okay";
281
282 ov5640: camera@3c {
283 compatible = "ovti,ov5640";
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_ov5640>;
286 reg = <0x3c>;
287 clocks = <&clks IMX6QDL_CLK_CKO>;
288 clock-names = "xclk";
289 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
290 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
291 rev B board is VGEN5 */
292 DVDD-supply = <&vgen2_reg>; /* 1.5v*/
293 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
294 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
295
296 port {
297 #address-cells = <1>;
298 #size-cells = <0>;
299
300 ov5640_to_mipi_csi2: endpoint {
301 remote-endpoint = <&mipi_csi2_in>;
302 clock-lanes = <0>;
303 data-lanes = <1 2>;
304 };
305 };
306 };
307
308 pmic: pfuze100@8 {
309 compatible = "fsl,pfuze100";
310 reg = <0x08>;
311
312 regulators {
313 sw1a_reg: sw1ab {
314 regulator-min-microvolt = <300000>;
315 regulator-max-microvolt = <1875000>;
316 regulator-boot-on;
317 regulator-always-on;
318 regulator-ramp-delay = <6250>;
319 };
320
321 sw1c_reg: sw1c {
322 regulator-min-microvolt = <300000>;
323 regulator-max-microvolt = <1875000>;
324 regulator-boot-on;
325 regulator-always-on;
326 regulator-ramp-delay = <6250>;
327 };
328
329 sw2_reg: sw2 {
330 regulator-min-microvolt = <800000>;
331 regulator-max-microvolt = <3300000>;
332 regulator-boot-on;
333 regulator-always-on;
334 regulator-ramp-delay = <6250>;
335 };
336
337 sw3a_reg: sw3a {
338 regulator-min-microvolt = <400000>;
339 regulator-max-microvolt = <1975000>;
340 regulator-boot-on;
341 regulator-always-on;
342 };
343
344 sw3b_reg: sw3b {
345 regulator-min-microvolt = <400000>;
346 regulator-max-microvolt = <1975000>;
347 regulator-boot-on;
348 regulator-always-on;
349 };
350
351 sw4_reg: sw4 {
352 regulator-min-microvolt = <800000>;
353 regulator-max-microvolt = <3300000>;
354 };
355
356 swbst_reg: swbst {
357 regulator-min-microvolt = <5000000>;
358 regulator-max-microvolt = <5150000>;
359 };
360
361 snvs_reg: vsnvs {
362 regulator-min-microvolt = <1000000>;
363 regulator-max-microvolt = <3000000>;
364 regulator-boot-on;
365 regulator-always-on;
366 };
367
368 vref_reg: vrefddr {
369 regulator-boot-on;
370 regulator-always-on;
371 };
372
373 vgen1_reg: vgen1 {
374 regulator-min-microvolt = <800000>;
375 regulator-max-microvolt = <1550000>;
376 };
377
378 vgen2_reg: vgen2 {
379 regulator-min-microvolt = <800000>;
380 regulator-max-microvolt = <1550000>;
381 };
382
383 vgen3_reg: vgen3 {
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <3300000>;
386 };
387
388 vgen4_reg: vgen4 {
389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <3300000>;
391 regulator-always-on;
392 };
393
394 vgen5_reg: vgen5 {
395 regulator-min-microvolt = <1800000>;
396 regulator-max-microvolt = <3300000>;
397 regulator-always-on;
398 };
399
400 vgen6_reg: vgen6 {
401 regulator-min-microvolt = <1800000>;
402 regulator-max-microvolt = <3300000>;
403 regulator-always-on;
404 };
405 };
406 };
407};
408
409&i2c3 {
410 clock-frequency = <100000>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_i2c3>;
413 status = "okay";
414
415 egalax_ts@4 {
416 compatible = "eeti,egalax_ts";
417 reg = <0x04>;
418 interrupt-parent = <&gpio6>;
419 interrupts = <7 2>;
420 wakeup-gpios = <&gpio6 7 0>;
421 };
422};
423
424&iomuxc {
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_hog>;
427
428 imx6qdl-sabresd {
429 pinctrl_hog: hoggrp {
430 fsl,pins = <
431 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
432 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
433 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
434 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
435 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
436 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
437 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
438 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
439 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
440 >;
441 };
442
443 pinctrl_audmux: audmuxgrp {
444 fsl,pins = <
445 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
446 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
447 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
448 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
449 >;
450 };
451
452 pinctrl_ecspi1: ecspi1grp {
453 fsl,pins = <
454 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
455 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
456 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
457 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
458 >;
459 };
460
461 pinctrl_enet: enetgrp {
462 fsl,pins = <
463 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
464 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
465 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
466 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
467 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
468 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
469 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
470 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
471 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
472 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
473 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
474 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
475 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
476 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
477 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
478 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
479 >;
480 };
481
482 pinctrl_gpio_keys: gpio_keysgrp {
483 fsl,pins = <
484 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
485 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
486 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
487 >;
488 };
489
490 pinctrl_hdmi_cec: hdmicecgrp {
491 fsl,pins = <
492 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
493 >;
494 };
495
496 pinctrl_i2c1: i2c1grp {
497 fsl,pins = <
498 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
499 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
500 >;
501 };
502
503 pinctrl_i2c2: i2c2grp {
504 fsl,pins = <
505 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
506 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
507 >;
508 };
509
510 pinctrl_i2c3: i2c3grp {
511 fsl,pins = <
512 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
513 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
514 >;
515 };
516
517 pinctrl_ipu1_csi0: ipu1csi0grp {
518 fsl,pins = <
519 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
520 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
521 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
522 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
523 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
524 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
525 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
526 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
527 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
528 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
529 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
530 >;
531 };
532
533 pinctrl_ov5640: ov5640grp {
534 fsl,pins = <
535 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
536 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
537 >;
538 };
539
540 pinctrl_ov5642: ov5642grp {
541 fsl,pins = <
542 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
543 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
544 >;
545 };
546
547 pinctrl_pcie: pciegrp {
548 fsl,pins = <
549 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
550 >;
551 };
552
553 pinctrl_pcie_reg: pciereggrp {
554 fsl,pins = <
555 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
556 >;
557 };
558
559 pinctrl_pwm1: pwm1grp {
560 fsl,pins = <
561 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
562 >;
563 };
564
565 pinctrl_uart1: uart1grp {
566 fsl,pins = <
567 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
568 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
569 >;
570 };
571
572 pinctrl_usbotg: usbotggrp {
573 fsl,pins = <
574 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
575 >;
576 };
577
578 pinctrl_usdhc2: usdhc2grp {
579 fsl,pins = <
580 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
581 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
582 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
583 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
584 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
585 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
586 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
587 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
588 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
589 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
590 >;
591 };
592
593 pinctrl_usdhc3: usdhc3grp {
594 fsl,pins = <
595 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
596 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
597 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
598 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
599 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
600 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
601 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
602 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
603 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
604 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
605 >;
606 };
607
608 pinctrl_usdhc4: usdhc4grp {
609 fsl,pins = <
610 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
611 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
612 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
613 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
614 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
615 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
616 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
617 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
618 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
619 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
620 >;
621 };
622
623 pinctrl_wdog: wdoggrp {
624 fsl,pins = <
625 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
626 >;
627 };
628 };
629
630 gpio_leds {
631 pinctrl_gpio_leds: gpioledsgrp {
632 fsl,pins = <
633 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
634 >;
635 };
636 };
637};
638
639&ldb {
640 status = "okay";
641
642 lvds-channel@1 {
643 fsl,data-mapping = "spwg";
644 fsl,data-width = <18>;
645 status = "okay";
646
647 port@4 {
648 reg = <4>;
649
650 lvds0_out: endpoint {
651 remote-endpoint = <&panel_in>;
652 };
653 };
654 };
655};
656
657&pcie {
658 pinctrl-names = "default";
659 pinctrl-0 = <&pinctrl_pcie>;
660 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
661 vpcie-supply = <®_pcie>;
662 status = "okay";
663};
664
665&pwm1 {
666 pinctrl-names = "default";
667 pinctrl-0 = <&pinctrl_pwm1>;
668 status = "okay";
669};
670
671®_arm {
672 vin-supply = <&sw1a_reg>;
673};
674
675®_pu {
676 vin-supply = <&sw1c_reg>;
677};
678
679®_soc {
680 vin-supply = <&sw1c_reg>;
681};
682
683&snvs_poweroff {
684 status = "okay";
685};
686
687&ssi2 {
688 status = "okay";
689};
690
691&uart1 {
692 pinctrl-names = "default";
693 pinctrl-0 = <&pinctrl_uart1>;
694 status = "okay";
695};
696
697&usbh1 {
698 vbus-supply = <®_usb_h1_vbus>;
699 status = "okay";
700};
701
702&usbotg {
703 vbus-supply = <®_usb_otg_vbus>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&pinctrl_usbotg>;
706 disable-over-current;
707 status = "okay";
708};
709
710&usdhc2 {
711 pinctrl-names = "default";
712 pinctrl-0 = <&pinctrl_usdhc2>;
713 bus-width = <8>;
714 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
715 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
716 status = "okay";
717};
718
719&usdhc3 {
720 pinctrl-names = "default";
721 pinctrl-0 = <&pinctrl_usdhc3>;
722 bus-width = <8>;
723 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
724 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
725 status = "okay";
726};
727
728&usdhc4 {
729 pinctrl-names = "default";
730 pinctrl-0 = <&pinctrl_usdhc4>;
731 bus-width = <8>;
732 non-removable;
733 no-1-8-v;
734 status = "okay";
735};
736
737&wdog1 {
738 status = "disabled";
739};
740
741&wdog2 {
742 pinctrl-names = "default";
743 pinctrl-0 = <&pinctrl_wdog>;
744 fsl,ext-reset-output;
745 status = "okay";
746};
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15
16/ {
17 chosen {
18 stdout-path = &uart1;
19 };
20
21 memory {
22 reg = <0x10000000 0x40000000>;
23 };
24
25 regulators {
26 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 reg_usb_otg_vbus: regulator@0 {
31 compatible = "regulator-fixed";
32 reg = <0>;
33 regulator-name = "usb_otg_vbus";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 22 0>;
37 enable-active-high;
38 vin-supply = <&swbst_reg>;
39 };
40
41 reg_usb_h1_vbus: regulator@1 {
42 compatible = "regulator-fixed";
43 reg = <1>;
44 regulator-name = "usb_h1_vbus";
45 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>;
47 gpio = <&gpio1 29 0>;
48 enable-active-high;
49 vin-supply = <&swbst_reg>;
50 };
51
52 reg_audio: regulator@2 {
53 compatible = "regulator-fixed";
54 reg = <2>;
55 regulator-name = "wm8962-supply";
56 gpio = <&gpio4 10 0>;
57 enable-active-high;
58 };
59
60 reg_pcie: regulator@3 {
61 compatible = "regulator-fixed";
62 reg = <3>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pcie_reg>;
65 regulator-name = "MPCIE_3V3";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 gpio = <&gpio3 19 0>;
69 regulator-always-on;
70 enable-active-high;
71 };
72 };
73
74 gpio-keys {
75 compatible = "gpio-keys";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_gpio_keys>;
78
79 power {
80 label = "Power Button";
81 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
82 wakeup-source;
83 linux,code = <KEY_POWER>;
84 };
85
86 volume-up {
87 label = "Volume Up";
88 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
89 wakeup-source;
90 linux,code = <KEY_VOLUMEUP>;
91 };
92
93 volume-down {
94 label = "Volume Down";
95 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
96 wakeup-source;
97 linux,code = <KEY_VOLUMEDOWN>;
98 };
99 };
100
101 sound {
102 compatible = "fsl,imx6q-sabresd-wm8962",
103 "fsl,imx-audio-wm8962";
104 model = "wm8962-audio";
105 ssi-controller = <&ssi2>;
106 audio-codec = <&codec>;
107 audio-routing =
108 "Headphone Jack", "HPOUTL",
109 "Headphone Jack", "HPOUTR",
110 "Ext Spk", "SPKOUTL",
111 "Ext Spk", "SPKOUTR",
112 "AMIC", "MICBIAS",
113 "IN3R", "AMIC";
114 mux-int-port = <2>;
115 mux-ext-port = <3>;
116 };
117
118 backlight_lvds: backlight-lvds {
119 compatible = "pwm-backlight";
120 pwms = <&pwm1 0 5000000>;
121 brightness-levels = <0 4 8 16 32 64 128 255>;
122 default-brightness-level = <7>;
123 status = "okay";
124 };
125
126 leds {
127 compatible = "gpio-leds";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_gpio_leds>;
130
131 red {
132 gpios = <&gpio1 2 0>;
133 default-state = "on";
134 };
135 };
136
137 panel {
138 compatible = "hannstar,hsd100pxn1";
139 backlight = <&backlight_lvds>;
140
141 port {
142 panel_in: endpoint {
143 remote-endpoint = <&lvds0_out>;
144 };
145 };
146 };
147};
148
149&audmux {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_audmux>;
152 status = "okay";
153};
154
155&clks {
156 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
157 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
158 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
159 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
160};
161
162&ecspi1 {
163 fsl,spi-num-chipselects = <1>;
164 cs-gpios = <&gpio4 9 0>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_ecspi1>;
167 status = "okay";
168
169 flash: m25p80@0 {
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "st,m25p32", "jedec,spi-nor";
173 spi-max-frequency = <20000000>;
174 reg = <0>;
175 };
176};
177
178&fec {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_enet>;
181 phy-mode = "rgmii";
182 phy-reset-gpios = <&gpio1 25 0>;
183 status = "okay";
184};
185
186&hdmi {
187 ddc-i2c-bus = <&i2c2>;
188 status = "okay";
189};
190
191&i2c1 {
192 clock-frequency = <100000>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_i2c1>;
195 status = "okay";
196
197 codec: wm8962@1a {
198 compatible = "wlf,wm8962";
199 reg = <0x1a>;
200 clocks = <&clks IMX6QDL_CLK_CKO>;
201 DCVDD-supply = <®_audio>;
202 DBVDD-supply = <®_audio>;
203 AVDD-supply = <®_audio>;
204 CPVDD-supply = <®_audio>;
205 MICVDD-supply = <®_audio>;
206 PLLVDD-supply = <®_audio>;
207 SPKVDD1-supply = <®_audio>;
208 SPKVDD2-supply = <®_audio>;
209 gpio-cfg = <
210 0x0000 /* 0:Default */
211 0x0000 /* 1:Default */
212 0x0013 /* 2:FN_DMICCLK */
213 0x0000 /* 3:Default */
214 0x8014 /* 4:FN_DMICCDAT */
215 0x0000 /* 5:Default */
216 >;
217 };
218};
219
220&i2c2 {
221 clock-frequency = <100000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c2>;
224 status = "okay";
225
226 pmic: pfuze100@08 {
227 compatible = "fsl,pfuze100";
228 reg = <0x08>;
229
230 regulators {
231 sw1a_reg: sw1ab {
232 regulator-min-microvolt = <300000>;
233 regulator-max-microvolt = <1875000>;
234 regulator-boot-on;
235 regulator-always-on;
236 regulator-ramp-delay = <6250>;
237 };
238
239 sw1c_reg: sw1c {
240 regulator-min-microvolt = <300000>;
241 regulator-max-microvolt = <1875000>;
242 regulator-boot-on;
243 regulator-always-on;
244 regulator-ramp-delay = <6250>;
245 };
246
247 sw2_reg: sw2 {
248 regulator-min-microvolt = <800000>;
249 regulator-max-microvolt = <3300000>;
250 regulator-boot-on;
251 regulator-always-on;
252 regulator-ramp-delay = <6250>;
253 };
254
255 sw3a_reg: sw3a {
256 regulator-min-microvolt = <400000>;
257 regulator-max-microvolt = <1975000>;
258 regulator-boot-on;
259 regulator-always-on;
260 };
261
262 sw3b_reg: sw3b {
263 regulator-min-microvolt = <400000>;
264 regulator-max-microvolt = <1975000>;
265 regulator-boot-on;
266 regulator-always-on;
267 };
268
269 sw4_reg: sw4 {
270 regulator-min-microvolt = <800000>;
271 regulator-max-microvolt = <3300000>;
272 };
273
274 swbst_reg: swbst {
275 regulator-min-microvolt = <5000000>;
276 regulator-max-microvolt = <5150000>;
277 };
278
279 snvs_reg: vsnvs {
280 regulator-min-microvolt = <1000000>;
281 regulator-max-microvolt = <3000000>;
282 regulator-boot-on;
283 regulator-always-on;
284 };
285
286 vref_reg: vrefddr {
287 regulator-boot-on;
288 regulator-always-on;
289 };
290
291 vgen1_reg: vgen1 {
292 regulator-min-microvolt = <800000>;
293 regulator-max-microvolt = <1550000>;
294 };
295
296 vgen2_reg: vgen2 {
297 regulator-min-microvolt = <800000>;
298 regulator-max-microvolt = <1550000>;
299 };
300
301 vgen3_reg: vgen3 {
302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <3300000>;
304 };
305
306 vgen4_reg: vgen4 {
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <3300000>;
309 regulator-always-on;
310 };
311
312 vgen5_reg: vgen5 {
313 regulator-min-microvolt = <1800000>;
314 regulator-max-microvolt = <3300000>;
315 regulator-always-on;
316 };
317
318 vgen6_reg: vgen6 {
319 regulator-min-microvolt = <1800000>;
320 regulator-max-microvolt = <3300000>;
321 regulator-always-on;
322 };
323 };
324 };
325};
326
327&i2c3 {
328 clock-frequency = <100000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c3>;
331 status = "okay";
332
333 egalax_ts@04 {
334 compatible = "eeti,egalax_ts";
335 reg = <0x04>;
336 interrupt-parent = <&gpio6>;
337 interrupts = <7 2>;
338 wakeup-gpios = <&gpio6 7 0>;
339 };
340};
341
342&iomuxc {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_hog>;
345
346 imx6qdl-sabresd {
347 pinctrl_hog: hoggrp {
348 fsl,pins = <
349 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
350 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
351 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
352 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
353 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
354 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
355 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
356 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
357 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
358 >;
359 };
360
361 pinctrl_audmux: audmuxgrp {
362 fsl,pins = <
363 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
364 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
365 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
366 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
367 >;
368 };
369
370 pinctrl_ecspi1: ecspi1grp {
371 fsl,pins = <
372 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
373 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
374 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
375 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
376 >;
377 };
378
379 pinctrl_enet: enetgrp {
380 fsl,pins = <
381 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
382 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
383 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
384 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
385 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
386 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
387 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
388 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
389 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
390 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
391 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
392 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
393 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
394 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
395 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
396 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
397 >;
398 };
399
400 pinctrl_gpio_keys: gpio_keysgrp {
401 fsl,pins = <
402 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
403 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
404 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
405 >;
406 };
407
408 pinctrl_i2c1: i2c1grp {
409 fsl,pins = <
410 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
411 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
412 >;
413 };
414
415 pinctrl_i2c2: i2c2grp {
416 fsl,pins = <
417 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
418 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
419 >;
420 };
421
422 pinctrl_i2c3: i2c3grp {
423 fsl,pins = <
424 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
425 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
426 >;
427 };
428
429 pinctrl_pcie: pciegrp {
430 fsl,pins = <
431 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
432 >;
433 };
434
435 pinctrl_pcie_reg: pciereggrp {
436 fsl,pins = <
437 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
438 >;
439 };
440
441 pinctrl_pwm1: pwm1grp {
442 fsl,pins = <
443 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
444 >;
445 };
446
447 pinctrl_uart1: uart1grp {
448 fsl,pins = <
449 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
450 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
451 >;
452 };
453
454 pinctrl_usbotg: usbotggrp {
455 fsl,pins = <
456 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
457 >;
458 };
459
460 pinctrl_usdhc2: usdhc2grp {
461 fsl,pins = <
462 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
463 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
464 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
465 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
466 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
467 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
468 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
469 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
470 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
471 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
472 >;
473 };
474
475 pinctrl_usdhc3: usdhc3grp {
476 fsl,pins = <
477 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
478 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
479 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
480 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
481 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
482 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
483 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
484 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
485 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
486 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
487 >;
488 };
489
490 pinctrl_usdhc4: usdhc4grp {
491 fsl,pins = <
492 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
493 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
494 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
495 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
496 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
497 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
498 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
499 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
500 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
501 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
502 >;
503 };
504
505 pinctrl_wdog: wdoggrp {
506 fsl,pins = <
507 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
508 >;
509 };
510 };
511
512 gpio_leds {
513 pinctrl_gpio_leds: gpioledsgrp {
514 fsl,pins = <
515 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
516 >;
517 };
518 };
519};
520
521&ldb {
522 status = "okay";
523
524 lvds-channel@1 {
525 fsl,data-mapping = "spwg";
526 fsl,data-width = <18>;
527 status = "okay";
528
529 port@4 {
530 reg = <4>;
531
532 lvds0_out: endpoint {
533 remote-endpoint = <&panel_in>;
534 };
535 };
536 };
537};
538
539&pcie {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_pcie>;
542 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
543 status = "okay";
544};
545
546&pwm1 {
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_pwm1>;
549 status = "okay";
550};
551
552&snvs_poweroff {
553 status = "okay";
554};
555
556&ssi2 {
557 status = "okay";
558};
559
560&uart1 {
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_uart1>;
563 status = "okay";
564};
565
566&usbh1 {
567 vbus-supply = <®_usb_h1_vbus>;
568 status = "okay";
569};
570
571&usbotg {
572 vbus-supply = <®_usb_otg_vbus>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_usbotg>;
575 disable-over-current;
576 status = "okay";
577};
578
579&usdhc2 {
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_usdhc2>;
582 bus-width = <8>;
583 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
584 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
585 status = "okay";
586};
587
588&usdhc3 {
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_usdhc3>;
591 bus-width = <8>;
592 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
593 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
594 status = "okay";
595};
596
597&usdhc4 {
598 pinctrl-names = "default";
599 pinctrl-0 = <&pinctrl_usdhc4>;
600 bus-width = <8>;
601 non-removable;
602 no-1-8-v;
603 status = "okay";
604};
605
606&wdog1 {
607 status = "disabled";
608};
609
610&wdog2 {
611 pinctrl-names = "default";
612 pinctrl-0 = <&pinctrl_wdog>;
613 fsl,ext-reset-output;
614 status = "okay";
615};