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1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include "imx28-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 interrupt-parent = <&icoll>;
20 /*
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
25 */
26 chosen {};
27 memory { device_type = "memory"; };
28
29 aliases {
30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
32 gpio0 = &gpio0;
33 gpio1 = &gpio1;
34 gpio2 = &gpio2;
35 gpio3 = &gpio3;
36 gpio4 = &gpio4;
37 saif0 = &saif0;
38 saif1 = &saif1;
39 serial0 = &auart0;
40 serial1 = &auart1;
41 serial2 = &auart2;
42 serial3 = &auart3;
43 serial4 = &auart4;
44 spi0 = &ssp1;
45 spi1 = &ssp2;
46 usbphy0 = &usbphy0;
47 usbphy1 = &usbphy1;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu@0 {
55 compatible = "arm,arm926ej-s";
56 device_type = "cpu";
57 reg = <0>;
58 };
59 };
60
61 apb@80000000 {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x80000000 0x80000>;
66 ranges;
67
68 apbh@80000000 {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x80000000 0x3c900>;
73 ranges;
74
75 icoll: interrupt-controller@80000000 {
76 compatible = "fsl,imx28-icoll", "fsl,icoll";
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x80000000 0x2000>;
80 };
81
82 hsadc: hsadc@80002000 {
83 reg = <0x80002000 0x2000>;
84 interrupts = <13>;
85 dmas = <&dma_apbh 12>;
86 dma-names = "rx";
87 status = "disabled";
88 };
89
90 dma_apbh: dma-apbh@80004000 {
91 compatible = "fsl,imx28-dma-apbh";
92 reg = <0x80004000 0x2000>;
93 interrupts = <82 83 84 85
94 88 88 88 88
95 88 88 88 88
96 87 86 0 0>;
97 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
98 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
99 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
100 "hsadc", "lcdif", "empty", "empty";
101 #dma-cells = <1>;
102 dma-channels = <16>;
103 clocks = <&clks 25>;
104 };
105
106 perfmon: perfmon@80006000 {
107 reg = <0x80006000 0x800>;
108 interrupts = <27>;
109 status = "disabled";
110 };
111
112 gpmi: gpmi-nand@8000c000 {
113 compatible = "fsl,imx28-gpmi-nand";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
117 reg-names = "gpmi-nand", "bch";
118 interrupts = <41>;
119 interrupt-names = "bch";
120 clocks = <&clks 50>;
121 clock-names = "gpmi_io";
122 dmas = <&dma_apbh 4>;
123 dma-names = "rx-tx";
124 status = "disabled";
125 };
126
127 ssp0: ssp@80010000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <0x80010000 0x2000>;
131 interrupts = <96>;
132 clocks = <&clks 46>;
133 dmas = <&dma_apbh 0>;
134 dma-names = "rx-tx";
135 status = "disabled";
136 };
137
138 ssp1: ssp@80012000 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 reg = <0x80012000 0x2000>;
142 interrupts = <97>;
143 clocks = <&clks 47>;
144 dmas = <&dma_apbh 1>;
145 dma-names = "rx-tx";
146 status = "disabled";
147 };
148
149 ssp2: ssp@80014000 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0x80014000 0x2000>;
153 interrupts = <98>;
154 clocks = <&clks 48>;
155 dmas = <&dma_apbh 2>;
156 dma-names = "rx-tx";
157 status = "disabled";
158 };
159
160 ssp3: ssp@80016000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 reg = <0x80016000 0x2000>;
164 interrupts = <99>;
165 clocks = <&clks 49>;
166 dmas = <&dma_apbh 3>;
167 dma-names = "rx-tx";
168 status = "disabled";
169 };
170
171 pinctrl: pinctrl@80018000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx28-pinctrl", "simple-bus";
175 reg = <0x80018000 0x2000>;
176
177 gpio0: gpio@0 {
178 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
179 reg = <0>;
180 interrupts = <127>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186
187 gpio1: gpio@1 {
188 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
189 reg = <1>;
190 interrupts = <126>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio2: gpio@2 {
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
199 reg = <2>;
200 interrupts = <125>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
207 gpio3: gpio@3 {
208 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
209 reg = <3>;
210 interrupts = <124>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 };
216
217 gpio4: gpio@4 {
218 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
219 reg = <4>;
220 interrupts = <123>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
227 duart_pins_a: duart@0 {
228 reg = <0>;
229 fsl,pinmux-ids = <
230 MX28_PAD_PWM0__DUART_RX
231 MX28_PAD_PWM1__DUART_TX
232 >;
233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
236 };
237
238 duart_pins_b: duart@1 {
239 reg = <1>;
240 fsl,pinmux-ids = <
241 MX28_PAD_AUART0_CTS__DUART_RX
242 MX28_PAD_AUART0_RTS__DUART_TX
243 >;
244 fsl,drive-strength = <MXS_DRIVE_4mA>;
245 fsl,voltage = <MXS_VOLTAGE_HIGH>;
246 fsl,pull-up = <MXS_PULL_DISABLE>;
247 };
248
249 duart_4pins_a: duart-4pins@0 {
250 reg = <0>;
251 fsl,pinmux-ids = <
252 MX28_PAD_AUART0_CTS__DUART_RX
253 MX28_PAD_AUART0_RTS__DUART_TX
254 MX28_PAD_AUART0_RX__DUART_CTS
255 MX28_PAD_AUART0_TX__DUART_RTS
256 >;
257 fsl,drive-strength = <MXS_DRIVE_4mA>;
258 fsl,voltage = <MXS_VOLTAGE_HIGH>;
259 fsl,pull-up = <MXS_PULL_DISABLE>;
260 };
261
262 gpmi_pins_a: gpmi-nand@0 {
263 reg = <0>;
264 fsl,pinmux-ids = <
265 MX28_PAD_GPMI_D00__GPMI_D0
266 MX28_PAD_GPMI_D01__GPMI_D1
267 MX28_PAD_GPMI_D02__GPMI_D2
268 MX28_PAD_GPMI_D03__GPMI_D3
269 MX28_PAD_GPMI_D04__GPMI_D4
270 MX28_PAD_GPMI_D05__GPMI_D5
271 MX28_PAD_GPMI_D06__GPMI_D6
272 MX28_PAD_GPMI_D07__GPMI_D7
273 MX28_PAD_GPMI_CE0N__GPMI_CE0N
274 MX28_PAD_GPMI_RDY0__GPMI_READY0
275 MX28_PAD_GPMI_RDN__GPMI_RDN
276 MX28_PAD_GPMI_WRN__GPMI_WRN
277 MX28_PAD_GPMI_ALE__GPMI_ALE
278 MX28_PAD_GPMI_CLE__GPMI_CLE
279 MX28_PAD_GPMI_RESETN__GPMI_RESETN
280 >;
281 fsl,drive-strength = <MXS_DRIVE_4mA>;
282 fsl,voltage = <MXS_VOLTAGE_HIGH>;
283 fsl,pull-up = <MXS_PULL_DISABLE>;
284 };
285
286 gpmi_status_cfg: gpmi-status-cfg@0 {
287 reg = <0>;
288 fsl,pinmux-ids = <
289 MX28_PAD_GPMI_RDN__GPMI_RDN
290 MX28_PAD_GPMI_WRN__GPMI_WRN
291 MX28_PAD_GPMI_RESETN__GPMI_RESETN
292 >;
293 fsl,drive-strength = <MXS_DRIVE_12mA>;
294 };
295
296 auart0_pins_a: auart0@0 {
297 reg = <0>;
298 fsl,pinmux-ids = <
299 MX28_PAD_AUART0_RX__AUART0_RX
300 MX28_PAD_AUART0_TX__AUART0_TX
301 MX28_PAD_AUART0_CTS__AUART0_CTS
302 MX28_PAD_AUART0_RTS__AUART0_RTS
303 >;
304 fsl,drive-strength = <MXS_DRIVE_4mA>;
305 fsl,voltage = <MXS_VOLTAGE_HIGH>;
306 fsl,pull-up = <MXS_PULL_DISABLE>;
307 };
308
309 auart0_2pins_a: auart0-2pins@0 {
310 reg = <0>;
311 fsl,pinmux-ids = <
312 MX28_PAD_AUART0_RX__AUART0_RX
313 MX28_PAD_AUART0_TX__AUART0_TX
314 >;
315 fsl,drive-strength = <MXS_DRIVE_4mA>;
316 fsl,voltage = <MXS_VOLTAGE_HIGH>;
317 fsl,pull-up = <MXS_PULL_DISABLE>;
318 };
319
320 auart1_pins_a: auart1@0 {
321 reg = <0>;
322 fsl,pinmux-ids = <
323 MX28_PAD_AUART1_RX__AUART1_RX
324 MX28_PAD_AUART1_TX__AUART1_TX
325 MX28_PAD_AUART1_CTS__AUART1_CTS
326 MX28_PAD_AUART1_RTS__AUART1_RTS
327 >;
328 fsl,drive-strength = <MXS_DRIVE_4mA>;
329 fsl,voltage = <MXS_VOLTAGE_HIGH>;
330 fsl,pull-up = <MXS_PULL_DISABLE>;
331 };
332
333 auart1_2pins_a: auart1-2pins@0 {
334 reg = <0>;
335 fsl,pinmux-ids = <
336 MX28_PAD_AUART1_RX__AUART1_RX
337 MX28_PAD_AUART1_TX__AUART1_TX
338 >;
339 fsl,drive-strength = <MXS_DRIVE_4mA>;
340 fsl,voltage = <MXS_VOLTAGE_HIGH>;
341 fsl,pull-up = <MXS_PULL_DISABLE>;
342 };
343
344 auart2_2pins_a: auart2-2pins@0 {
345 reg = <0>;
346 fsl,pinmux-ids = <
347 MX28_PAD_SSP2_SCK__AUART2_RX
348 MX28_PAD_SSP2_MOSI__AUART2_TX
349 >;
350 fsl,drive-strength = <MXS_DRIVE_4mA>;
351 fsl,voltage = <MXS_VOLTAGE_HIGH>;
352 fsl,pull-up = <MXS_PULL_DISABLE>;
353 };
354
355 auart2_2pins_b: auart2-2pins@1 {
356 reg = <1>;
357 fsl,pinmux-ids = <
358 MX28_PAD_AUART2_RX__AUART2_RX
359 MX28_PAD_AUART2_TX__AUART2_TX
360 >;
361 fsl,drive-strength = <MXS_DRIVE_4mA>;
362 fsl,voltage = <MXS_VOLTAGE_HIGH>;
363 fsl,pull-up = <MXS_PULL_DISABLE>;
364 };
365
366 auart2_pins_a: auart2-pins@0 {
367 reg = <0>;
368 fsl,pinmux-ids = <
369 MX28_PAD_AUART2_RX__AUART2_RX
370 MX28_PAD_AUART2_TX__AUART2_TX
371 MX28_PAD_AUART2_CTS__AUART2_CTS
372 MX28_PAD_AUART2_RTS__AUART2_RTS
373 >;
374 fsl,drive-strength = <MXS_DRIVE_4mA>;
375 fsl,voltage = <MXS_VOLTAGE_HIGH>;
376 fsl,pull-up = <MXS_PULL_DISABLE>;
377 };
378
379 auart3_pins_a: auart3@0 {
380 reg = <0>;
381 fsl,pinmux-ids = <
382 MX28_PAD_AUART3_RX__AUART3_RX
383 MX28_PAD_AUART3_TX__AUART3_TX
384 MX28_PAD_AUART3_CTS__AUART3_CTS
385 MX28_PAD_AUART3_RTS__AUART3_RTS
386 >;
387 fsl,drive-strength = <MXS_DRIVE_4mA>;
388 fsl,voltage = <MXS_VOLTAGE_HIGH>;
389 fsl,pull-up = <MXS_PULL_DISABLE>;
390 };
391
392 auart3_2pins_a: auart3-2pins@0 {
393 reg = <0>;
394 fsl,pinmux-ids = <
395 MX28_PAD_SSP2_MISO__AUART3_RX
396 MX28_PAD_SSP2_SS0__AUART3_TX
397 >;
398 fsl,drive-strength = <MXS_DRIVE_4mA>;
399 fsl,voltage = <MXS_VOLTAGE_HIGH>;
400 fsl,pull-up = <MXS_PULL_DISABLE>;
401 };
402
403 auart3_2pins_b: auart3-2pins@1 {
404 reg = <1>;
405 fsl,pinmux-ids = <
406 MX28_PAD_AUART3_RX__AUART3_RX
407 MX28_PAD_AUART3_TX__AUART3_TX
408 >;
409 fsl,drive-strength = <MXS_DRIVE_4mA>;
410 fsl,voltage = <MXS_VOLTAGE_HIGH>;
411 fsl,pull-up = <MXS_PULL_DISABLE>;
412 };
413
414 auart4_2pins_a: auart4@0 {
415 reg = <0>;
416 fsl,pinmux-ids = <
417 MX28_PAD_SSP3_SCK__AUART4_TX
418 MX28_PAD_SSP3_MOSI__AUART4_RX
419 >;
420 fsl,drive-strength = <MXS_DRIVE_4mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_DISABLE>;
423 };
424
425 auart4_2pins_b: auart4@1 {
426 reg = <1>;
427 fsl,pinmux-ids = <
428 MX28_PAD_AUART0_CTS__AUART4_RX
429 MX28_PAD_AUART0_RTS__AUART4_TX
430 >;
431 fsl,drive-strength = <MXS_DRIVE_4mA>;
432 fsl,voltage = <MXS_VOLTAGE_HIGH>;
433 fsl,pull-up = <MXS_PULL_DISABLE>;
434 };
435
436 mac0_pins_a: mac0@0 {
437 reg = <0>;
438 fsl,pinmux-ids = <
439 MX28_PAD_ENET0_MDC__ENET0_MDC
440 MX28_PAD_ENET0_MDIO__ENET0_MDIO
441 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
442 MX28_PAD_ENET0_RXD0__ENET0_RXD0
443 MX28_PAD_ENET0_RXD1__ENET0_RXD1
444 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
445 MX28_PAD_ENET0_TXD0__ENET0_TXD0
446 MX28_PAD_ENET0_TXD1__ENET0_TXD1
447 MX28_PAD_ENET_CLK__CLKCTRL_ENET
448 >;
449 fsl,drive-strength = <MXS_DRIVE_8mA>;
450 fsl,voltage = <MXS_VOLTAGE_HIGH>;
451 fsl,pull-up = <MXS_PULL_ENABLE>;
452 };
453
454 mac0_pins_b: mac0@1 {
455 reg = <1>;
456 fsl,pinmux-ids = <
457 MX28_PAD_ENET0_MDC__ENET0_MDC
458 MX28_PAD_ENET0_MDIO__ENET0_MDIO
459 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
460 MX28_PAD_ENET0_RXD0__ENET0_RXD0
461 MX28_PAD_ENET0_RXD1__ENET0_RXD1
462 MX28_PAD_ENET0_RXD2__ENET0_RXD2
463 MX28_PAD_ENET0_RXD3__ENET0_RXD3
464 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
465 MX28_PAD_ENET0_TXD0__ENET0_TXD0
466 MX28_PAD_ENET0_TXD1__ENET0_TXD1
467 MX28_PAD_ENET0_TXD2__ENET0_TXD2
468 MX28_PAD_ENET0_TXD3__ENET0_TXD3
469 MX28_PAD_ENET_CLK__CLKCTRL_ENET
470 MX28_PAD_ENET0_COL__ENET0_COL
471 MX28_PAD_ENET0_CRS__ENET0_CRS
472 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
473 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
474 >;
475 fsl,drive-strength = <MXS_DRIVE_8mA>;
476 fsl,voltage = <MXS_VOLTAGE_HIGH>;
477 fsl,pull-up = <MXS_PULL_ENABLE>;
478 };
479
480 mac1_pins_a: mac1@0 {
481 reg = <0>;
482 fsl,pinmux-ids = <
483 MX28_PAD_ENET0_CRS__ENET1_RX_EN
484 MX28_PAD_ENET0_RXD2__ENET1_RXD0
485 MX28_PAD_ENET0_RXD3__ENET1_RXD1
486 MX28_PAD_ENET0_COL__ENET1_TX_EN
487 MX28_PAD_ENET0_TXD2__ENET1_TXD0
488 MX28_PAD_ENET0_TXD3__ENET1_TXD1
489 >;
490 fsl,drive-strength = <MXS_DRIVE_8mA>;
491 fsl,voltage = <MXS_VOLTAGE_HIGH>;
492 fsl,pull-up = <MXS_PULL_ENABLE>;
493 };
494
495 mmc0_8bit_pins_a: mmc0-8bit@0 {
496 reg = <0>;
497 fsl,pinmux-ids = <
498 MX28_PAD_SSP0_DATA0__SSP0_D0
499 MX28_PAD_SSP0_DATA1__SSP0_D1
500 MX28_PAD_SSP0_DATA2__SSP0_D2
501 MX28_PAD_SSP0_DATA3__SSP0_D3
502 MX28_PAD_SSP0_DATA4__SSP0_D4
503 MX28_PAD_SSP0_DATA5__SSP0_D5
504 MX28_PAD_SSP0_DATA6__SSP0_D6
505 MX28_PAD_SSP0_DATA7__SSP0_D7
506 MX28_PAD_SSP0_CMD__SSP0_CMD
507 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
508 MX28_PAD_SSP0_SCK__SSP0_SCK
509 >;
510 fsl,drive-strength = <MXS_DRIVE_8mA>;
511 fsl,voltage = <MXS_VOLTAGE_HIGH>;
512 fsl,pull-up = <MXS_PULL_ENABLE>;
513 };
514
515 mmc0_4bit_pins_a: mmc0-4bit@0 {
516 reg = <0>;
517 fsl,pinmux-ids = <
518 MX28_PAD_SSP0_DATA0__SSP0_D0
519 MX28_PAD_SSP0_DATA1__SSP0_D1
520 MX28_PAD_SSP0_DATA2__SSP0_D2
521 MX28_PAD_SSP0_DATA3__SSP0_D3
522 MX28_PAD_SSP0_CMD__SSP0_CMD
523 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
524 MX28_PAD_SSP0_SCK__SSP0_SCK
525 >;
526 fsl,drive-strength = <MXS_DRIVE_8mA>;
527 fsl,voltage = <MXS_VOLTAGE_HIGH>;
528 fsl,pull-up = <MXS_PULL_ENABLE>;
529 };
530
531 mmc0_cd_cfg: mmc0-cd-cfg@0 {
532 reg = <0>;
533 fsl,pinmux-ids = <
534 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
535 >;
536 fsl,pull-up = <MXS_PULL_DISABLE>;
537 };
538
539 mmc0_sck_cfg: mmc0-sck-cfg@0 {
540 reg = <0>;
541 fsl,pinmux-ids = <
542 MX28_PAD_SSP0_SCK__SSP0_SCK
543 >;
544 fsl,drive-strength = <MXS_DRIVE_12mA>;
545 fsl,pull-up = <MXS_PULL_DISABLE>;
546 };
547
548 mmc1_4bit_pins_a: mmc1-4bit@0 {
549 reg = <0>;
550 fsl,pinmux-ids = <
551 MX28_PAD_GPMI_D00__SSP1_D0
552 MX28_PAD_GPMI_D01__SSP1_D1
553 MX28_PAD_GPMI_D02__SSP1_D2
554 MX28_PAD_GPMI_D03__SSP1_D3
555 MX28_PAD_GPMI_RDY1__SSP1_CMD
556 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
557 MX28_PAD_GPMI_WRN__SSP1_SCK
558 >;
559 fsl,drive-strength = <MXS_DRIVE_8mA>;
560 fsl,voltage = <MXS_VOLTAGE_HIGH>;
561 fsl,pull-up = <MXS_PULL_ENABLE>;
562 };
563
564 mmc1_cd_cfg: mmc1-cd-cfg@0 {
565 reg = <0>;
566 fsl,pinmux-ids = <
567 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
568 >;
569 fsl,pull-up = <MXS_PULL_DISABLE>;
570 };
571
572 mmc1_sck_cfg: mmc1-sck-cfg@0 {
573 reg = <0>;
574 fsl,pinmux-ids = <
575 MX28_PAD_GPMI_WRN__SSP1_SCK
576 >;
577 fsl,drive-strength = <MXS_DRIVE_12mA>;
578 fsl,pull-up = <MXS_PULL_DISABLE>;
579 };
580
581
582 mmc2_4bit_pins_a: mmc2-4bit@0 {
583 reg = <0>;
584 fsl,pinmux-ids = <
585 MX28_PAD_SSP0_DATA4__SSP2_D0
586 MX28_PAD_SSP1_SCK__SSP2_D1
587 MX28_PAD_SSP1_CMD__SSP2_D2
588 MX28_PAD_SSP0_DATA5__SSP2_D3
589 MX28_PAD_SSP0_DATA6__SSP2_CMD
590 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
591 MX28_PAD_SSP0_DATA7__SSP2_SCK
592 >;
593 fsl,drive-strength = <MXS_DRIVE_8mA>;
594 fsl,voltage = <MXS_VOLTAGE_HIGH>;
595 fsl,pull-up = <MXS_PULL_ENABLE>;
596 };
597
598 mmc2_4bit_pins_b: mmc2-4bit@1 {
599 reg = <1>;
600 fsl,pinmux-ids = <
601 MX28_PAD_SSP2_SCK__SSP2_SCK
602 MX28_PAD_SSP2_MOSI__SSP2_CMD
603 MX28_PAD_SSP2_MISO__SSP2_D0
604 MX28_PAD_SSP2_SS0__SSP2_D3
605 MX28_PAD_SSP2_SS1__SSP2_D1
606 MX28_PAD_SSP2_SS2__SSP2_D2
607 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
608 >;
609 fsl,drive-strength = <MXS_DRIVE_8mA>;
610 fsl,voltage = <MXS_VOLTAGE_HIGH>;
611 fsl,pull-up = <MXS_PULL_ENABLE>;
612 };
613
614 mmc2_cd_cfg: mmc2-cd-cfg@0 {
615 reg = <0>;
616 fsl,pinmux-ids = <
617 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
618 >;
619 fsl,pull-up = <MXS_PULL_DISABLE>;
620 };
621
622 mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
623 reg = <0>;
624 fsl,pinmux-ids = <
625 MX28_PAD_SSP0_DATA7__SSP2_SCK
626 >;
627 fsl,drive-strength = <MXS_DRIVE_12mA>;
628 fsl,pull-up = <MXS_PULL_DISABLE>;
629 };
630
631 mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
632 reg = <1>;
633 fsl,pinmux-ids = <
634 MX28_PAD_SSP2_SCK__SSP2_SCK
635 >;
636 fsl,drive-strength = <MXS_DRIVE_12mA>;
637 fsl,pull-up = <MXS_PULL_DISABLE>;
638 };
639
640 i2c0_pins_a: i2c0@0 {
641 reg = <0>;
642 fsl,pinmux-ids = <
643 MX28_PAD_I2C0_SCL__I2C0_SCL
644 MX28_PAD_I2C0_SDA__I2C0_SDA
645 >;
646 fsl,drive-strength = <MXS_DRIVE_8mA>;
647 fsl,voltage = <MXS_VOLTAGE_HIGH>;
648 fsl,pull-up = <MXS_PULL_ENABLE>;
649 };
650
651 i2c0_pins_b: i2c0@1 {
652 reg = <1>;
653 fsl,pinmux-ids = <
654 MX28_PAD_AUART0_RX__I2C0_SCL
655 MX28_PAD_AUART0_TX__I2C0_SDA
656 >;
657 fsl,drive-strength = <MXS_DRIVE_8mA>;
658 fsl,voltage = <MXS_VOLTAGE_HIGH>;
659 fsl,pull-up = <MXS_PULL_ENABLE>;
660 };
661
662 i2c1_pins_a: i2c1@0 {
663 reg = <0>;
664 fsl,pinmux-ids = <
665 MX28_PAD_PWM0__I2C1_SCL
666 MX28_PAD_PWM1__I2C1_SDA
667 >;
668 fsl,drive-strength = <MXS_DRIVE_8mA>;
669 fsl,voltage = <MXS_VOLTAGE_HIGH>;
670 fsl,pull-up = <MXS_PULL_ENABLE>;
671 };
672
673 i2c1_pins_b: i2c1@1 {
674 reg = <1>;
675 fsl,pinmux-ids = <
676 MX28_PAD_AUART2_CTS__I2C1_SCL
677 MX28_PAD_AUART2_RTS__I2C1_SDA
678 >;
679 fsl,drive-strength = <MXS_DRIVE_8mA>;
680 fsl,voltage = <MXS_VOLTAGE_HIGH>;
681 fsl,pull-up = <MXS_PULL_ENABLE>;
682 };
683
684 saif0_pins_a: saif0@0 {
685 reg = <0>;
686 fsl,pinmux-ids = <
687 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
688 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
689 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
690 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
691 >;
692 fsl,drive-strength = <MXS_DRIVE_12mA>;
693 fsl,voltage = <MXS_VOLTAGE_HIGH>;
694 fsl,pull-up = <MXS_PULL_ENABLE>;
695 };
696
697 saif0_pins_b: saif0@1 {
698 reg = <1>;
699 fsl,pinmux-ids = <
700 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
701 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
702 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
703 >;
704 fsl,drive-strength = <MXS_DRIVE_12mA>;
705 fsl,voltage = <MXS_VOLTAGE_HIGH>;
706 fsl,pull-up = <MXS_PULL_ENABLE>;
707 };
708
709 saif1_pins_a: saif1@0 {
710 reg = <0>;
711 fsl,pinmux-ids = <
712 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
713 >;
714 fsl,drive-strength = <MXS_DRIVE_12mA>;
715 fsl,voltage = <MXS_VOLTAGE_HIGH>;
716 fsl,pull-up = <MXS_PULL_ENABLE>;
717 };
718
719 pwm0_pins_a: pwm0@0 {
720 reg = <0>;
721 fsl,pinmux-ids = <
722 MX28_PAD_PWM0__PWM_0
723 >;
724 fsl,drive-strength = <MXS_DRIVE_4mA>;
725 fsl,voltage = <MXS_VOLTAGE_HIGH>;
726 fsl,pull-up = <MXS_PULL_DISABLE>;
727 };
728
729 pwm2_pins_a: pwm2@0 {
730 reg = <0>;
731 fsl,pinmux-ids = <
732 MX28_PAD_PWM2__PWM_2
733 >;
734 fsl,drive-strength = <MXS_DRIVE_4mA>;
735 fsl,voltage = <MXS_VOLTAGE_HIGH>;
736 fsl,pull-up = <MXS_PULL_DISABLE>;
737 };
738
739 pwm3_pins_a: pwm3@0 {
740 reg = <0>;
741 fsl,pinmux-ids = <
742 MX28_PAD_PWM3__PWM_3
743 >;
744 fsl,drive-strength = <MXS_DRIVE_4mA>;
745 fsl,voltage = <MXS_VOLTAGE_HIGH>;
746 fsl,pull-up = <MXS_PULL_DISABLE>;
747 };
748
749 pwm3_pins_b: pwm3@1 {
750 reg = <1>;
751 fsl,pinmux-ids = <
752 MX28_PAD_SAIF0_MCLK__PWM_3
753 >;
754 fsl,drive-strength = <MXS_DRIVE_4mA>;
755 fsl,voltage = <MXS_VOLTAGE_HIGH>;
756 fsl,pull-up = <MXS_PULL_DISABLE>;
757 };
758
759 pwm4_pins_a: pwm4@0 {
760 reg = <0>;
761 fsl,pinmux-ids = <
762 MX28_PAD_PWM4__PWM_4
763 >;
764 fsl,drive-strength = <MXS_DRIVE_4mA>;
765 fsl,voltage = <MXS_VOLTAGE_HIGH>;
766 fsl,pull-up = <MXS_PULL_DISABLE>;
767 };
768
769 lcdif_24bit_pins_a: lcdif-24bit@0 {
770 reg = <0>;
771 fsl,pinmux-ids = <
772 MX28_PAD_LCD_D00__LCD_D0
773 MX28_PAD_LCD_D01__LCD_D1
774 MX28_PAD_LCD_D02__LCD_D2
775 MX28_PAD_LCD_D03__LCD_D3
776 MX28_PAD_LCD_D04__LCD_D4
777 MX28_PAD_LCD_D05__LCD_D5
778 MX28_PAD_LCD_D06__LCD_D6
779 MX28_PAD_LCD_D07__LCD_D7
780 MX28_PAD_LCD_D08__LCD_D8
781 MX28_PAD_LCD_D09__LCD_D9
782 MX28_PAD_LCD_D10__LCD_D10
783 MX28_PAD_LCD_D11__LCD_D11
784 MX28_PAD_LCD_D12__LCD_D12
785 MX28_PAD_LCD_D13__LCD_D13
786 MX28_PAD_LCD_D14__LCD_D14
787 MX28_PAD_LCD_D15__LCD_D15
788 MX28_PAD_LCD_D16__LCD_D16
789 MX28_PAD_LCD_D17__LCD_D17
790 MX28_PAD_LCD_D18__LCD_D18
791 MX28_PAD_LCD_D19__LCD_D19
792 MX28_PAD_LCD_D20__LCD_D20
793 MX28_PAD_LCD_D21__LCD_D21
794 MX28_PAD_LCD_D22__LCD_D22
795 MX28_PAD_LCD_D23__LCD_D23
796 >;
797 fsl,drive-strength = <MXS_DRIVE_4mA>;
798 fsl,voltage = <MXS_VOLTAGE_HIGH>;
799 fsl,pull-up = <MXS_PULL_DISABLE>;
800 };
801
802 lcdif_18bit_pins_a: lcdif-18bit@0 {
803 reg = <0>;
804 fsl,pinmux-ids = <
805 MX28_PAD_LCD_D00__LCD_D0
806 MX28_PAD_LCD_D01__LCD_D1
807 MX28_PAD_LCD_D02__LCD_D2
808 MX28_PAD_LCD_D03__LCD_D3
809 MX28_PAD_LCD_D04__LCD_D4
810 MX28_PAD_LCD_D05__LCD_D5
811 MX28_PAD_LCD_D06__LCD_D6
812 MX28_PAD_LCD_D07__LCD_D7
813 MX28_PAD_LCD_D08__LCD_D8
814 MX28_PAD_LCD_D09__LCD_D9
815 MX28_PAD_LCD_D10__LCD_D10
816 MX28_PAD_LCD_D11__LCD_D11
817 MX28_PAD_LCD_D12__LCD_D12
818 MX28_PAD_LCD_D13__LCD_D13
819 MX28_PAD_LCD_D14__LCD_D14
820 MX28_PAD_LCD_D15__LCD_D15
821 MX28_PAD_LCD_D16__LCD_D16
822 MX28_PAD_LCD_D17__LCD_D17
823 >;
824 fsl,drive-strength = <MXS_DRIVE_4mA>;
825 fsl,voltage = <MXS_VOLTAGE_HIGH>;
826 fsl,pull-up = <MXS_PULL_DISABLE>;
827 };
828
829 lcdif_16bit_pins_a: lcdif-16bit@0 {
830 reg = <0>;
831 fsl,pinmux-ids = <
832 MX28_PAD_LCD_D00__LCD_D0
833 MX28_PAD_LCD_D01__LCD_D1
834 MX28_PAD_LCD_D02__LCD_D2
835 MX28_PAD_LCD_D03__LCD_D3
836 MX28_PAD_LCD_D04__LCD_D4
837 MX28_PAD_LCD_D05__LCD_D5
838 MX28_PAD_LCD_D06__LCD_D6
839 MX28_PAD_LCD_D07__LCD_D7
840 MX28_PAD_LCD_D08__LCD_D8
841 MX28_PAD_LCD_D09__LCD_D9
842 MX28_PAD_LCD_D10__LCD_D10
843 MX28_PAD_LCD_D11__LCD_D11
844 MX28_PAD_LCD_D12__LCD_D12
845 MX28_PAD_LCD_D13__LCD_D13
846 MX28_PAD_LCD_D14__LCD_D14
847 MX28_PAD_LCD_D15__LCD_D15
848 >;
849 fsl,drive-strength = <MXS_DRIVE_4mA>;
850 fsl,voltage = <MXS_VOLTAGE_HIGH>;
851 fsl,pull-up = <MXS_PULL_DISABLE>;
852 };
853
854 lcdif_sync_pins_a: lcdif-sync@0 {
855 reg = <0>;
856 fsl,pinmux-ids = <
857 MX28_PAD_LCD_RS__LCD_DOTCLK
858 MX28_PAD_LCD_CS__LCD_ENABLE
859 MX28_PAD_LCD_RD_E__LCD_VSYNC
860 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
861 >;
862 fsl,drive-strength = <MXS_DRIVE_4mA>;
863 fsl,voltage = <MXS_VOLTAGE_HIGH>;
864 fsl,pull-up = <MXS_PULL_DISABLE>;
865 };
866
867 can0_pins_a: can0@0 {
868 reg = <0>;
869 fsl,pinmux-ids = <
870 MX28_PAD_GPMI_RDY2__CAN0_TX
871 MX28_PAD_GPMI_RDY3__CAN0_RX
872 >;
873 fsl,drive-strength = <MXS_DRIVE_4mA>;
874 fsl,voltage = <MXS_VOLTAGE_HIGH>;
875 fsl,pull-up = <MXS_PULL_DISABLE>;
876 };
877
878 can1_pins_a: can1@0 {
879 reg = <0>;
880 fsl,pinmux-ids = <
881 MX28_PAD_GPMI_CE2N__CAN1_TX
882 MX28_PAD_GPMI_CE3N__CAN1_RX
883 >;
884 fsl,drive-strength = <MXS_DRIVE_4mA>;
885 fsl,voltage = <MXS_VOLTAGE_HIGH>;
886 fsl,pull-up = <MXS_PULL_DISABLE>;
887 };
888
889 spi2_pins_a: spi2@0 {
890 reg = <0>;
891 fsl,pinmux-ids = <
892 MX28_PAD_SSP2_SCK__SSP2_SCK
893 MX28_PAD_SSP2_MOSI__SSP2_CMD
894 MX28_PAD_SSP2_MISO__SSP2_D0
895 MX28_PAD_SSP2_SS0__SSP2_D3
896 >;
897 fsl,drive-strength = <MXS_DRIVE_8mA>;
898 fsl,voltage = <MXS_VOLTAGE_HIGH>;
899 fsl,pull-up = <MXS_PULL_ENABLE>;
900 };
901
902 spi3_pins_a: spi3@0 {
903 reg = <0>;
904 fsl,pinmux-ids = <
905 MX28_PAD_AUART2_RX__SSP3_D4
906 MX28_PAD_AUART2_TX__SSP3_D5
907 MX28_PAD_SSP3_SCK__SSP3_SCK
908 MX28_PAD_SSP3_MOSI__SSP3_CMD
909 MX28_PAD_SSP3_MISO__SSP3_D0
910 MX28_PAD_SSP3_SS0__SSP3_D3
911 >;
912 fsl,drive-strength = <MXS_DRIVE_8mA>;
913 fsl,voltage = <MXS_VOLTAGE_HIGH>;
914 fsl,pull-up = <MXS_PULL_DISABLE>;
915 };
916
917 spi3_pins_b: spi3@1 {
918 reg = <1>;
919 fsl,pinmux-ids = <
920 MX28_PAD_SSP3_SCK__SSP3_SCK
921 MX28_PAD_SSP3_MOSI__SSP3_CMD
922 MX28_PAD_SSP3_MISO__SSP3_D0
923 MX28_PAD_SSP3_SS0__SSP3_D3
924 >;
925 fsl,drive-strength = <MXS_DRIVE_8mA>;
926 fsl,voltage = <MXS_VOLTAGE_HIGH>;
927 fsl,pull-up = <MXS_PULL_ENABLE>;
928 };
929
930 usb0_pins_a: usb0@0 {
931 reg = <0>;
932 fsl,pinmux-ids = <
933 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
934 >;
935 fsl,drive-strength = <MXS_DRIVE_12mA>;
936 fsl,voltage = <MXS_VOLTAGE_HIGH>;
937 fsl,pull-up = <MXS_PULL_DISABLE>;
938 };
939
940 usb0_pins_b: usb0@1 {
941 reg = <1>;
942 fsl,pinmux-ids = <
943 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
944 >;
945 fsl,drive-strength = <MXS_DRIVE_12mA>;
946 fsl,voltage = <MXS_VOLTAGE_HIGH>;
947 fsl,pull-up = <MXS_PULL_DISABLE>;
948 };
949
950 usb1_pins_a: usb1@0 {
951 reg = <0>;
952 fsl,pinmux-ids = <
953 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
954 >;
955 fsl,drive-strength = <MXS_DRIVE_12mA>;
956 fsl,voltage = <MXS_VOLTAGE_HIGH>;
957 fsl,pull-up = <MXS_PULL_DISABLE>;
958 };
959
960 usb0_id_pins_a: usb0id@0 {
961 reg = <0>;
962 fsl,pinmux-ids = <
963 MX28_PAD_AUART1_RTS__USB0_ID
964 >;
965 fsl,drive-strength = <MXS_DRIVE_12mA>;
966 fsl,voltage = <MXS_VOLTAGE_HIGH>;
967 fsl,pull-up = <MXS_PULL_ENABLE>;
968 };
969
970 usb0_id_pins_b: usb0id1@0 {
971 reg = <0>;
972 fsl,pinmux-ids = <
973 MX28_PAD_PWM2__USB0_ID
974 >;
975 fsl,drive-strength = <MXS_DRIVE_12mA>;
976 fsl,voltage = <MXS_VOLTAGE_HIGH>;
977 fsl,pull-up = <MXS_PULL_ENABLE>;
978 };
979
980 };
981
982 digctl: digctl@8001c000 {
983 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
984 reg = <0x8001c000 0x2000>;
985 interrupts = <89>;
986 status = "disabled";
987 };
988
989 etm: etm@80022000 {
990 reg = <0x80022000 0x2000>;
991 status = "disabled";
992 };
993
994 dma_apbx: dma-apbx@80024000 {
995 compatible = "fsl,imx28-dma-apbx";
996 reg = <0x80024000 0x2000>;
997 interrupts = <78 79 66 0
998 80 81 68 69
999 70 71 72 73
1000 74 75 76 77>;
1001 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
1002 "saif0", "saif1", "i2c0", "i2c1",
1003 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
1004 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
1005 #dma-cells = <1>;
1006 dma-channels = <16>;
1007 clocks = <&clks 26>;
1008 };
1009
1010 dcp: dcp@80028000 {
1011 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
1012 reg = <0x80028000 0x2000>;
1013 interrupts = <52 53 54>;
1014 status = "okay";
1015 };
1016
1017 pxp: pxp@8002a000 {
1018 reg = <0x8002a000 0x2000>;
1019 interrupts = <39>;
1020 status = "disabled";
1021 };
1022
1023 ocotp: ocotp@8002c000 {
1024 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1025 #address-cells = <1>;
1026 #size-cells = <1>;
1027 reg = <0x8002c000 0x2000>;
1028 clocks = <&clks 25>;
1029 };
1030
1031 axi-ahb@8002e000 {
1032 reg = <0x8002e000 0x2000>;
1033 status = "disabled";
1034 };
1035
1036 lcdif: lcdif@80030000 {
1037 compatible = "fsl,imx28-lcdif";
1038 reg = <0x80030000 0x2000>;
1039 interrupts = <38>;
1040 clocks = <&clks 55>;
1041 dmas = <&dma_apbh 13>;
1042 dma-names = "rx";
1043 status = "disabled";
1044 };
1045
1046 can0: can@80032000 {
1047 compatible = "fsl,imx28-flexcan";
1048 reg = <0x80032000 0x2000>;
1049 interrupts = <8>;
1050 clocks = <&clks 58>, <&clks 58>;
1051 clock-names = "ipg", "per";
1052 status = "disabled";
1053 };
1054
1055 can1: can@80034000 {
1056 compatible = "fsl,imx28-flexcan";
1057 reg = <0x80034000 0x2000>;
1058 interrupts = <9>;
1059 clocks = <&clks 59>, <&clks 59>;
1060 clock-names = "ipg", "per";
1061 status = "disabled";
1062 };
1063
1064 simdbg: simdbg@8003c000 {
1065 reg = <0x8003c000 0x200>;
1066 status = "disabled";
1067 };
1068
1069 simgpmisel: simgpmisel@8003c200 {
1070 reg = <0x8003c200 0x100>;
1071 status = "disabled";
1072 };
1073
1074 simsspsel: simsspsel@8003c300 {
1075 reg = <0x8003c300 0x100>;
1076 status = "disabled";
1077 };
1078
1079 simmemsel: simmemsel@8003c400 {
1080 reg = <0x8003c400 0x100>;
1081 status = "disabled";
1082 };
1083
1084 gpiomon: gpiomon@8003c500 {
1085 reg = <0x8003c500 0x100>;
1086 status = "disabled";
1087 };
1088
1089 simenet: simenet@8003c700 {
1090 reg = <0x8003c700 0x100>;
1091 status = "disabled";
1092 };
1093
1094 armjtag: armjtag@8003c800 {
1095 reg = <0x8003c800 0x100>;
1096 status = "disabled";
1097 };
1098 };
1099
1100 apbx@80040000 {
1101 compatible = "simple-bus";
1102 #address-cells = <1>;
1103 #size-cells = <1>;
1104 reg = <0x80040000 0x40000>;
1105 ranges;
1106
1107 clks: clkctrl@80040000 {
1108 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1109 reg = <0x80040000 0x2000>;
1110 #clock-cells = <1>;
1111 };
1112
1113 saif0: saif@80042000 {
1114 #sound-dai-cells = <0>;
1115 compatible = "fsl,imx28-saif";
1116 reg = <0x80042000 0x2000>;
1117 interrupts = <59>;
1118 #clock-cells = <0>;
1119 clocks = <&clks 53>;
1120 dmas = <&dma_apbx 4>;
1121 dma-names = "rx-tx";
1122 status = "disabled";
1123 };
1124
1125 power: power@80044000 {
1126 reg = <0x80044000 0x2000>;
1127 status = "disabled";
1128 };
1129
1130 saif1: saif@80046000 {
1131 #sound-dai-cells = <0>;
1132 compatible = "fsl,imx28-saif";
1133 reg = <0x80046000 0x2000>;
1134 interrupts = <58>;
1135 clocks = <&clks 54>;
1136 dmas = <&dma_apbx 5>;
1137 dma-names = "rx-tx";
1138 status = "disabled";
1139 };
1140
1141 lradc: lradc@80050000 {
1142 compatible = "fsl,imx28-lradc";
1143 reg = <0x80050000 0x2000>;
1144 interrupts = <10 14 15 16 17 18 19
1145 20 21 22 23 24 25>;
1146 status = "disabled";
1147 clocks = <&clks 41>;
1148 #io-channel-cells = <1>;
1149 };
1150
1151 spdif: spdif@80054000 {
1152 reg = <0x80054000 0x2000>;
1153 interrupts = <45>;
1154 dmas = <&dma_apbx 2>;
1155 dma-names = "tx";
1156 status = "disabled";
1157 };
1158
1159 mxs_rtc: rtc@80056000 {
1160 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1161 reg = <0x80056000 0x2000>;
1162 interrupts = <29>;
1163 };
1164
1165 i2c0: i2c@80058000 {
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 compatible = "fsl,imx28-i2c";
1169 reg = <0x80058000 0x2000>;
1170 interrupts = <111>;
1171 clock-frequency = <100000>;
1172 dmas = <&dma_apbx 6>;
1173 dma-names = "rx-tx";
1174 status = "disabled";
1175 };
1176
1177 i2c1: i2c@8005a000 {
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180 compatible = "fsl,imx28-i2c";
1181 reg = <0x8005a000 0x2000>;
1182 interrupts = <110>;
1183 clock-frequency = <100000>;
1184 dmas = <&dma_apbx 7>;
1185 dma-names = "rx-tx";
1186 status = "disabled";
1187 };
1188
1189 pwm: pwm@80064000 {
1190 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1191 reg = <0x80064000 0x2000>;
1192 clocks = <&clks 44>;
1193 #pwm-cells = <2>;
1194 fsl,pwm-number = <8>;
1195 status = "disabled";
1196 };
1197
1198 timer: timrot@80068000 {
1199 compatible = "fsl,imx28-timrot", "fsl,timrot";
1200 reg = <0x80068000 0x2000>;
1201 interrupts = <48 49 50 51>;
1202 clocks = <&clks 26>;
1203 };
1204
1205 auart0: serial@8006a000 {
1206 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1207 reg = <0x8006a000 0x2000>;
1208 interrupts = <112>;
1209 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1210 dma-names = "rx", "tx";
1211 clocks = <&clks 45>;
1212 status = "disabled";
1213 };
1214
1215 auart1: serial@8006c000 {
1216 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1217 reg = <0x8006c000 0x2000>;
1218 interrupts = <113>;
1219 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1220 dma-names = "rx", "tx";
1221 clocks = <&clks 45>;
1222 status = "disabled";
1223 };
1224
1225 auart2: serial@8006e000 {
1226 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1227 reg = <0x8006e000 0x2000>;
1228 interrupts = <114>;
1229 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1230 dma-names = "rx", "tx";
1231 clocks = <&clks 45>;
1232 status = "disabled";
1233 };
1234
1235 auart3: serial@80070000 {
1236 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1237 reg = <0x80070000 0x2000>;
1238 interrupts = <115>;
1239 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1240 dma-names = "rx", "tx";
1241 clocks = <&clks 45>;
1242 status = "disabled";
1243 };
1244
1245 auart4: serial@80072000 {
1246 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1247 reg = <0x80072000 0x2000>;
1248 interrupts = <116>;
1249 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1250 dma-names = "rx", "tx";
1251 clocks = <&clks 45>;
1252 status = "disabled";
1253 };
1254
1255 duart: serial@80074000 {
1256 compatible = "arm,pl011", "arm,primecell";
1257 reg = <0x80074000 0x1000>;
1258 interrupts = <47>;
1259 clocks = <&clks 45>, <&clks 26>;
1260 clock-names = "uart", "apb_pclk";
1261 status = "disabled";
1262 };
1263
1264 usbphy0: usbphy@8007c000 {
1265 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1266 reg = <0x8007c000 0x2000>;
1267 clocks = <&clks 62>;
1268 status = "disabled";
1269 };
1270
1271 usbphy1: usbphy@8007e000 {
1272 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1273 reg = <0x8007e000 0x2000>;
1274 clocks = <&clks 63>;
1275 status = "disabled";
1276 };
1277 };
1278 };
1279
1280 ahb@80080000 {
1281 compatible = "simple-bus";
1282 #address-cells = <1>;
1283 #size-cells = <1>;
1284 reg = <0x80080000 0x80000>;
1285 ranges;
1286
1287 usb0: usb@80080000 {
1288 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1289 reg = <0x80080000 0x10000>;
1290 interrupts = <93>;
1291 clocks = <&clks 60>;
1292 fsl,usbphy = <&usbphy0>;
1293 status = "disabled";
1294 };
1295
1296 usb1: usb@80090000 {
1297 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1298 reg = <0x80090000 0x10000>;
1299 interrupts = <92>;
1300 clocks = <&clks 61>;
1301 fsl,usbphy = <&usbphy1>;
1302 dr_mode = "host";
1303 status = "disabled";
1304 };
1305
1306 dflpt: dflpt@800c0000 {
1307 reg = <0x800c0000 0x10000>;
1308 status = "disabled";
1309 };
1310
1311 mac0: ethernet@800f0000 {
1312 compatible = "fsl,imx28-fec";
1313 reg = <0x800f0000 0x4000>;
1314 interrupts = <101>;
1315 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1316 clock-names = "ipg", "ahb", "enet_out";
1317 status = "disabled";
1318 };
1319
1320 mac1: ethernet@800f4000 {
1321 compatible = "fsl,imx28-fec";
1322 reg = <0x800f4000 0x4000>;
1323 interrupts = <102>;
1324 clocks = <&clks 57>, <&clks 57>;
1325 clock-names = "ipg", "ahb";
1326 status = "disabled";
1327 };
1328
1329 etn_switch: switch@800f8000 {
1330 reg = <0x800f8000 0x8000>;
1331 status = "disabled";
1332 };
1333 };
1334
1335 iio-hwmon {
1336 compatible = "iio-hwmon";
1337 io-channels = <&lradc 8>;
1338 };
1339};
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include "imx28-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 interrupt-parent = <&icoll>;
20 /*
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
25 */
26 chosen {};
27 memory { device_type = "memory"; reg = <0 0>; };
28
29 aliases {
30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
32 gpio0 = &gpio0;
33 gpio1 = &gpio1;
34 gpio2 = &gpio2;
35 gpio3 = &gpio3;
36 gpio4 = &gpio4;
37 saif0 = &saif0;
38 saif1 = &saif1;
39 serial0 = &auart0;
40 serial1 = &auart1;
41 serial2 = &auart2;
42 serial3 = &auart3;
43 serial4 = &auart4;
44 spi0 = &ssp1;
45 spi1 = &ssp2;
46 usbphy0 = &usbphy0;
47 usbphy1 = &usbphy1;
48 };
49
50 cpus {
51 #address-cells = <0>;
52 #size-cells = <0>;
53
54 cpu {
55 compatible = "arm,arm926ej-s";
56 device_type = "cpu";
57 };
58 };
59
60 apb@80000000 {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 reg = <0x80000000 0x80000>;
65 ranges;
66
67 apbh@80000000 {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 reg = <0x80000000 0x3c900>;
72 ranges;
73
74 icoll: interrupt-controller@80000000 {
75 compatible = "fsl,imx28-icoll", "fsl,icoll";
76 interrupt-controller;
77 #interrupt-cells = <1>;
78 reg = <0x80000000 0x2000>;
79 };
80
81 hsadc: hsadc@80002000 {
82 reg = <0x80002000 0x2000>;
83 interrupts = <13>;
84 dmas = <&dma_apbh 12>;
85 dma-names = "rx";
86 status = "disabled";
87 };
88
89 dma_apbh: dma-apbh@80004000 {
90 compatible = "fsl,imx28-dma-apbh";
91 reg = <0x80004000 0x2000>;
92 interrupts = <82 83 84 85
93 88 88 88 88
94 88 88 88 88
95 87 86 0 0>;
96 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
97 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
98 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
99 "hsadc", "lcdif", "empty", "empty";
100 #dma-cells = <1>;
101 dma-channels = <16>;
102 clocks = <&clks 25>;
103 };
104
105 perfmon: perfmon@80006000 {
106 reg = <0x80006000 0x800>;
107 interrupts = <27>;
108 status = "disabled";
109 };
110
111 gpmi: gpmi-nand@8000c000 {
112 compatible = "fsl,imx28-gpmi-nand";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
116 reg-names = "gpmi-nand", "bch";
117 interrupts = <41>;
118 interrupt-names = "bch";
119 clocks = <&clks 50>;
120 clock-names = "gpmi_io";
121 dmas = <&dma_apbh 4>;
122 dma-names = "rx-tx";
123 status = "disabled";
124 };
125
126 ssp0: ssp@80010000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 reg = <0x80010000 0x2000>;
130 interrupts = <96>;
131 clocks = <&clks 46>;
132 dmas = <&dma_apbh 0>;
133 dma-names = "rx-tx";
134 status = "disabled";
135 };
136
137 ssp1: ssp@80012000 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 reg = <0x80012000 0x2000>;
141 interrupts = <97>;
142 clocks = <&clks 47>;
143 dmas = <&dma_apbh 1>;
144 dma-names = "rx-tx";
145 status = "disabled";
146 };
147
148 ssp2: ssp@80014000 {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 reg = <0x80014000 0x2000>;
152 interrupts = <98>;
153 clocks = <&clks 48>;
154 dmas = <&dma_apbh 2>;
155 dma-names = "rx-tx";
156 status = "disabled";
157 };
158
159 ssp3: ssp@80016000 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <0x80016000 0x2000>;
163 interrupts = <99>;
164 clocks = <&clks 49>;
165 dmas = <&dma_apbh 3>;
166 dma-names = "rx-tx";
167 status = "disabled";
168 };
169
170 pinctrl: pinctrl@80018000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,imx28-pinctrl", "simple-bus";
174 reg = <0x80018000 0x2000>;
175
176 gpio0: gpio@0 {
177 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
178 reg = <0>;
179 interrupts = <127>;
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 gpio1: gpio@1 {
187 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
188 reg = <1>;
189 interrupts = <126>;
190 gpio-controller;
191 #gpio-cells = <2>;
192 interrupt-controller;
193 #interrupt-cells = <2>;
194 };
195
196 gpio2: gpio@2 {
197 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
198 reg = <2>;
199 interrupts = <125>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 };
205
206 gpio3: gpio@3 {
207 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
208 reg = <3>;
209 interrupts = <124>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215
216 gpio4: gpio@4 {
217 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
218 reg = <4>;
219 interrupts = <123>;
220 gpio-controller;
221 #gpio-cells = <2>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
224 };
225
226 duart_pins_a: duart@0 {
227 reg = <0>;
228 fsl,pinmux-ids = <
229 MX28_PAD_PWM0__DUART_RX
230 MX28_PAD_PWM1__DUART_TX
231 >;
232 fsl,drive-strength = <MXS_DRIVE_4mA>;
233 fsl,voltage = <MXS_VOLTAGE_HIGH>;
234 fsl,pull-up = <MXS_PULL_DISABLE>;
235 };
236
237 duart_pins_b: duart@1 {
238 reg = <1>;
239 fsl,pinmux-ids = <
240 MX28_PAD_AUART0_CTS__DUART_RX
241 MX28_PAD_AUART0_RTS__DUART_TX
242 >;
243 fsl,drive-strength = <MXS_DRIVE_4mA>;
244 fsl,voltage = <MXS_VOLTAGE_HIGH>;
245 fsl,pull-up = <MXS_PULL_DISABLE>;
246 };
247
248 duart_4pins_a: duart-4pins@0 {
249 reg = <0>;
250 fsl,pinmux-ids = <
251 MX28_PAD_AUART0_CTS__DUART_RX
252 MX28_PAD_AUART0_RTS__DUART_TX
253 MX28_PAD_AUART0_RX__DUART_CTS
254 MX28_PAD_AUART0_TX__DUART_RTS
255 >;
256 fsl,drive-strength = <MXS_DRIVE_4mA>;
257 fsl,voltage = <MXS_VOLTAGE_HIGH>;
258 fsl,pull-up = <MXS_PULL_DISABLE>;
259 };
260
261 gpmi_pins_a: gpmi-nand@0 {
262 reg = <0>;
263 fsl,pinmux-ids = <
264 MX28_PAD_GPMI_D00__GPMI_D0
265 MX28_PAD_GPMI_D01__GPMI_D1
266 MX28_PAD_GPMI_D02__GPMI_D2
267 MX28_PAD_GPMI_D03__GPMI_D3
268 MX28_PAD_GPMI_D04__GPMI_D4
269 MX28_PAD_GPMI_D05__GPMI_D5
270 MX28_PAD_GPMI_D06__GPMI_D6
271 MX28_PAD_GPMI_D07__GPMI_D7
272 MX28_PAD_GPMI_CE0N__GPMI_CE0N
273 MX28_PAD_GPMI_RDY0__GPMI_READY0
274 MX28_PAD_GPMI_RDN__GPMI_RDN
275 MX28_PAD_GPMI_WRN__GPMI_WRN
276 MX28_PAD_GPMI_ALE__GPMI_ALE
277 MX28_PAD_GPMI_CLE__GPMI_CLE
278 MX28_PAD_GPMI_RESETN__GPMI_RESETN
279 >;
280 fsl,drive-strength = <MXS_DRIVE_4mA>;
281 fsl,voltage = <MXS_VOLTAGE_HIGH>;
282 fsl,pull-up = <MXS_PULL_DISABLE>;
283 };
284
285 gpmi_status_cfg: gpmi-status-cfg {
286 fsl,pinmux-ids = <
287 MX28_PAD_GPMI_RDN__GPMI_RDN
288 MX28_PAD_GPMI_WRN__GPMI_WRN
289 MX28_PAD_GPMI_RESETN__GPMI_RESETN
290 >;
291 fsl,drive-strength = <MXS_DRIVE_12mA>;
292 };
293
294 auart0_pins_a: auart0@0 {
295 reg = <0>;
296 fsl,pinmux-ids = <
297 MX28_PAD_AUART0_RX__AUART0_RX
298 MX28_PAD_AUART0_TX__AUART0_TX
299 MX28_PAD_AUART0_CTS__AUART0_CTS
300 MX28_PAD_AUART0_RTS__AUART0_RTS
301 >;
302 fsl,drive-strength = <MXS_DRIVE_4mA>;
303 fsl,voltage = <MXS_VOLTAGE_HIGH>;
304 fsl,pull-up = <MXS_PULL_DISABLE>;
305 };
306
307 auart0_2pins_a: auart0-2pins@0 {
308 reg = <0>;
309 fsl,pinmux-ids = <
310 MX28_PAD_AUART0_RX__AUART0_RX
311 MX28_PAD_AUART0_TX__AUART0_TX
312 >;
313 fsl,drive-strength = <MXS_DRIVE_4mA>;
314 fsl,voltage = <MXS_VOLTAGE_HIGH>;
315 fsl,pull-up = <MXS_PULL_DISABLE>;
316 };
317
318 auart1_pins_a: auart1@0 {
319 reg = <0>;
320 fsl,pinmux-ids = <
321 MX28_PAD_AUART1_RX__AUART1_RX
322 MX28_PAD_AUART1_TX__AUART1_TX
323 MX28_PAD_AUART1_CTS__AUART1_CTS
324 MX28_PAD_AUART1_RTS__AUART1_RTS
325 >;
326 fsl,drive-strength = <MXS_DRIVE_4mA>;
327 fsl,voltage = <MXS_VOLTAGE_HIGH>;
328 fsl,pull-up = <MXS_PULL_DISABLE>;
329 };
330
331 auart1_2pins_a: auart1-2pins@0 {
332 reg = <0>;
333 fsl,pinmux-ids = <
334 MX28_PAD_AUART1_RX__AUART1_RX
335 MX28_PAD_AUART1_TX__AUART1_TX
336 >;
337 fsl,drive-strength = <MXS_DRIVE_4mA>;
338 fsl,voltage = <MXS_VOLTAGE_HIGH>;
339 fsl,pull-up = <MXS_PULL_DISABLE>;
340 };
341
342 auart2_2pins_a: auart2-2pins@0 {
343 reg = <0>;
344 fsl,pinmux-ids = <
345 MX28_PAD_SSP2_SCK__AUART2_RX
346 MX28_PAD_SSP2_MOSI__AUART2_TX
347 >;
348 fsl,drive-strength = <MXS_DRIVE_4mA>;
349 fsl,voltage = <MXS_VOLTAGE_HIGH>;
350 fsl,pull-up = <MXS_PULL_DISABLE>;
351 };
352
353 auart2_2pins_b: auart2-2pins@1 {
354 reg = <1>;
355 fsl,pinmux-ids = <
356 MX28_PAD_AUART2_RX__AUART2_RX
357 MX28_PAD_AUART2_TX__AUART2_TX
358 >;
359 fsl,drive-strength = <MXS_DRIVE_4mA>;
360 fsl,voltage = <MXS_VOLTAGE_HIGH>;
361 fsl,pull-up = <MXS_PULL_DISABLE>;
362 };
363
364 auart2_pins_a: auart2-pins@0 {
365 reg = <0>;
366 fsl,pinmux-ids = <
367 MX28_PAD_AUART2_RX__AUART2_RX
368 MX28_PAD_AUART2_TX__AUART2_TX
369 MX28_PAD_AUART2_CTS__AUART2_CTS
370 MX28_PAD_AUART2_RTS__AUART2_RTS
371 >;
372 fsl,drive-strength = <MXS_DRIVE_4mA>;
373 fsl,voltage = <MXS_VOLTAGE_HIGH>;
374 fsl,pull-up = <MXS_PULL_DISABLE>;
375 };
376
377 auart3_pins_a: auart3@0 {
378 reg = <0>;
379 fsl,pinmux-ids = <
380 MX28_PAD_AUART3_RX__AUART3_RX
381 MX28_PAD_AUART3_TX__AUART3_TX
382 MX28_PAD_AUART3_CTS__AUART3_CTS
383 MX28_PAD_AUART3_RTS__AUART3_RTS
384 >;
385 fsl,drive-strength = <MXS_DRIVE_4mA>;
386 fsl,voltage = <MXS_VOLTAGE_HIGH>;
387 fsl,pull-up = <MXS_PULL_DISABLE>;
388 };
389
390 auart3_2pins_a: auart3-2pins@0 {
391 reg = <0>;
392 fsl,pinmux-ids = <
393 MX28_PAD_SSP2_MISO__AUART3_RX
394 MX28_PAD_SSP2_SS0__AUART3_TX
395 >;
396 fsl,drive-strength = <MXS_DRIVE_4mA>;
397 fsl,voltage = <MXS_VOLTAGE_HIGH>;
398 fsl,pull-up = <MXS_PULL_DISABLE>;
399 };
400
401 auart3_2pins_b: auart3-2pins@1 {
402 reg = <1>;
403 fsl,pinmux-ids = <
404 MX28_PAD_AUART3_RX__AUART3_RX
405 MX28_PAD_AUART3_TX__AUART3_TX
406 >;
407 fsl,drive-strength = <MXS_DRIVE_4mA>;
408 fsl,voltage = <MXS_VOLTAGE_HIGH>;
409 fsl,pull-up = <MXS_PULL_DISABLE>;
410 };
411
412 auart4_2pins_a: auart4@0 {
413 reg = <0>;
414 fsl,pinmux-ids = <
415 MX28_PAD_SSP3_SCK__AUART4_TX
416 MX28_PAD_SSP3_MOSI__AUART4_RX
417 >;
418 fsl,drive-strength = <MXS_DRIVE_4mA>;
419 fsl,voltage = <MXS_VOLTAGE_HIGH>;
420 fsl,pull-up = <MXS_PULL_DISABLE>;
421 };
422
423 auart4_2pins_b: auart4@1 {
424 reg = <1>;
425 fsl,pinmux-ids = <
426 MX28_PAD_AUART0_CTS__AUART4_RX
427 MX28_PAD_AUART0_RTS__AUART4_TX
428 >;
429 fsl,drive-strength = <MXS_DRIVE_4mA>;
430 fsl,voltage = <MXS_VOLTAGE_HIGH>;
431 fsl,pull-up = <MXS_PULL_DISABLE>;
432 };
433
434 mac0_pins_a: mac0@0 {
435 reg = <0>;
436 fsl,pinmux-ids = <
437 MX28_PAD_ENET0_MDC__ENET0_MDC
438 MX28_PAD_ENET0_MDIO__ENET0_MDIO
439 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
440 MX28_PAD_ENET0_RXD0__ENET0_RXD0
441 MX28_PAD_ENET0_RXD1__ENET0_RXD1
442 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
443 MX28_PAD_ENET0_TXD0__ENET0_TXD0
444 MX28_PAD_ENET0_TXD1__ENET0_TXD1
445 MX28_PAD_ENET_CLK__CLKCTRL_ENET
446 >;
447 fsl,drive-strength = <MXS_DRIVE_8mA>;
448 fsl,voltage = <MXS_VOLTAGE_HIGH>;
449 fsl,pull-up = <MXS_PULL_ENABLE>;
450 };
451
452 mac0_pins_b: mac0@1 {
453 reg = <1>;
454 fsl,pinmux-ids = <
455 MX28_PAD_ENET0_MDC__ENET0_MDC
456 MX28_PAD_ENET0_MDIO__ENET0_MDIO
457 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
458 MX28_PAD_ENET0_RXD0__ENET0_RXD0
459 MX28_PAD_ENET0_RXD1__ENET0_RXD1
460 MX28_PAD_ENET0_RXD2__ENET0_RXD2
461 MX28_PAD_ENET0_RXD3__ENET0_RXD3
462 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
463 MX28_PAD_ENET0_TXD0__ENET0_TXD0
464 MX28_PAD_ENET0_TXD1__ENET0_TXD1
465 MX28_PAD_ENET0_TXD2__ENET0_TXD2
466 MX28_PAD_ENET0_TXD3__ENET0_TXD3
467 MX28_PAD_ENET_CLK__CLKCTRL_ENET
468 MX28_PAD_ENET0_COL__ENET0_COL
469 MX28_PAD_ENET0_CRS__ENET0_CRS
470 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
471 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
472 >;
473 fsl,drive-strength = <MXS_DRIVE_8mA>;
474 fsl,voltage = <MXS_VOLTAGE_HIGH>;
475 fsl,pull-up = <MXS_PULL_ENABLE>;
476 };
477
478 mac1_pins_a: mac1@0 {
479 reg = <0>;
480 fsl,pinmux-ids = <
481 MX28_PAD_ENET0_CRS__ENET1_RX_EN
482 MX28_PAD_ENET0_RXD2__ENET1_RXD0
483 MX28_PAD_ENET0_RXD3__ENET1_RXD1
484 MX28_PAD_ENET0_COL__ENET1_TX_EN
485 MX28_PAD_ENET0_TXD2__ENET1_TXD0
486 MX28_PAD_ENET0_TXD3__ENET1_TXD1
487 >;
488 fsl,drive-strength = <MXS_DRIVE_8mA>;
489 fsl,voltage = <MXS_VOLTAGE_HIGH>;
490 fsl,pull-up = <MXS_PULL_ENABLE>;
491 };
492
493 mmc0_8bit_pins_a: mmc0-8bit@0 {
494 reg = <0>;
495 fsl,pinmux-ids = <
496 MX28_PAD_SSP0_DATA0__SSP0_D0
497 MX28_PAD_SSP0_DATA1__SSP0_D1
498 MX28_PAD_SSP0_DATA2__SSP0_D2
499 MX28_PAD_SSP0_DATA3__SSP0_D3
500 MX28_PAD_SSP0_DATA4__SSP0_D4
501 MX28_PAD_SSP0_DATA5__SSP0_D5
502 MX28_PAD_SSP0_DATA6__SSP0_D6
503 MX28_PAD_SSP0_DATA7__SSP0_D7
504 MX28_PAD_SSP0_CMD__SSP0_CMD
505 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
506 MX28_PAD_SSP0_SCK__SSP0_SCK
507 >;
508 fsl,drive-strength = <MXS_DRIVE_8mA>;
509 fsl,voltage = <MXS_VOLTAGE_HIGH>;
510 fsl,pull-up = <MXS_PULL_ENABLE>;
511 };
512
513 mmc0_4bit_pins_a: mmc0-4bit@0 {
514 reg = <0>;
515 fsl,pinmux-ids = <
516 MX28_PAD_SSP0_DATA0__SSP0_D0
517 MX28_PAD_SSP0_DATA1__SSP0_D1
518 MX28_PAD_SSP0_DATA2__SSP0_D2
519 MX28_PAD_SSP0_DATA3__SSP0_D3
520 MX28_PAD_SSP0_CMD__SSP0_CMD
521 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
522 MX28_PAD_SSP0_SCK__SSP0_SCK
523 >;
524 fsl,drive-strength = <MXS_DRIVE_8mA>;
525 fsl,voltage = <MXS_VOLTAGE_HIGH>;
526 fsl,pull-up = <MXS_PULL_ENABLE>;
527 };
528
529 mmc0_cd_cfg: mmc0-cd-cfg {
530 fsl,pinmux-ids = <
531 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
532 >;
533 fsl,pull-up = <MXS_PULL_DISABLE>;
534 };
535
536 mmc0_sck_cfg: mmc0-sck-cfg {
537 fsl,pinmux-ids = <
538 MX28_PAD_SSP0_SCK__SSP0_SCK
539 >;
540 fsl,drive-strength = <MXS_DRIVE_12mA>;
541 fsl,pull-up = <MXS_PULL_DISABLE>;
542 };
543
544 mmc1_4bit_pins_a: mmc1-4bit@0 {
545 reg = <0>;
546 fsl,pinmux-ids = <
547 MX28_PAD_GPMI_D00__SSP1_D0
548 MX28_PAD_GPMI_D01__SSP1_D1
549 MX28_PAD_GPMI_D02__SSP1_D2
550 MX28_PAD_GPMI_D03__SSP1_D3
551 MX28_PAD_GPMI_RDY1__SSP1_CMD
552 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
553 MX28_PAD_GPMI_WRN__SSP1_SCK
554 >;
555 fsl,drive-strength = <MXS_DRIVE_8mA>;
556 fsl,voltage = <MXS_VOLTAGE_HIGH>;
557 fsl,pull-up = <MXS_PULL_ENABLE>;
558 };
559
560 mmc1_cd_cfg: mmc1-cd-cfg {
561 fsl,pinmux-ids = <
562 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
563 >;
564 fsl,pull-up = <MXS_PULL_DISABLE>;
565 };
566
567 mmc1_sck_cfg: mmc1-sck-cfg {
568 fsl,pinmux-ids = <
569 MX28_PAD_GPMI_WRN__SSP1_SCK
570 >;
571 fsl,drive-strength = <MXS_DRIVE_12mA>;
572 fsl,pull-up = <MXS_PULL_DISABLE>;
573 };
574
575
576 mmc2_4bit_pins_a: mmc2-4bit@0 {
577 reg = <0>;
578 fsl,pinmux-ids = <
579 MX28_PAD_SSP0_DATA4__SSP2_D0
580 MX28_PAD_SSP1_SCK__SSP2_D1
581 MX28_PAD_SSP1_CMD__SSP2_D2
582 MX28_PAD_SSP0_DATA5__SSP2_D3
583 MX28_PAD_SSP0_DATA6__SSP2_CMD
584 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
585 MX28_PAD_SSP0_DATA7__SSP2_SCK
586 >;
587 fsl,drive-strength = <MXS_DRIVE_8mA>;
588 fsl,voltage = <MXS_VOLTAGE_HIGH>;
589 fsl,pull-up = <MXS_PULL_ENABLE>;
590 };
591
592 mmc2_cd_cfg: mmc2-cd-cfg {
593 fsl,pinmux-ids = <
594 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
595 >;
596 fsl,pull-up = <MXS_PULL_DISABLE>;
597 };
598
599 mmc2_sck_cfg: mmc2-sck-cfg {
600 fsl,pinmux-ids = <
601 MX28_PAD_SSP0_DATA7__SSP2_SCK
602 >;
603 fsl,drive-strength = <MXS_DRIVE_12mA>;
604 fsl,pull-up = <MXS_PULL_DISABLE>;
605 };
606
607 i2c0_pins_a: i2c0@0 {
608 reg = <0>;
609 fsl,pinmux-ids = <
610 MX28_PAD_I2C0_SCL__I2C0_SCL
611 MX28_PAD_I2C0_SDA__I2C0_SDA
612 >;
613 fsl,drive-strength = <MXS_DRIVE_8mA>;
614 fsl,voltage = <MXS_VOLTAGE_HIGH>;
615 fsl,pull-up = <MXS_PULL_ENABLE>;
616 };
617
618 i2c0_pins_b: i2c0@1 {
619 reg = <1>;
620 fsl,pinmux-ids = <
621 MX28_PAD_AUART0_RX__I2C0_SCL
622 MX28_PAD_AUART0_TX__I2C0_SDA
623 >;
624 fsl,drive-strength = <MXS_DRIVE_8mA>;
625 fsl,voltage = <MXS_VOLTAGE_HIGH>;
626 fsl,pull-up = <MXS_PULL_ENABLE>;
627 };
628
629 i2c1_pins_a: i2c1@0 {
630 reg = <0>;
631 fsl,pinmux-ids = <
632 MX28_PAD_PWM0__I2C1_SCL
633 MX28_PAD_PWM1__I2C1_SDA
634 >;
635 fsl,drive-strength = <MXS_DRIVE_8mA>;
636 fsl,voltage = <MXS_VOLTAGE_HIGH>;
637 fsl,pull-up = <MXS_PULL_ENABLE>;
638 };
639
640 i2c1_pins_b: i2c1@1 {
641 reg = <1>;
642 fsl,pinmux-ids = <
643 MX28_PAD_AUART2_CTS__I2C1_SCL
644 MX28_PAD_AUART2_RTS__I2C1_SDA
645 >;
646 fsl,drive-strength = <MXS_DRIVE_8mA>;
647 fsl,voltage = <MXS_VOLTAGE_HIGH>;
648 fsl,pull-up = <MXS_PULL_ENABLE>;
649 };
650
651 saif0_pins_a: saif0@0 {
652 reg = <0>;
653 fsl,pinmux-ids = <
654 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
655 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
656 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
657 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
658 >;
659 fsl,drive-strength = <MXS_DRIVE_12mA>;
660 fsl,voltage = <MXS_VOLTAGE_HIGH>;
661 fsl,pull-up = <MXS_PULL_ENABLE>;
662 };
663
664 saif0_pins_b: saif0@1 {
665 reg = <1>;
666 fsl,pinmux-ids = <
667 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
668 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
669 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
670 >;
671 fsl,drive-strength = <MXS_DRIVE_12mA>;
672 fsl,voltage = <MXS_VOLTAGE_HIGH>;
673 fsl,pull-up = <MXS_PULL_ENABLE>;
674 };
675
676 saif1_pins_a: saif1@0 {
677 reg = <0>;
678 fsl,pinmux-ids = <
679 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
680 >;
681 fsl,drive-strength = <MXS_DRIVE_12mA>;
682 fsl,voltage = <MXS_VOLTAGE_HIGH>;
683 fsl,pull-up = <MXS_PULL_ENABLE>;
684 };
685
686 pwm0_pins_a: pwm0@0 {
687 reg = <0>;
688 fsl,pinmux-ids = <
689 MX28_PAD_PWM0__PWM_0
690 >;
691 fsl,drive-strength = <MXS_DRIVE_4mA>;
692 fsl,voltage = <MXS_VOLTAGE_HIGH>;
693 fsl,pull-up = <MXS_PULL_DISABLE>;
694 };
695
696 pwm2_pins_a: pwm2@0 {
697 reg = <0>;
698 fsl,pinmux-ids = <
699 MX28_PAD_PWM2__PWM_2
700 >;
701 fsl,drive-strength = <MXS_DRIVE_4mA>;
702 fsl,voltage = <MXS_VOLTAGE_HIGH>;
703 fsl,pull-up = <MXS_PULL_DISABLE>;
704 };
705
706 pwm3_pins_a: pwm3@0 {
707 reg = <0>;
708 fsl,pinmux-ids = <
709 MX28_PAD_PWM3__PWM_3
710 >;
711 fsl,drive-strength = <MXS_DRIVE_4mA>;
712 fsl,voltage = <MXS_VOLTAGE_HIGH>;
713 fsl,pull-up = <MXS_PULL_DISABLE>;
714 };
715
716 pwm3_pins_b: pwm3@1 {
717 reg = <1>;
718 fsl,pinmux-ids = <
719 MX28_PAD_SAIF0_MCLK__PWM_3
720 >;
721 fsl,drive-strength = <MXS_DRIVE_4mA>;
722 fsl,voltage = <MXS_VOLTAGE_HIGH>;
723 fsl,pull-up = <MXS_PULL_DISABLE>;
724 };
725
726 pwm4_pins_a: pwm4@0 {
727 reg = <0>;
728 fsl,pinmux-ids = <
729 MX28_PAD_PWM4__PWM_4
730 >;
731 fsl,drive-strength = <MXS_DRIVE_4mA>;
732 fsl,voltage = <MXS_VOLTAGE_HIGH>;
733 fsl,pull-up = <MXS_PULL_DISABLE>;
734 };
735
736 lcdif_24bit_pins_a: lcdif-24bit@0 {
737 reg = <0>;
738 fsl,pinmux-ids = <
739 MX28_PAD_LCD_D00__LCD_D0
740 MX28_PAD_LCD_D01__LCD_D1
741 MX28_PAD_LCD_D02__LCD_D2
742 MX28_PAD_LCD_D03__LCD_D3
743 MX28_PAD_LCD_D04__LCD_D4
744 MX28_PAD_LCD_D05__LCD_D5
745 MX28_PAD_LCD_D06__LCD_D6
746 MX28_PAD_LCD_D07__LCD_D7
747 MX28_PAD_LCD_D08__LCD_D8
748 MX28_PAD_LCD_D09__LCD_D9
749 MX28_PAD_LCD_D10__LCD_D10
750 MX28_PAD_LCD_D11__LCD_D11
751 MX28_PAD_LCD_D12__LCD_D12
752 MX28_PAD_LCD_D13__LCD_D13
753 MX28_PAD_LCD_D14__LCD_D14
754 MX28_PAD_LCD_D15__LCD_D15
755 MX28_PAD_LCD_D16__LCD_D16
756 MX28_PAD_LCD_D17__LCD_D17
757 MX28_PAD_LCD_D18__LCD_D18
758 MX28_PAD_LCD_D19__LCD_D19
759 MX28_PAD_LCD_D20__LCD_D20
760 MX28_PAD_LCD_D21__LCD_D21
761 MX28_PAD_LCD_D22__LCD_D22
762 MX28_PAD_LCD_D23__LCD_D23
763 >;
764 fsl,drive-strength = <MXS_DRIVE_4mA>;
765 fsl,voltage = <MXS_VOLTAGE_HIGH>;
766 fsl,pull-up = <MXS_PULL_DISABLE>;
767 };
768
769 lcdif_18bit_pins_a: lcdif-18bit@0 {
770 reg = <0>;
771 fsl,pinmux-ids = <
772 MX28_PAD_LCD_D00__LCD_D0
773 MX28_PAD_LCD_D01__LCD_D1
774 MX28_PAD_LCD_D02__LCD_D2
775 MX28_PAD_LCD_D03__LCD_D3
776 MX28_PAD_LCD_D04__LCD_D4
777 MX28_PAD_LCD_D05__LCD_D5
778 MX28_PAD_LCD_D06__LCD_D6
779 MX28_PAD_LCD_D07__LCD_D7
780 MX28_PAD_LCD_D08__LCD_D8
781 MX28_PAD_LCD_D09__LCD_D9
782 MX28_PAD_LCD_D10__LCD_D10
783 MX28_PAD_LCD_D11__LCD_D11
784 MX28_PAD_LCD_D12__LCD_D12
785 MX28_PAD_LCD_D13__LCD_D13
786 MX28_PAD_LCD_D14__LCD_D14
787 MX28_PAD_LCD_D15__LCD_D15
788 MX28_PAD_LCD_D16__LCD_D16
789 MX28_PAD_LCD_D17__LCD_D17
790 >;
791 fsl,drive-strength = <MXS_DRIVE_4mA>;
792 fsl,voltage = <MXS_VOLTAGE_HIGH>;
793 fsl,pull-up = <MXS_PULL_DISABLE>;
794 };
795
796 lcdif_16bit_pins_a: lcdif-16bit@0 {
797 reg = <0>;
798 fsl,pinmux-ids = <
799 MX28_PAD_LCD_D00__LCD_D0
800 MX28_PAD_LCD_D01__LCD_D1
801 MX28_PAD_LCD_D02__LCD_D2
802 MX28_PAD_LCD_D03__LCD_D3
803 MX28_PAD_LCD_D04__LCD_D4
804 MX28_PAD_LCD_D05__LCD_D5
805 MX28_PAD_LCD_D06__LCD_D6
806 MX28_PAD_LCD_D07__LCD_D7
807 MX28_PAD_LCD_D08__LCD_D8
808 MX28_PAD_LCD_D09__LCD_D9
809 MX28_PAD_LCD_D10__LCD_D10
810 MX28_PAD_LCD_D11__LCD_D11
811 MX28_PAD_LCD_D12__LCD_D12
812 MX28_PAD_LCD_D13__LCD_D13
813 MX28_PAD_LCD_D14__LCD_D14
814 MX28_PAD_LCD_D15__LCD_D15
815 >;
816 fsl,drive-strength = <MXS_DRIVE_4mA>;
817 fsl,voltage = <MXS_VOLTAGE_HIGH>;
818 fsl,pull-up = <MXS_PULL_DISABLE>;
819 };
820
821 lcdif_sync_pins_a: lcdif-sync@0 {
822 reg = <0>;
823 fsl,pinmux-ids = <
824 MX28_PAD_LCD_RS__LCD_DOTCLK
825 MX28_PAD_LCD_CS__LCD_ENABLE
826 MX28_PAD_LCD_RD_E__LCD_VSYNC
827 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
828 >;
829 fsl,drive-strength = <MXS_DRIVE_4mA>;
830 fsl,voltage = <MXS_VOLTAGE_HIGH>;
831 fsl,pull-up = <MXS_PULL_DISABLE>;
832 };
833
834 can0_pins_a: can0@0 {
835 reg = <0>;
836 fsl,pinmux-ids = <
837 MX28_PAD_GPMI_RDY2__CAN0_TX
838 MX28_PAD_GPMI_RDY3__CAN0_RX
839 >;
840 fsl,drive-strength = <MXS_DRIVE_4mA>;
841 fsl,voltage = <MXS_VOLTAGE_HIGH>;
842 fsl,pull-up = <MXS_PULL_DISABLE>;
843 };
844
845 can1_pins_a: can1@0 {
846 reg = <0>;
847 fsl,pinmux-ids = <
848 MX28_PAD_GPMI_CE2N__CAN1_TX
849 MX28_PAD_GPMI_CE3N__CAN1_RX
850 >;
851 fsl,drive-strength = <MXS_DRIVE_4mA>;
852 fsl,voltage = <MXS_VOLTAGE_HIGH>;
853 fsl,pull-up = <MXS_PULL_DISABLE>;
854 };
855
856 spi2_pins_a: spi2@0 {
857 reg = <0>;
858 fsl,pinmux-ids = <
859 MX28_PAD_SSP2_SCK__SSP2_SCK
860 MX28_PAD_SSP2_MOSI__SSP2_CMD
861 MX28_PAD_SSP2_MISO__SSP2_D0
862 MX28_PAD_SSP2_SS0__SSP2_D3
863 >;
864 fsl,drive-strength = <MXS_DRIVE_8mA>;
865 fsl,voltage = <MXS_VOLTAGE_HIGH>;
866 fsl,pull-up = <MXS_PULL_ENABLE>;
867 };
868
869 spi3_pins_a: spi3@0 {
870 reg = <0>;
871 fsl,pinmux-ids = <
872 MX28_PAD_AUART2_RX__SSP3_D4
873 MX28_PAD_AUART2_TX__SSP3_D5
874 MX28_PAD_SSP3_SCK__SSP3_SCK
875 MX28_PAD_SSP3_MOSI__SSP3_CMD
876 MX28_PAD_SSP3_MISO__SSP3_D0
877 MX28_PAD_SSP3_SS0__SSP3_D3
878 >;
879 fsl,drive-strength = <MXS_DRIVE_8mA>;
880 fsl,voltage = <MXS_VOLTAGE_HIGH>;
881 fsl,pull-up = <MXS_PULL_DISABLE>;
882 };
883
884 spi3_pins_b: spi3@1 {
885 reg = <1>;
886 fsl,pinmux-ids = <
887 MX28_PAD_SSP3_SCK__SSP3_SCK
888 MX28_PAD_SSP3_MOSI__SSP3_CMD
889 MX28_PAD_SSP3_MISO__SSP3_D0
890 MX28_PAD_SSP3_SS0__SSP3_D3
891 >;
892 fsl,drive-strength = <MXS_DRIVE_8mA>;
893 fsl,voltage = <MXS_VOLTAGE_HIGH>;
894 fsl,pull-up = <MXS_PULL_ENABLE>;
895 };
896
897 usb0_pins_a: usb0@0 {
898 reg = <0>;
899 fsl,pinmux-ids = <
900 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
901 >;
902 fsl,drive-strength = <MXS_DRIVE_12mA>;
903 fsl,voltage = <MXS_VOLTAGE_HIGH>;
904 fsl,pull-up = <MXS_PULL_DISABLE>;
905 };
906
907 usb0_pins_b: usb0@1 {
908 reg = <1>;
909 fsl,pinmux-ids = <
910 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
911 >;
912 fsl,drive-strength = <MXS_DRIVE_12mA>;
913 fsl,voltage = <MXS_VOLTAGE_HIGH>;
914 fsl,pull-up = <MXS_PULL_DISABLE>;
915 };
916
917 usb1_pins_a: usb1@0 {
918 reg = <0>;
919 fsl,pinmux-ids = <
920 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
921 >;
922 fsl,drive-strength = <MXS_DRIVE_12mA>;
923 fsl,voltage = <MXS_VOLTAGE_HIGH>;
924 fsl,pull-up = <MXS_PULL_DISABLE>;
925 };
926
927 usb0_id_pins_a: usb0id@0 {
928 reg = <0>;
929 fsl,pinmux-ids = <
930 MX28_PAD_AUART1_RTS__USB0_ID
931 >;
932 fsl,drive-strength = <MXS_DRIVE_12mA>;
933 fsl,voltage = <MXS_VOLTAGE_HIGH>;
934 fsl,pull-up = <MXS_PULL_ENABLE>;
935 };
936
937 usb0_id_pins_b: usb0id1@0 {
938 reg = <0>;
939 fsl,pinmux-ids = <
940 MX28_PAD_PWM2__USB0_ID
941 >;
942 fsl,drive-strength = <MXS_DRIVE_12mA>;
943 fsl,voltage = <MXS_VOLTAGE_HIGH>;
944 fsl,pull-up = <MXS_PULL_ENABLE>;
945 };
946
947 };
948
949 digctl: digctl@8001c000 {
950 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
951 reg = <0x8001c000 0x2000>;
952 interrupts = <89>;
953 status = "disabled";
954 };
955
956 etm: etm@80022000 {
957 reg = <0x80022000 0x2000>;
958 status = "disabled";
959 };
960
961 dma_apbx: dma-apbx@80024000 {
962 compatible = "fsl,imx28-dma-apbx";
963 reg = <0x80024000 0x2000>;
964 interrupts = <78 79 66 0
965 80 81 68 69
966 70 71 72 73
967 74 75 76 77>;
968 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
969 "saif0", "saif1", "i2c0", "i2c1",
970 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
971 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
972 #dma-cells = <1>;
973 dma-channels = <16>;
974 clocks = <&clks 26>;
975 };
976
977 dcp: dcp@80028000 {
978 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
979 reg = <0x80028000 0x2000>;
980 interrupts = <52 53 54>;
981 status = "okay";
982 };
983
984 pxp: pxp@8002a000 {
985 reg = <0x8002a000 0x2000>;
986 interrupts = <39>;
987 status = "disabled";
988 };
989
990 ocotp: ocotp@8002c000 {
991 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
992 #address-cells = <1>;
993 #size-cells = <1>;
994 reg = <0x8002c000 0x2000>;
995 clocks = <&clks 25>;
996 };
997
998 axi-ahb@8002e000 {
999 reg = <0x8002e000 0x2000>;
1000 status = "disabled";
1001 };
1002
1003 lcdif: lcdif@80030000 {
1004 compatible = "fsl,imx28-lcdif";
1005 reg = <0x80030000 0x2000>;
1006 interrupts = <38>;
1007 clocks = <&clks 55>;
1008 dmas = <&dma_apbh 13>;
1009 dma-names = "rx";
1010 status = "disabled";
1011 };
1012
1013 can0: can@80032000 {
1014 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
1015 reg = <0x80032000 0x2000>;
1016 interrupts = <8>;
1017 clocks = <&clks 58>, <&clks 58>;
1018 clock-names = "ipg", "per";
1019 status = "disabled";
1020 };
1021
1022 can1: can@80034000 {
1023 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
1024 reg = <0x80034000 0x2000>;
1025 interrupts = <9>;
1026 clocks = <&clks 59>, <&clks 59>;
1027 clock-names = "ipg", "per";
1028 status = "disabled";
1029 };
1030
1031 simdbg: simdbg@8003c000 {
1032 reg = <0x8003c000 0x200>;
1033 status = "disabled";
1034 };
1035
1036 simgpmisel: simgpmisel@8003c200 {
1037 reg = <0x8003c200 0x100>;
1038 status = "disabled";
1039 };
1040
1041 simsspsel: simsspsel@8003c300 {
1042 reg = <0x8003c300 0x100>;
1043 status = "disabled";
1044 };
1045
1046 simmemsel: simmemsel@8003c400 {
1047 reg = <0x8003c400 0x100>;
1048 status = "disabled";
1049 };
1050
1051 gpiomon: gpiomon@8003c500 {
1052 reg = <0x8003c500 0x100>;
1053 status = "disabled";
1054 };
1055
1056 simenet: simenet@8003c700 {
1057 reg = <0x8003c700 0x100>;
1058 status = "disabled";
1059 };
1060
1061 armjtag: armjtag@8003c800 {
1062 reg = <0x8003c800 0x100>;
1063 status = "disabled";
1064 };
1065 };
1066
1067 apbx@80040000 {
1068 compatible = "simple-bus";
1069 #address-cells = <1>;
1070 #size-cells = <1>;
1071 reg = <0x80040000 0x40000>;
1072 ranges;
1073
1074 clks: clkctrl@80040000 {
1075 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1076 reg = <0x80040000 0x2000>;
1077 #clock-cells = <1>;
1078 };
1079
1080 saif0: saif@80042000 {
1081 compatible = "fsl,imx28-saif";
1082 reg = <0x80042000 0x2000>;
1083 interrupts = <59>;
1084 #clock-cells = <0>;
1085 clocks = <&clks 53>;
1086 dmas = <&dma_apbx 4>;
1087 dma-names = "rx-tx";
1088 status = "disabled";
1089 };
1090
1091 power: power@80044000 {
1092 reg = <0x80044000 0x2000>;
1093 status = "disabled";
1094 };
1095
1096 saif1: saif@80046000 {
1097 compatible = "fsl,imx28-saif";
1098 reg = <0x80046000 0x2000>;
1099 interrupts = <58>;
1100 clocks = <&clks 54>;
1101 dmas = <&dma_apbx 5>;
1102 dma-names = "rx-tx";
1103 status = "disabled";
1104 };
1105
1106 lradc: lradc@80050000 {
1107 compatible = "fsl,imx28-lradc";
1108 reg = <0x80050000 0x2000>;
1109 interrupts = <10 14 15 16 17 18 19
1110 20 21 22 23 24 25>;
1111 status = "disabled";
1112 clocks = <&clks 41>;
1113 #io-channel-cells = <1>;
1114 };
1115
1116 spdif: spdif@80054000 {
1117 reg = <0x80054000 0x2000>;
1118 interrupts = <45>;
1119 dmas = <&dma_apbx 2>;
1120 dma-names = "tx";
1121 status = "disabled";
1122 };
1123
1124 mxs_rtc: rtc@80056000 {
1125 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1126 reg = <0x80056000 0x2000>;
1127 interrupts = <29>;
1128 };
1129
1130 i2c0: i2c@80058000 {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 compatible = "fsl,imx28-i2c";
1134 reg = <0x80058000 0x2000>;
1135 interrupts = <111>;
1136 clock-frequency = <100000>;
1137 dmas = <&dma_apbx 6>;
1138 dma-names = "rx-tx";
1139 status = "disabled";
1140 };
1141
1142 i2c1: i2c@8005a000 {
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 compatible = "fsl,imx28-i2c";
1146 reg = <0x8005a000 0x2000>;
1147 interrupts = <110>;
1148 clock-frequency = <100000>;
1149 dmas = <&dma_apbx 7>;
1150 dma-names = "rx-tx";
1151 status = "disabled";
1152 };
1153
1154 pwm: pwm@80064000 {
1155 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1156 reg = <0x80064000 0x2000>;
1157 clocks = <&clks 44>;
1158 #pwm-cells = <2>;
1159 fsl,pwm-number = <8>;
1160 status = "disabled";
1161 };
1162
1163 timer: timrot@80068000 {
1164 compatible = "fsl,imx28-timrot", "fsl,timrot";
1165 reg = <0x80068000 0x2000>;
1166 interrupts = <48 49 50 51>;
1167 clocks = <&clks 26>;
1168 };
1169
1170 auart0: serial@8006a000 {
1171 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1172 reg = <0x8006a000 0x2000>;
1173 interrupts = <112>;
1174 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1175 dma-names = "rx", "tx";
1176 clocks = <&clks 45>;
1177 status = "disabled";
1178 };
1179
1180 auart1: serial@8006c000 {
1181 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1182 reg = <0x8006c000 0x2000>;
1183 interrupts = <113>;
1184 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1185 dma-names = "rx", "tx";
1186 clocks = <&clks 45>;
1187 status = "disabled";
1188 };
1189
1190 auart2: serial@8006e000 {
1191 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1192 reg = <0x8006e000 0x2000>;
1193 interrupts = <114>;
1194 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1195 dma-names = "rx", "tx";
1196 clocks = <&clks 45>;
1197 status = "disabled";
1198 };
1199
1200 auart3: serial@80070000 {
1201 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1202 reg = <0x80070000 0x2000>;
1203 interrupts = <115>;
1204 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1205 dma-names = "rx", "tx";
1206 clocks = <&clks 45>;
1207 status = "disabled";
1208 };
1209
1210 auart4: serial@80072000 {
1211 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1212 reg = <0x80072000 0x2000>;
1213 interrupts = <116>;
1214 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1215 dma-names = "rx", "tx";
1216 clocks = <&clks 45>;
1217 status = "disabled";
1218 };
1219
1220 duart: serial@80074000 {
1221 compatible = "arm,pl011", "arm,primecell";
1222 reg = <0x80074000 0x1000>;
1223 interrupts = <47>;
1224 clocks = <&clks 45>, <&clks 26>;
1225 clock-names = "uart", "apb_pclk";
1226 status = "disabled";
1227 };
1228
1229 usbphy0: usbphy@8007c000 {
1230 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1231 reg = <0x8007c000 0x2000>;
1232 clocks = <&clks 62>;
1233 status = "disabled";
1234 };
1235
1236 usbphy1: usbphy@8007e000 {
1237 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1238 reg = <0x8007e000 0x2000>;
1239 clocks = <&clks 63>;
1240 status = "disabled";
1241 };
1242 };
1243 };
1244
1245 ahb@80080000 {
1246 compatible = "simple-bus";
1247 #address-cells = <1>;
1248 #size-cells = <1>;
1249 reg = <0x80080000 0x80000>;
1250 ranges;
1251
1252 usb0: usb@80080000 {
1253 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1254 reg = <0x80080000 0x10000>;
1255 interrupts = <93>;
1256 clocks = <&clks 60>;
1257 fsl,usbphy = <&usbphy0>;
1258 status = "disabled";
1259 };
1260
1261 usb1: usb@80090000 {
1262 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1263 reg = <0x80090000 0x10000>;
1264 interrupts = <92>;
1265 clocks = <&clks 61>;
1266 fsl,usbphy = <&usbphy1>;
1267 dr_mode = "host";
1268 status = "disabled";
1269 };
1270
1271 dflpt: dflpt@800c0000 {
1272 reg = <0x800c0000 0x10000>;
1273 status = "disabled";
1274 };
1275
1276 mac0: ethernet@800f0000 {
1277 compatible = "fsl,imx28-fec";
1278 reg = <0x800f0000 0x4000>;
1279 interrupts = <101>;
1280 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1281 clock-names = "ipg", "ahb", "enet_out";
1282 status = "disabled";
1283 };
1284
1285 mac1: ethernet@800f4000 {
1286 compatible = "fsl,imx28-fec";
1287 reg = <0x800f4000 0x4000>;
1288 interrupts = <102>;
1289 clocks = <&clks 57>, <&clks 57>;
1290 clock-names = "ipg", "ahb";
1291 status = "disabled";
1292 };
1293
1294 etn_switch: switch@800f8000 {
1295 reg = <0x800f8000 0x8000>;
1296 status = "disabled";
1297 };
1298 };
1299
1300 iio-hwmon {
1301 compatible = "iio-hwmon";
1302 io-channels = <&lradc 8>;
1303 };
1304};