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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
15 */
16
17#include "exynos4-cpu-thermal.dtsi"
18#include "exynos-syscon-restart.dtsi"
19#include <dt-bindings/clock/exynos3250.h>
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21#include <dt-bindings/interrupt-controller/irq.h>
22
23/ {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 mshc0 = &mshc_0;
33 mshc1 = &mshc_1;
34 mshc2 = &mshc_2;
35 spi0 = &spi_0;
36 spi1 = &spi_1;
37 i2c0 = &i2c_0;
38 i2c1 = &i2c_1;
39 i2c2 = &i2c_2;
40 i2c3 = &i2c_3;
41 i2c4 = &i2c_4;
42 i2c5 = &i2c_5;
43 i2c6 = &i2c_6;
44 i2c7 = &i2c_7;
45 serial0 = &serial_0;
46 serial1 = &serial_1;
47 serial2 = &serial_2;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a7";
57 reg = <0>;
58 clock-frequency = <1000000000>;
59 clocks = <&cmu CLK_ARM_CLK>;
60 clock-names = "cpu";
61 #cooling-cells = <2>;
62
63 operating-points = <
64 1000000 1150000
65 900000 1112500
66 800000 1075000
67 700000 1037500
68 600000 1000000
69 500000 962500
70 400000 925000
71 300000 887500
72 200000 850000
73 100000 850000
74 >;
75 };
76
77 cpu1: cpu@1 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a7";
80 reg = <1>;
81 clock-frequency = <1000000000>;
82 };
83 };
84
85 soc: soc {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90
91 fixed-rate-clocks {
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 xusbxti: clock@0 {
96 compatible = "fixed-clock";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <0>;
100 clock-frequency = <0>;
101 #clock-cells = <0>;
102 clock-output-names = "xusbxti";
103 };
104
105 xxti: clock@1 {
106 compatible = "fixed-clock";
107 reg = <1>;
108 clock-frequency = <0>;
109 #clock-cells = <0>;
110 clock-output-names = "xxti";
111 };
112
113 xtcxo: clock@2 {
114 compatible = "fixed-clock";
115 reg = <2>;
116 clock-frequency = <0>;
117 #clock-cells = <0>;
118 clock-output-names = "xtcxo";
119 };
120 };
121
122 sysram@2020000 {
123 compatible = "mmio-sram";
124 reg = <0x02020000 0x40000>;
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0 0x02020000 0x40000>;
128
129 smp-sysram@0 {
130 compatible = "samsung,exynos4210-sysram";
131 reg = <0x0 0x1000>;
132 };
133
134 smp-sysram@3f000 {
135 compatible = "samsung,exynos4210-sysram-ns";
136 reg = <0x3f000 0x1000>;
137 };
138 };
139
140 chipid@10000000 {
141 compatible = "samsung,exynos4210-chipid";
142 reg = <0x10000000 0x100>;
143 };
144
145 sys_reg: syscon@10010000 {
146 compatible = "samsung,exynos3-sysreg", "syscon";
147 reg = <0x10010000 0x400>;
148 };
149
150 pmu_system_controller: system-controller@10020000 {
151 compatible = "samsung,exynos3250-pmu", "syscon";
152 reg = <0x10020000 0x4000>;
153 interrupt-controller;
154 #interrupt-cells = <3>;
155 interrupt-parent = <&gic>;
156 };
157
158 mipi_phy: video-phy {
159 compatible = "samsung,s5pv210-mipi-video-phy";
160 #phy-cells = <1>;
161 syscon = <&pmu_system_controller>;
162 };
163
164 pd_cam: power-domain@10023c00 {
165 compatible = "samsung,exynos4210-pd";
166 reg = <0x10023C00 0x20>;
167 #power-domain-cells = <0>;
168 label = "CAM";
169 };
170
171 pd_mfc: power-domain@10023c40 {
172 compatible = "samsung,exynos4210-pd";
173 reg = <0x10023C40 0x20>;
174 #power-domain-cells = <0>;
175 label = "MFC";
176 };
177
178 pd_g3d: power-domain@10023c60 {
179 compatible = "samsung,exynos4210-pd";
180 reg = <0x10023C60 0x20>;
181 #power-domain-cells = <0>;
182 label = "G3D";
183 };
184
185 pd_lcd0: power-domain@10023c80 {
186 compatible = "samsung,exynos4210-pd";
187 reg = <0x10023C80 0x20>;
188 #power-domain-cells = <0>;
189 label = "LCD0";
190 };
191
192 pd_isp: power-domain@10023ca0 {
193 compatible = "samsung,exynos4210-pd";
194 reg = <0x10023CA0 0x20>;
195 #power-domain-cells = <0>;
196 label = "ISP";
197 };
198
199 cmu: clock-controller@10030000 {
200 compatible = "samsung,exynos3250-cmu";
201 reg = <0x10030000 0x20000>;
202 #clock-cells = <1>;
203 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
204 <&cmu CLK_MOUT_ACLK_266_SUB>;
205 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
206 <&cmu CLK_FIN_PLL>;
207 };
208
209 cmu_dmc: clock-controller@105c0000 {
210 compatible = "samsung,exynos3250-cmu-dmc";
211 reg = <0x105C0000 0x2000>;
212 #clock-cells = <1>;
213 };
214
215 rtc: rtc@10070000 {
216 compatible = "samsung,s3c6410-rtc";
217 reg = <0x10070000 0x100>;
218 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
220 interrupt-parent = <&pmu_system_controller>;
221 status = "disabled";
222 };
223
224 tmu: tmu@100c0000 {
225 compatible = "samsung,exynos3250-tmu";
226 reg = <0x100C0000 0x100>;
227 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cmu CLK_TMU_APBIF>;
229 clock-names = "tmu_apbif";
230 #include "exynos4412-tmu-sensor-conf.dtsi"
231 status = "disabled";
232 };
233
234 gic: interrupt-controller@10481000 {
235 compatible = "arm,cortex-a15-gic";
236 #interrupt-cells = <3>;
237 interrupt-controller;
238 reg = <0x10481000 0x1000>,
239 <0x10482000 0x2000>,
240 <0x10484000 0x2000>,
241 <0x10486000 0x2000>;
242 interrupts = <GIC_PPI 9
243 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
244 };
245
246 mct@10050000 {
247 compatible = "samsung,exynos4210-mct";
248 reg = <0x10050000 0x800>;
249 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
258 clock-names = "fin_pll", "mct";
259 };
260
261 pinctrl_1: pinctrl@11000000 {
262 compatible = "samsung,exynos3250-pinctrl";
263 reg = <0x11000000 0x1000>;
264 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
265
266 wakeup-interrupt-controller {
267 compatible = "samsung,exynos4210-wakeup-eint";
268 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
269 };
270 };
271
272 pinctrl_0: pinctrl@11400000 {
273 compatible = "samsung,exynos3250-pinctrl";
274 reg = <0x11400000 0x1000>;
275 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
276 };
277
278 jpeg: codec@11830000 {
279 compatible = "samsung,exynos3250-jpeg";
280 reg = <0x11830000 0x1000>;
281 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
283 clock-names = "jpeg", "sclk";
284 power-domains = <&pd_cam>;
285 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
286 assigned-clock-rates = <0>, <150000000>;
287 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
288 iommus = <&sysmmu_jpeg>;
289 status = "disabled";
290 };
291
292 sysmmu_jpeg: sysmmu@11a60000 {
293 compatible = "samsung,exynos-sysmmu";
294 reg = <0x11a60000 0x1000>;
295 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
297 clock-names = "sysmmu", "master";
298 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
299 power-domains = <&pd_cam>;
300 #iommu-cells = <0>;
301 };
302
303 fimd: fimd@11c00000 {
304 compatible = "samsung,exynos3250-fimd";
305 reg = <0x11c00000 0x30000>;
306 interrupt-names = "fifo", "vsync", "lcd_sys";
307 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
311 clock-names = "sclk_fimd", "fimd";
312 power-domains = <&pd_lcd0>;
313 iommus = <&sysmmu_fimd0>;
314 samsung,sysreg = <&sys_reg>;
315 status = "disabled";
316 };
317
318 dsi_0: dsi@11c80000 {
319 compatible = "samsung,exynos3250-mipi-dsi";
320 reg = <0x11C80000 0x10000>;
321 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
322 samsung,phy-type = <0>;
323 power-domains = <&pd_lcd0>;
324 phys = <&mipi_phy 1>;
325 phy-names = "dsim";
326 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
327 clock-names = "bus_clk", "pll_clk";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 status = "disabled";
331 };
332
333 sysmmu_fimd0: sysmmu@11e20000 {
334 compatible = "samsung,exynos-sysmmu";
335 reg = <0x11e20000 0x1000>;
336 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "sysmmu", "master";
339 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
340 power-domains = <&pd_lcd0>;
341 #iommu-cells = <0>;
342 };
343
344 hsotg: hsotg@12480000 {
345 compatible = "snps,dwc2";
346 reg = <0x12480000 0x20000>;
347 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cmu CLK_USBOTG>;
349 clock-names = "otg";
350 phys = <&exynos_usbphy 0>;
351 phy-names = "usb2-phy";
352 status = "disabled";
353 };
354
355 mshc_0: mshc@12510000 {
356 compatible = "samsung,exynos5420-dw-mshc";
357 reg = <0x12510000 0x1000>;
358 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
360 clock-names = "biu", "ciu";
361 fifo-depth = <0x80>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 status = "disabled";
365 };
366
367 mshc_1: mshc@12520000 {
368 compatible = "samsung,exynos5420-dw-mshc";
369 reg = <0x12520000 0x1000>;
370 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
372 clock-names = "biu", "ciu";
373 fifo-depth = <0x80>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 status = "disabled";
377 };
378
379 mshc_2: mshc@12530000 {
380 compatible = "samsung,exynos5250-dw-mshc";
381 reg = <0x12530000 0x1000>;
382 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
384 clock-names = "biu", "ciu";
385 fifo-depth = <0x80>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
391 exynos_usbphy: exynos-usbphy@125b0000 {
392 compatible = "samsung,exynos3250-usb2-phy";
393 reg = <0x125B0000 0x100>;
394 samsung,pmureg-phandle = <&pmu_system_controller>;
395 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
396 clock-names = "phy", "ref";
397 #phy-cells = <1>;
398 status = "disabled";
399 };
400
401 amba {
402 compatible = "simple-bus";
403 #address-cells = <1>;
404 #size-cells = <1>;
405 ranges;
406
407 pdma0: pdma@12680000 {
408 compatible = "arm,pl330", "arm,primecell";
409 reg = <0x12680000 0x1000>;
410 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&cmu CLK_PDMA0>;
412 clock-names = "apb_pclk";
413 #dma-cells = <1>;
414 #dma-channels = <8>;
415 #dma-requests = <32>;
416 };
417
418 pdma1: pdma@12690000 {
419 compatible = "arm,pl330", "arm,primecell";
420 reg = <0x12690000 0x1000>;
421 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cmu CLK_PDMA1>;
423 clock-names = "apb_pclk";
424 #dma-cells = <1>;
425 #dma-channels = <8>;
426 #dma-requests = <32>;
427 };
428 };
429
430 adc: adc@126c0000 {
431 compatible = "samsung,exynos3250-adc",
432 "samsung,exynos-adc-v2";
433 reg = <0x126C0000 0x100>;
434 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
435 clock-names = "adc", "sclk";
436 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
437 #io-channel-cells = <1>;
438 io-channel-ranges;
439 samsung,syscon-phandle = <&pmu_system_controller>;
440 status = "disabled";
441 };
442
443 mfc: codec@13400000 {
444 compatible = "samsung,mfc-v7";
445 reg = <0x13400000 0x10000>;
446 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
447 clock-names = "mfc", "sclk_mfc";
448 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
449 power-domains = <&pd_mfc>;
450 iommus = <&sysmmu_mfc>;
451 };
452
453 sysmmu_mfc: sysmmu@13620000 {
454 compatible = "samsung,exynos-sysmmu";
455 reg = <0x13620000 0x1000>;
456 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
458 clock-names = "sysmmu", "master";
459 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
460 power-domains = <&pd_mfc>;
461 #iommu-cells = <0>;
462 };
463
464 serial_0: serial@13800000 {
465 compatible = "samsung,exynos4210-uart";
466 reg = <0x13800000 0x100>;
467 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
469 clock-names = "uart", "clk_uart_baud0";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart0_data &uart0_fctl>;
472 status = "disabled";
473 };
474
475 serial_1: serial@13810000 {
476 compatible = "samsung,exynos4210-uart";
477 reg = <0x13810000 0x100>;
478 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
480 clock-names = "uart", "clk_uart_baud0";
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart1_data>;
483 status = "disabled";
484 };
485
486 serial_2: serial@13820000 {
487 compatible = "samsung,exynos4210-uart";
488 reg = <0x13820000 0x100>;
489 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
491 clock-names = "uart", "clk_uart_baud0";
492 pinctrl-names = "default";
493 pinctrl-0 = <&uart2_data>;
494 status = "disabled";
495 };
496
497 i2c_0: i2c@13860000 {
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "samsung,s3c2440-i2c";
501 reg = <0x13860000 0x100>;
502 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cmu CLK_I2C0>;
504 clock-names = "i2c";
505 pinctrl-names = "default";
506 pinctrl-0 = <&i2c0_bus>;
507 status = "disabled";
508 };
509
510 i2c_1: i2c@13870000 {
511 #address-cells = <1>;
512 #size-cells = <0>;
513 compatible = "samsung,s3c2440-i2c";
514 reg = <0x13870000 0x100>;
515 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cmu CLK_I2C1>;
517 clock-names = "i2c";
518 pinctrl-names = "default";
519 pinctrl-0 = <&i2c1_bus>;
520 status = "disabled";
521 };
522
523 i2c_2: i2c@13880000 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "samsung,s3c2440-i2c";
527 reg = <0x13880000 0x100>;
528 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&cmu CLK_I2C2>;
530 clock-names = "i2c";
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c2_bus>;
533 status = "disabled";
534 };
535
536 i2c_3: i2c@13890000 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "samsung,s3c2440-i2c";
540 reg = <0x13890000 0x100>;
541 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cmu CLK_I2C3>;
543 clock-names = "i2c";
544 pinctrl-names = "default";
545 pinctrl-0 = <&i2c3_bus>;
546 status = "disabled";
547 };
548
549 i2c_4: i2c@138a0000 {
550 #address-cells = <1>;
551 #size-cells = <0>;
552 compatible = "samsung,s3c2440-i2c";
553 reg = <0x138A0000 0x100>;
554 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&cmu CLK_I2C4>;
556 clock-names = "i2c";
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2c4_bus>;
559 status = "disabled";
560 };
561
562 i2c_5: i2c@138b0000 {
563 #address-cells = <1>;
564 #size-cells = <0>;
565 compatible = "samsung,s3c2440-i2c";
566 reg = <0x138B0000 0x100>;
567 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cmu CLK_I2C5>;
569 clock-names = "i2c";
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2c5_bus>;
572 status = "disabled";
573 };
574
575 i2c_6: i2c@138c0000 {
576 #address-cells = <1>;
577 #size-cells = <0>;
578 compatible = "samsung,s3c2440-i2c";
579 reg = <0x138C0000 0x100>;
580 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cmu CLK_I2C6>;
582 clock-names = "i2c";
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c6_bus>;
585 status = "disabled";
586 };
587
588 i2c_7: i2c@138d0000 {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 compatible = "samsung,s3c2440-i2c";
592 reg = <0x138D0000 0x100>;
593 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&cmu CLK_I2C7>;
595 clock-names = "i2c";
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c7_bus>;
598 status = "disabled";
599 };
600
601 spi_0: spi@13920000 {
602 compatible = "samsung,exynos4210-spi";
603 reg = <0x13920000 0x100>;
604 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
605 dmas = <&pdma0 7>, <&pdma0 6>;
606 dma-names = "tx", "rx";
607 #address-cells = <1>;
608 #size-cells = <0>;
609 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
610 clock-names = "spi", "spi_busclk0";
611 samsung,spi-src-clk = <0>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&spi0_bus>;
614 status = "disabled";
615 };
616
617 spi_1: spi@13930000 {
618 compatible = "samsung,exynos4210-spi";
619 reg = <0x13930000 0x100>;
620 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
621 dmas = <&pdma1 7>, <&pdma1 6>;
622 dma-names = "tx", "rx";
623 #address-cells = <1>;
624 #size-cells = <0>;
625 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
626 clock-names = "spi", "spi_busclk0";
627 samsung,spi-src-clk = <0>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&spi1_bus>;
630 status = "disabled";
631 };
632
633 i2s2: i2s@13970000 {
634 compatible = "samsung,s3c6410-i2s";
635 reg = <0x13970000 0x100>;
636 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
638 clock-names = "iis", "i2s_opclk0";
639 dmas = <&pdma0 14>, <&pdma0 13>;
640 dma-names = "tx", "rx";
641 pinctrl-0 = <&i2s2_bus>;
642 pinctrl-names = "default";
643 status = "disabled";
644 };
645
646 pwm: pwm@139d0000 {
647 compatible = "samsung,exynos4210-pwm";
648 reg = <0x139D0000 0x1000>;
649 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
654 #pwm-cells = <3>;
655 status = "disabled";
656 };
657
658 pmu {
659 compatible = "arm,cortex-a7-pmu";
660 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
662 };
663
664 ppmu_dmc0: ppmu_dmc0@106a0000 {
665 compatible = "samsung,exynos-ppmu";
666 reg = <0x106a0000 0x2000>;
667 status = "disabled";
668 };
669
670 ppmu_dmc1: ppmu_dmc1@106b0000 {
671 compatible = "samsung,exynos-ppmu";
672 reg = <0x106b0000 0x2000>;
673 status = "disabled";
674 };
675
676 ppmu_cpu: ppmu_cpu@106c0000 {
677 compatible = "samsung,exynos-ppmu";
678 reg = <0x106c0000 0x2000>;
679 status = "disabled";
680 };
681
682 ppmu_rightbus: ppmu_rightbus@112a0000 {
683 compatible = "samsung,exynos-ppmu";
684 reg = <0x112a0000 0x2000>;
685 clocks = <&cmu CLK_PPMURIGHT>;
686 clock-names = "ppmu";
687 status = "disabled";
688 };
689
690 ppmu_leftbus: ppmu_leftbus0@116a0000 {
691 compatible = "samsung,exynos-ppmu";
692 reg = <0x116a0000 0x2000>;
693 clocks = <&cmu CLK_PPMULEFT>;
694 clock-names = "ppmu";
695 status = "disabled";
696 };
697
698 ppmu_camif: ppmu_camif@11ac0000 {
699 compatible = "samsung,exynos-ppmu";
700 reg = <0x11ac0000 0x2000>;
701 clocks = <&cmu CLK_PPMUCAMIF>;
702 clock-names = "ppmu";
703 status = "disabled";
704 };
705
706 ppmu_lcd0: ppmu_lcd0@11e40000 {
707 compatible = "samsung,exynos-ppmu";
708 reg = <0x11e40000 0x2000>;
709 clocks = <&cmu CLK_PPMULCD0>;
710 clock-names = "ppmu";
711 status = "disabled";
712 };
713
714 ppmu_fsys: ppmu_fsys@12630000 {
715 compatible = "samsung,exynos-ppmu";
716 reg = <0x12630000 0x2000>;
717 clocks = <&cmu CLK_PPMUFILE>;
718 clock-names = "ppmu";
719 status = "disabled";
720 };
721
722 ppmu_g3d: ppmu_g3d@13220000 {
723 compatible = "samsung,exynos-ppmu";
724 reg = <0x13220000 0x2000>;
725 clocks = <&cmu CLK_PPMUG3D>;
726 clock-names = "ppmu";
727 status = "disabled";
728 };
729
730 ppmu_mfc: ppmu_mfc@13660000 {
731 compatible = "samsung,exynos-ppmu";
732 reg = <0x13660000 0x2000>;
733 clocks = <&cmu CLK_PPMUMFC_L>;
734 clock-names = "ppmu";
735 status = "disabled";
736 };
737
738 bus_dmc: bus_dmc {
739 compatible = "samsung,exynos-bus";
740 clocks = <&cmu_dmc CLK_DIV_DMC>;
741 clock-names = "bus";
742 operating-points-v2 = <&bus_dmc_opp_table>;
743 status = "disabled";
744 };
745
746 bus_dmc_opp_table: opp_table1 {
747 compatible = "operating-points-v2";
748 opp-shared;
749
750 opp-50000000 {
751 opp-hz = /bits/ 64 <50000000>;
752 opp-microvolt = <800000>;
753 };
754 opp-100000000 {
755 opp-hz = /bits/ 64 <100000000>;
756 opp-microvolt = <800000>;
757 };
758 opp-134000000 {
759 opp-hz = /bits/ 64 <134000000>;
760 opp-microvolt = <800000>;
761 };
762 opp-200000000 {
763 opp-hz = /bits/ 64 <200000000>;
764 opp-microvolt = <825000>;
765 };
766 opp-400000000 {
767 opp-hz = /bits/ 64 <400000000>;
768 opp-microvolt = <875000>;
769 };
770 };
771
772 bus_leftbus: bus_leftbus {
773 compatible = "samsung,exynos-bus";
774 clocks = <&cmu CLK_DIV_GDL>;
775 clock-names = "bus";
776 operating-points-v2 = <&bus_leftbus_opp_table>;
777 status = "disabled";
778 };
779
780 bus_rightbus: bus_rightbus {
781 compatible = "samsung,exynos-bus";
782 clocks = <&cmu CLK_DIV_GDR>;
783 clock-names = "bus";
784 operating-points-v2 = <&bus_leftbus_opp_table>;
785 status = "disabled";
786 };
787
788 bus_lcd0: bus_lcd0 {
789 compatible = "samsung,exynos-bus";
790 clocks = <&cmu CLK_DIV_ACLK_160>;
791 clock-names = "bus";
792 operating-points-v2 = <&bus_leftbus_opp_table>;
793 status = "disabled";
794 };
795
796 bus_fsys: bus_fsys {
797 compatible = "samsung,exynos-bus";
798 clocks = <&cmu CLK_DIV_ACLK_200>;
799 clock-names = "bus";
800 operating-points-v2 = <&bus_leftbus_opp_table>;
801 status = "disabled";
802 };
803
804 bus_mcuisp: bus_mcuisp {
805 compatible = "samsung,exynos-bus";
806 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
807 clock-names = "bus";
808 operating-points-v2 = <&bus_mcuisp_opp_table>;
809 status = "disabled";
810 };
811
812 bus_isp: bus_isp {
813 compatible = "samsung,exynos-bus";
814 clocks = <&cmu CLK_DIV_ACLK_266>;
815 clock-names = "bus";
816 operating-points-v2 = <&bus_isp_opp_table>;
817 status = "disabled";
818 };
819
820 bus_peril: bus_peril {
821 compatible = "samsung,exynos-bus";
822 clocks = <&cmu CLK_DIV_ACLK_100>;
823 clock-names = "bus";
824 operating-points-v2 = <&bus_peril_opp_table>;
825 status = "disabled";
826 };
827
828 bus_mfc: bus_mfc {
829 compatible = "samsung,exynos-bus";
830 clocks = <&cmu CLK_SCLK_MFC>;
831 clock-names = "bus";
832 operating-points-v2 = <&bus_leftbus_opp_table>;
833 status = "disabled";
834 };
835
836 bus_leftbus_opp_table: opp_table2 {
837 compatible = "operating-points-v2";
838 opp-shared;
839
840 opp-50000000 {
841 opp-hz = /bits/ 64 <50000000>;
842 opp-microvolt = <900000>;
843 };
844 opp-80000000 {
845 opp-hz = /bits/ 64 <80000000>;
846 opp-microvolt = <900000>;
847 };
848 opp-100000000 {
849 opp-hz = /bits/ 64 <100000000>;
850 opp-microvolt = <1000000>;
851 };
852 opp-134000000 {
853 opp-hz = /bits/ 64 <134000000>;
854 opp-microvolt = <1000000>;
855 };
856 opp-200000000 {
857 opp-hz = /bits/ 64 <200000000>;
858 opp-microvolt = <1000000>;
859 };
860 };
861
862 bus_mcuisp_opp_table: opp_table3 {
863 compatible = "operating-points-v2";
864 opp-shared;
865
866 opp-50000000 {
867 opp-hz = /bits/ 64 <50000000>;
868 };
869 opp-80000000 {
870 opp-hz = /bits/ 64 <80000000>;
871 };
872 opp-100000000 {
873 opp-hz = /bits/ 64 <100000000>;
874 };
875 opp-200000000 {
876 opp-hz = /bits/ 64 <200000000>;
877 };
878 opp-400000000 {
879 opp-hz = /bits/ 64 <400000000>;
880 };
881 };
882
883 bus_isp_opp_table: opp_table4 {
884 compatible = "operating-points-v2";
885 opp-shared;
886
887 opp-50000000 {
888 opp-hz = /bits/ 64 <50000000>;
889 };
890 opp-80000000 {
891 opp-hz = /bits/ 64 <80000000>;
892 };
893 opp-100000000 {
894 opp-hz = /bits/ 64 <100000000>;
895 };
896 opp-200000000 {
897 opp-hz = /bits/ 64 <200000000>;
898 };
899 opp-300000000 {
900 opp-hz = /bits/ 64 <300000000>;
901 };
902 };
903
904 bus_peril_opp_table: opp_table5 {
905 compatible = "operating-points-v2";
906 opp-shared;
907
908 opp-50000000 {
909 opp-hz = /bits/ 64 <50000000>;
910 };
911 opp-80000000 {
912 opp-hz = /bits/ 64 <80000000>;
913 };
914 opp-100000000 {
915 opp-hz = /bits/ 64 <100000000>;
916 };
917 };
918 };
919};
920
921#include "exynos3250-pinctrl.dtsi"
1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include "exynos4-cpu-thermal.dtsi"
21#include "exynos-syscon-restart.dtsi"
22#include <dt-bindings/clock/exynos3250.h>
23#include <dt-bindings/interrupt-controller/arm-gic.h>
24#include <dt-bindings/interrupt-controller/irq.h>
25
26/ {
27 compatible = "samsung,exynos3250";
28 interrupt-parent = <&gic>;
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 aliases {
33 pinctrl0 = &pinctrl_0;
34 pinctrl1 = &pinctrl_1;
35 mshc0 = &mshc_0;
36 mshc1 = &mshc_1;
37 mshc2 = &mshc_2;
38 spi0 = &spi_0;
39 spi1 = &spi_1;
40 i2c0 = &i2c_0;
41 i2c1 = &i2c_1;
42 i2c2 = &i2c_2;
43 i2c3 = &i2c_3;
44 i2c4 = &i2c_4;
45 i2c5 = &i2c_5;
46 i2c6 = &i2c_6;
47 i2c7 = &i2c_7;
48 serial0 = &serial_0;
49 serial1 = &serial_1;
50 serial2 = &serial_2;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 cpu0: cpu@0 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <0>;
61 clock-frequency = <1000000000>;
62 clocks = <&cmu CLK_ARM_CLK>;
63 clock-names = "cpu";
64 #cooling-cells = <2>;
65
66 operating-points = <
67 1000000 1150000
68 900000 1112500
69 800000 1075000
70 700000 1037500
71 600000 1000000
72 500000 962500
73 400000 925000
74 300000 887500
75 200000 850000
76 100000 850000
77 >;
78 };
79
80 cpu1: cpu@1 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a7";
83 reg = <1>;
84 clock-frequency = <1000000000>;
85 };
86 };
87
88 soc: soc {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 fixed-rate-clocks {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 xusbxti: clock@0 {
99 compatible = "fixed-clock";
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0>;
103 clock-frequency = <0>;
104 #clock-cells = <0>;
105 clock-output-names = "xusbxti";
106 };
107
108 xxti: clock@1 {
109 compatible = "fixed-clock";
110 reg = <1>;
111 clock-frequency = <0>;
112 #clock-cells = <0>;
113 clock-output-names = "xxti";
114 };
115
116 xtcxo: clock@2 {
117 compatible = "fixed-clock";
118 reg = <2>;
119 clock-frequency = <0>;
120 #clock-cells = <0>;
121 clock-output-names = "xtcxo";
122 };
123 };
124
125 sysram@02020000 {
126 compatible = "mmio-sram";
127 reg = <0x02020000 0x40000>;
128 #address-cells = <1>;
129 #size-cells = <1>;
130 ranges = <0 0x02020000 0x40000>;
131
132 smp-sysram@0 {
133 compatible = "samsung,exynos4210-sysram";
134 reg = <0x0 0x1000>;
135 };
136
137 smp-sysram@3f000 {
138 compatible = "samsung,exynos4210-sysram-ns";
139 reg = <0x3f000 0x1000>;
140 };
141 };
142
143 chipid@10000000 {
144 compatible = "samsung,exynos4210-chipid";
145 reg = <0x10000000 0x100>;
146 };
147
148 sys_reg: syscon@10010000 {
149 compatible = "samsung,exynos3-sysreg", "syscon";
150 reg = <0x10010000 0x400>;
151 };
152
153 pmu_system_controller: system-controller@10020000 {
154 compatible = "samsung,exynos3250-pmu", "syscon";
155 reg = <0x10020000 0x4000>;
156 interrupt-controller;
157 #interrupt-cells = <3>;
158 interrupt-parent = <&gic>;
159 };
160
161 mipi_phy: video-phy {
162 compatible = "samsung,s5pv210-mipi-video-phy";
163 #phy-cells = <1>;
164 syscon = <&pmu_system_controller>;
165 };
166
167 pd_cam: cam-power-domain@10023C00 {
168 compatible = "samsung,exynos4210-pd";
169 reg = <0x10023C00 0x20>;
170 #power-domain-cells = <0>;
171 };
172
173 pd_mfc: mfc-power-domain@10023C40 {
174 compatible = "samsung,exynos4210-pd";
175 reg = <0x10023C40 0x20>;
176 #power-domain-cells = <0>;
177 };
178
179 pd_g3d: g3d-power-domain@10023C60 {
180 compatible = "samsung,exynos4210-pd";
181 reg = <0x10023C60 0x20>;
182 #power-domain-cells = <0>;
183 };
184
185 pd_lcd0: lcd0-power-domain@10023C80 {
186 compatible = "samsung,exynos4210-pd";
187 reg = <0x10023C80 0x20>;
188 #power-domain-cells = <0>;
189 };
190
191 pd_isp: isp-power-domain@10023CA0 {
192 compatible = "samsung,exynos4210-pd";
193 reg = <0x10023CA0 0x20>;
194 #power-domain-cells = <0>;
195 };
196
197 cmu: clock-controller@10030000 {
198 compatible = "samsung,exynos3250-cmu";
199 reg = <0x10030000 0x20000>;
200 #clock-cells = <1>;
201 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
202 <&cmu CLK_MOUT_ACLK_266_SUB>;
203 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
204 <&cmu CLK_FIN_PLL>;
205 };
206
207 cmu_dmc: clock-controller@105C0000 {
208 compatible = "samsung,exynos3250-cmu-dmc";
209 reg = <0x105C0000 0x2000>;
210 #clock-cells = <1>;
211 };
212
213 rtc: rtc@10070000 {
214 compatible = "samsung,s3c6410-rtc";
215 reg = <0x10070000 0x100>;
216 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
218 interrupt-parent = <&pmu_system_controller>;
219 status = "disabled";
220 };
221
222 tmu: tmu@100C0000 {
223 compatible = "samsung,exynos3250-tmu";
224 reg = <0x100C0000 0x100>;
225 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&cmu CLK_TMU_APBIF>;
227 clock-names = "tmu_apbif";
228 #include "exynos4412-tmu-sensor-conf.dtsi"
229 status = "disabled";
230 };
231
232 gic: interrupt-controller@10481000 {
233 compatible = "arm,cortex-a15-gic";
234 #interrupt-cells = <3>;
235 interrupt-controller;
236 reg = <0x10481000 0x1000>,
237 <0x10482000 0x1000>,
238 <0x10484000 0x2000>,
239 <0x10486000 0x2000>;
240 interrupts = <GIC_PPI 9
241 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
242 };
243
244 mct@10050000 {
245 compatible = "samsung,exynos4210-mct";
246 reg = <0x10050000 0x800>;
247 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
256 clock-names = "fin_pll", "mct";
257 };
258
259 pinctrl_1: pinctrl@11000000 {
260 compatible = "samsung,exynos3250-pinctrl";
261 reg = <0x11000000 0x1000>;
262 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
263
264 wakeup-interrupt-controller {
265 compatible = "samsung,exynos4210-wakeup-eint";
266 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
267 };
268 };
269
270 pinctrl_0: pinctrl@11400000 {
271 compatible = "samsung,exynos3250-pinctrl";
272 reg = <0x11400000 0x1000>;
273 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
274 };
275
276 jpeg: codec@11830000 {
277 compatible = "samsung,exynos3250-jpeg";
278 reg = <0x11830000 0x1000>;
279 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
281 clock-names = "jpeg", "sclk";
282 power-domains = <&pd_cam>;
283 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
284 assigned-clock-rates = <0>, <150000000>;
285 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
286 iommus = <&sysmmu_jpeg>;
287 status = "disabled";
288 };
289
290 sysmmu_jpeg: sysmmu@11A60000 {
291 compatible = "samsung,exynos-sysmmu";
292 reg = <0x11a60000 0x1000>;
293 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
295 clock-names = "sysmmu", "master";
296 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
297 power-domains = <&pd_cam>;
298 #iommu-cells = <0>;
299 };
300
301 fimd: fimd@11c00000 {
302 compatible = "samsung,exynos3250-fimd";
303 reg = <0x11c00000 0x30000>;
304 interrupt-names = "fifo", "vsync", "lcd_sys";
305 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
309 clock-names = "sclk_fimd", "fimd";
310 power-domains = <&pd_lcd0>;
311 iommus = <&sysmmu_fimd0>;
312 samsung,sysreg = <&sys_reg>;
313 status = "disabled";
314 };
315
316 dsi_0: dsi@11C80000 {
317 compatible = "samsung,exynos3250-mipi-dsi";
318 reg = <0x11C80000 0x10000>;
319 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
320 samsung,phy-type = <0>;
321 power-domains = <&pd_lcd0>;
322 phys = <&mipi_phy 1>;
323 phy-names = "dsim";
324 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
325 clock-names = "bus_clk", "pll_clk";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 status = "disabled";
329 };
330
331 sysmmu_fimd0: sysmmu@11E20000 {
332 compatible = "samsung,exynos-sysmmu";
333 reg = <0x11e20000 0x1000>;
334 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
336 clock-names = "sysmmu", "master";
337 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
338 power-domains = <&pd_lcd0>;
339 #iommu-cells = <0>;
340 };
341
342 hsotg: hsotg@12480000 {
343 compatible = "snps,dwc2";
344 reg = <0x12480000 0x20000>;
345 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&cmu CLK_USBOTG>;
347 clock-names = "otg";
348 phys = <&exynos_usbphy 0>;
349 phy-names = "usb2-phy";
350 status = "disabled";
351 };
352
353 mshc_0: mshc@12510000 {
354 compatible = "samsung,exynos5420-dw-mshc";
355 reg = <0x12510000 0x1000>;
356 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
358 clock-names = "biu", "ciu";
359 fifo-depth = <0x80>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 status = "disabled";
363 };
364
365 mshc_1: mshc@12520000 {
366 compatible = "samsung,exynos5420-dw-mshc";
367 reg = <0x12520000 0x1000>;
368 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
370 clock-names = "biu", "ciu";
371 fifo-depth = <0x80>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
376
377 mshc_2: mshc@12530000 {
378 compatible = "samsung,exynos5250-dw-mshc";
379 reg = <0x12530000 0x1000>;
380 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
382 clock-names = "biu", "ciu";
383 fifo-depth = <0x80>;
384 #address-cells = <1>;
385 #size-cells = <0>;
386 status = "disabled";
387 };
388
389 exynos_usbphy: exynos-usbphy@125B0000 {
390 compatible = "samsung,exynos3250-usb2-phy";
391 reg = <0x125B0000 0x100>;
392 samsung,pmureg-phandle = <&pmu_system_controller>;
393 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
394 clock-names = "phy", "ref";
395 #phy-cells = <1>;
396 status = "disabled";
397 };
398
399 amba {
400 compatible = "simple-bus";
401 #address-cells = <1>;
402 #size-cells = <1>;
403 ranges;
404
405 pdma0: pdma@12680000 {
406 compatible = "arm,pl330", "arm,primecell";
407 reg = <0x12680000 0x1000>;
408 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&cmu CLK_PDMA0>;
410 clock-names = "apb_pclk";
411 #dma-cells = <1>;
412 #dma-channels = <8>;
413 #dma-requests = <32>;
414 };
415
416 pdma1: pdma@12690000 {
417 compatible = "arm,pl330", "arm,primecell";
418 reg = <0x12690000 0x1000>;
419 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cmu CLK_PDMA1>;
421 clock-names = "apb_pclk";
422 #dma-cells = <1>;
423 #dma-channels = <8>;
424 #dma-requests = <32>;
425 };
426 };
427
428 adc: adc@126C0000 {
429 compatible = "samsung,exynos3250-adc",
430 "samsung,exynos-adc-v2";
431 reg = <0x126C0000 0x100>;
432 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
433 clock-names = "adc", "sclk";
434 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
435 #io-channel-cells = <1>;
436 io-channel-ranges;
437 samsung,syscon-phandle = <&pmu_system_controller>;
438 status = "disabled";
439 };
440
441 mfc: codec@13400000 {
442 compatible = "samsung,mfc-v7";
443 reg = <0x13400000 0x10000>;
444 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
445 clock-names = "mfc", "sclk_mfc";
446 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
447 power-domains = <&pd_mfc>;
448 iommus = <&sysmmu_mfc>;
449 };
450
451 sysmmu_mfc: sysmmu@13620000 {
452 compatible = "samsung,exynos-sysmmu";
453 reg = <0x13620000 0x1000>;
454 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
456 clock-names = "sysmmu", "master";
457 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
458 power-domains = <&pd_mfc>;
459 #iommu-cells = <0>;
460 };
461
462 serial_0: serial@13800000 {
463 compatible = "samsung,exynos4210-uart";
464 reg = <0x13800000 0x100>;
465 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
467 clock-names = "uart", "clk_uart_baud0";
468 pinctrl-names = "default";
469 pinctrl-0 = <&uart0_data &uart0_fctl>;
470 status = "disabled";
471 };
472
473 serial_1: serial@13810000 {
474 compatible = "samsung,exynos4210-uart";
475 reg = <0x13810000 0x100>;
476 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
478 clock-names = "uart", "clk_uart_baud0";
479 pinctrl-names = "default";
480 pinctrl-0 = <&uart1_data>;
481 status = "disabled";
482 };
483
484 serial_2: serial@13820000 {
485 compatible = "samsung,exynos4210-uart";
486 reg = <0x13820000 0x100>;
487 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
489 clock-names = "uart", "clk_uart_baud0";
490 pinctrl-names = "default";
491 pinctrl-0 = <&uart2_data>;
492 status = "disabled";
493 };
494
495 i2c_0: i2c@13860000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "samsung,s3c2440-i2c";
499 reg = <0x13860000 0x100>;
500 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cmu CLK_I2C0>;
502 clock-names = "i2c";
503 pinctrl-names = "default";
504 pinctrl-0 = <&i2c0_bus>;
505 status = "disabled";
506 };
507
508 i2c_1: i2c@13870000 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 compatible = "samsung,s3c2440-i2c";
512 reg = <0x13870000 0x100>;
513 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&cmu CLK_I2C1>;
515 clock-names = "i2c";
516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c1_bus>;
518 status = "disabled";
519 };
520
521 i2c_2: i2c@13880000 {
522 #address-cells = <1>;
523 #size-cells = <0>;
524 compatible = "samsung,s3c2440-i2c";
525 reg = <0x13880000 0x100>;
526 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cmu CLK_I2C2>;
528 clock-names = "i2c";
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2c2_bus>;
531 status = "disabled";
532 };
533
534 i2c_3: i2c@13890000 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 compatible = "samsung,s3c2440-i2c";
538 reg = <0x13890000 0x100>;
539 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cmu CLK_I2C3>;
541 clock-names = "i2c";
542 pinctrl-names = "default";
543 pinctrl-0 = <&i2c3_bus>;
544 status = "disabled";
545 };
546
547 i2c_4: i2c@138A0000 {
548 #address-cells = <1>;
549 #size-cells = <0>;
550 compatible = "samsung,s3c2440-i2c";
551 reg = <0x138A0000 0x100>;
552 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cmu CLK_I2C4>;
554 clock-names = "i2c";
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c4_bus>;
557 status = "disabled";
558 };
559
560 i2c_5: i2c@138B0000 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "samsung,s3c2440-i2c";
564 reg = <0x138B0000 0x100>;
565 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cmu CLK_I2C5>;
567 clock-names = "i2c";
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2c5_bus>;
570 status = "disabled";
571 };
572
573 i2c_6: i2c@138C0000 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "samsung,s3c2440-i2c";
577 reg = <0x138C0000 0x100>;
578 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&cmu CLK_I2C6>;
580 clock-names = "i2c";
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c6_bus>;
583 status = "disabled";
584 };
585
586 i2c_7: i2c@138D0000 {
587 #address-cells = <1>;
588 #size-cells = <0>;
589 compatible = "samsung,s3c2440-i2c";
590 reg = <0x138D0000 0x100>;
591 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cmu CLK_I2C7>;
593 clock-names = "i2c";
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c7_bus>;
596 status = "disabled";
597 };
598
599 spi_0: spi@13920000 {
600 compatible = "samsung,exynos4210-spi";
601 reg = <0x13920000 0x100>;
602 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
603 dmas = <&pdma0 7>, <&pdma0 6>;
604 dma-names = "tx", "rx";
605 #address-cells = <1>;
606 #size-cells = <0>;
607 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
608 clock-names = "spi", "spi_busclk0";
609 samsung,spi-src-clk = <0>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&spi0_bus>;
612 status = "disabled";
613 };
614
615 spi_1: spi@13930000 {
616 compatible = "samsung,exynos4210-spi";
617 reg = <0x13930000 0x100>;
618 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
619 dmas = <&pdma1 7>, <&pdma1 6>;
620 dma-names = "tx", "rx";
621 #address-cells = <1>;
622 #size-cells = <0>;
623 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
624 clock-names = "spi", "spi_busclk0";
625 samsung,spi-src-clk = <0>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&spi1_bus>;
628 status = "disabled";
629 };
630
631 i2s2: i2s@13970000 {
632 compatible = "samsung,s3c6410-i2s";
633 reg = <0x13970000 0x100>;
634 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
636 clock-names = "iis", "i2s_opclk0";
637 dmas = <&pdma0 14>, <&pdma0 13>;
638 dma-names = "tx", "rx";
639 pinctrl-0 = <&i2s2_bus>;
640 pinctrl-names = "default";
641 status = "disabled";
642 };
643
644 pwm: pwm@139D0000 {
645 compatible = "samsung,exynos4210-pwm";
646 reg = <0x139D0000 0x1000>;
647 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
652 #pwm-cells = <3>;
653 status = "disabled";
654 };
655
656 pmu {
657 compatible = "arm,cortex-a7-pmu";
658 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
660 };
661
662 ppmu_dmc0: ppmu_dmc0@106a0000 {
663 compatible = "samsung,exynos-ppmu";
664 reg = <0x106a0000 0x2000>;
665 status = "disabled";
666 };
667
668 ppmu_dmc1: ppmu_dmc1@106b0000 {
669 compatible = "samsung,exynos-ppmu";
670 reg = <0x106b0000 0x2000>;
671 status = "disabled";
672 };
673
674 ppmu_cpu: ppmu_cpu@106c0000 {
675 compatible = "samsung,exynos-ppmu";
676 reg = <0x106c0000 0x2000>;
677 status = "disabled";
678 };
679
680 ppmu_rightbus: ppmu_rightbus@112a0000 {
681 compatible = "samsung,exynos-ppmu";
682 reg = <0x112a0000 0x2000>;
683 clocks = <&cmu CLK_PPMURIGHT>;
684 clock-names = "ppmu";
685 status = "disabled";
686 };
687
688 ppmu_leftbus: ppmu_leftbus0@116a0000 {
689 compatible = "samsung,exynos-ppmu";
690 reg = <0x116a0000 0x2000>;
691 clocks = <&cmu CLK_PPMULEFT>;
692 clock-names = "ppmu";
693 status = "disabled";
694 };
695
696 ppmu_camif: ppmu_camif@11ac0000 {
697 compatible = "samsung,exynos-ppmu";
698 reg = <0x11ac0000 0x2000>;
699 clocks = <&cmu CLK_PPMUCAMIF>;
700 clock-names = "ppmu";
701 status = "disabled";
702 };
703
704 ppmu_lcd0: ppmu_lcd0@11e40000 {
705 compatible = "samsung,exynos-ppmu";
706 reg = <0x11e40000 0x2000>;
707 clocks = <&cmu CLK_PPMULCD0>;
708 clock-names = "ppmu";
709 status = "disabled";
710 };
711
712 ppmu_fsys: ppmu_fsys@12630000 {
713 compatible = "samsung,exynos-ppmu";
714 reg = <0x12630000 0x2000>;
715 clocks = <&cmu CLK_PPMUFILE>;
716 clock-names = "ppmu";
717 status = "disabled";
718 };
719
720 ppmu_g3d: ppmu_g3d@13220000 {
721 compatible = "samsung,exynos-ppmu";
722 reg = <0x13220000 0x2000>;
723 clocks = <&cmu CLK_PPMUG3D>;
724 clock-names = "ppmu";
725 status = "disabled";
726 };
727
728 ppmu_mfc: ppmu_mfc@13660000 {
729 compatible = "samsung,exynos-ppmu";
730 reg = <0x13660000 0x2000>;
731 clocks = <&cmu CLK_PPMUMFC_L>;
732 clock-names = "ppmu";
733 status = "disabled";
734 };
735
736 bus_dmc: bus_dmc {
737 compatible = "samsung,exynos-bus";
738 clocks = <&cmu_dmc CLK_DIV_DMC>;
739 clock-names = "bus";
740 operating-points-v2 = <&bus_dmc_opp_table>;
741 status = "disabled";
742 };
743
744 bus_dmc_opp_table: opp_table1 {
745 compatible = "operating-points-v2";
746 opp-shared;
747
748 opp@50000000 {
749 opp-hz = /bits/ 64 <50000000>;
750 opp-microvolt = <800000>;
751 };
752 opp@100000000 {
753 opp-hz = /bits/ 64 <100000000>;
754 opp-microvolt = <800000>;
755 };
756 opp@134000000 {
757 opp-hz = /bits/ 64 <134000000>;
758 opp-microvolt = <800000>;
759 };
760 opp@200000000 {
761 opp-hz = /bits/ 64 <200000000>;
762 opp-microvolt = <825000>;
763 };
764 opp@400000000 {
765 opp-hz = /bits/ 64 <400000000>;
766 opp-microvolt = <875000>;
767 };
768 };
769
770 bus_leftbus: bus_leftbus {
771 compatible = "samsung,exynos-bus";
772 clocks = <&cmu CLK_DIV_GDL>;
773 clock-names = "bus";
774 operating-points-v2 = <&bus_leftbus_opp_table>;
775 status = "disabled";
776 };
777
778 bus_rightbus: bus_rightbus {
779 compatible = "samsung,exynos-bus";
780 clocks = <&cmu CLK_DIV_GDR>;
781 clock-names = "bus";
782 operating-points-v2 = <&bus_leftbus_opp_table>;
783 status = "disabled";
784 };
785
786 bus_lcd0: bus_lcd0 {
787 compatible = "samsung,exynos-bus";
788 clocks = <&cmu CLK_DIV_ACLK_160>;
789 clock-names = "bus";
790 operating-points-v2 = <&bus_leftbus_opp_table>;
791 status = "disabled";
792 };
793
794 bus_fsys: bus_fsys {
795 compatible = "samsung,exynos-bus";
796 clocks = <&cmu CLK_DIV_ACLK_200>;
797 clock-names = "bus";
798 operating-points-v2 = <&bus_leftbus_opp_table>;
799 status = "disabled";
800 };
801
802 bus_mcuisp: bus_mcuisp {
803 compatible = "samsung,exynos-bus";
804 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
805 clock-names = "bus";
806 operating-points-v2 = <&bus_mcuisp_opp_table>;
807 status = "disabled";
808 };
809
810 bus_isp: bus_isp {
811 compatible = "samsung,exynos-bus";
812 clocks = <&cmu CLK_DIV_ACLK_266>;
813 clock-names = "bus";
814 operating-points-v2 = <&bus_isp_opp_table>;
815 status = "disabled";
816 };
817
818 bus_peril: bus_peril {
819 compatible = "samsung,exynos-bus";
820 clocks = <&cmu CLK_DIV_ACLK_100>;
821 clock-names = "bus";
822 operating-points-v2 = <&bus_peril_opp_table>;
823 status = "disabled";
824 };
825
826 bus_mfc: bus_mfc {
827 compatible = "samsung,exynos-bus";
828 clocks = <&cmu CLK_SCLK_MFC>;
829 clock-names = "bus";
830 operating-points-v2 = <&bus_leftbus_opp_table>;
831 status = "disabled";
832 };
833
834 bus_leftbus_opp_table: opp_table2 {
835 compatible = "operating-points-v2";
836 opp-shared;
837
838 opp@50000000 {
839 opp-hz = /bits/ 64 <50000000>;
840 opp-microvolt = <900000>;
841 };
842 opp@80000000 {
843 opp-hz = /bits/ 64 <80000000>;
844 opp-microvolt = <900000>;
845 };
846 opp@100000000 {
847 opp-hz = /bits/ 64 <100000000>;
848 opp-microvolt = <1000000>;
849 };
850 opp@134000000 {
851 opp-hz = /bits/ 64 <134000000>;
852 opp-microvolt = <1000000>;
853 };
854 opp@200000000 {
855 opp-hz = /bits/ 64 <200000000>;
856 opp-microvolt = <1000000>;
857 };
858 };
859
860 bus_mcuisp_opp_table: opp_table3 {
861 compatible = "operating-points-v2";
862 opp-shared;
863
864 opp@50000000 {
865 opp-hz = /bits/ 64 <50000000>;
866 };
867 opp@80000000 {
868 opp-hz = /bits/ 64 <80000000>;
869 };
870 opp@100000000 {
871 opp-hz = /bits/ 64 <100000000>;
872 };
873 opp@200000000 {
874 opp-hz = /bits/ 64 <200000000>;
875 };
876 opp@400000000 {
877 opp-hz = /bits/ 64 <400000000>;
878 };
879 };
880
881 bus_isp_opp_table: opp_table4 {
882 compatible = "operating-points-v2";
883 opp-shared;
884
885 opp@50000000 {
886 opp-hz = /bits/ 64 <50000000>;
887 };
888 opp@80000000 {
889 opp-hz = /bits/ 64 <80000000>;
890 };
891 opp@100000000 {
892 opp-hz = /bits/ 64 <100000000>;
893 };
894 opp@200000000 {
895 opp-hz = /bits/ 64 <200000000>;
896 };
897 opp@300000000 {
898 opp-hz = /bits/ 64 <300000000>;
899 };
900 };
901
902 bus_peril_opp_table: opp_table5 {
903 compatible = "operating-points-v2";
904 opp-shared;
905
906 opp@50000000 {
907 opp-hz = /bits/ 64 <50000000>;
908 };
909 opp@80000000 {
910 opp-hz = /bits/ 64 <80000000>;
911 };
912 opp@100000000 {
913 opp-hz = /bits/ 64 <100000000>;
914 };
915 };
916 };
917};
918
919#include "exynos3250-pinctrl.dtsi"