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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Broadcom BCM63138 DSL SoCs Device Tree
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8
9#include "skeleton.dtsi"
10
11/ {
12 compatible = "brcm,bcm63138";
13 model = "Broadcom BCM63138 DSL SoC";
14 interrupt-parent = <&gic>;
15
16 aliases {
17 uart0 = &serial0;
18 uart1 = &serial1;
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
29 reg = <0>;
30 enable-method = "brcm,bcm63138";
31 };
32
33 cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
37 reg = <1>;
38 enable-method = "brcm,bcm63138";
39 resets = <&pmb0 4 1>;
40 };
41 };
42
43 clocks {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 /* UBUS peripheral clock */
48 periph_clk: periph_clk {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
52 clock-output-names = "periph";
53 };
54
55 /* peripheral clock for system timer */
56 axi_clk: axi_clk {
57 #clock-cells = <0>;
58 compatible = "fixed-factor-clock";
59 clocks = <&armpll>;
60 clock-div = <2>;
61 clock-mult = <1>;
62 };
63
64 /* APB bus clock */
65 apb_clk: apb_clk {
66 #clock-cells = <0>;
67 compatible = "fixed-factor-clock";
68 clocks = <&armpll>;
69 clock-div = <4>;
70 clock-mult = <1>;
71 };
72 };
73
74 /* ARM bus */
75 axi@80000000 {
76 compatible = "simple-bus";
77 ranges = <0 0x80000000 0x784000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80
81 L2: cache-controller@1d000 {
82 compatible = "arm,pl310-cache";
83 reg = <0x1d000 0x1000>;
84 cache-unified;
85 cache-level = <2>;
86 cache-size = <524288>;
87 cache-sets = <1024>;
88 cache-line-size = <32>;
89 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
90 };
91
92 scu: scu@1e000 {
93 compatible = "arm,cortex-a9-scu";
94 reg = <0x1e000 0x100>;
95 };
96
97 gic: interrupt-controller@1e100 {
98 compatible = "arm,cortex-a9-gic";
99 reg = <0x1f000 0x1000
100 0x1e100 0x100>;
101 #interrupt-cells = <3>;
102 #address-cells = <0>;
103 interrupt-controller;
104 };
105
106 global_timer: timer@1e200 {
107 compatible = "arm,cortex-a9-global-timer";
108 reg = <0x1e200 0x20>;
109 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&axi_clk>;
111 };
112
113 local_timer: local-timer@1e600 {
114 compatible = "arm,cortex-a9-twd-timer";
115 reg = <0x1e600 0x20>;
116 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&axi_clk>;
118 };
119
120 twd_watchdog: watchdog@1e620 {
121 compatible = "arm,cortex-a9-twd-wdt";
122 reg = <0x1e620 0x20>;
123 interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
124 };
125
126 armpll: armpll {
127 #clock-cells = <0>;
128 compatible = "brcm,bcm63138-armpll";
129 clocks = <&periph_clk>;
130 reg = <0x20000 0xf00>;
131 };
132
133 pmb0: reset-controller@4800c0 {
134 compatible = "brcm,bcm63138-pmb";
135 reg = <0x4800c0 0x10>;
136 #reset-cells = <2>;
137 };
138
139 pmb1: reset-controller@4800e0 {
140 compatible = "brcm,bcm63138-pmb";
141 reg = <0x4800e0 0x10>;
142 #reset-cells = <2>;
143 };
144 };
145
146 /* Legacy UBUS base */
147 ubus@fffe8000 {
148 compatible = "simple-bus";
149 #address-cells = <1>;
150 #size-cells = <1>;
151 ranges = <0 0xfffe8000 0x8100>;
152
153 timer: timer@80 {
154 compatible = "brcm,bcm6328-timer", "syscon";
155 reg = <0x80 0x3c>;
156 };
157
158 serial0: serial@600 {
159 compatible = "brcm,bcm6345-uart";
160 reg = <0x600 0x1b>;
161 interrupts = <GIC_SPI 32 0>;
162 clocks = <&periph_clk>;
163 clock-names = "periph";
164 status = "disabled";
165 };
166
167 serial1: serial@620 {
168 compatible = "brcm,bcm6345-uart";
169 reg = <0x620 0x1b>;
170 interrupts = <GIC_SPI 33 0>;
171 clocks = <&periph_clk>;
172 clock-names = "periph";
173 status = "disabled";
174 };
175
176 nand: nand@2000 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
180 reg = <0x2000 0x600>, <0xf0 0x10>;
181 reg-names = "nand", "nand-int-base";
182 status = "disabled";
183 interrupts = <GIC_SPI 38 0>;
184 interrupt-names = "nand";
185 };
186
187 bootlut: bootlut@8000 {
188 compatible = "brcm,bcm63138-bootlut";
189 reg = <0x8000 0x50>;
190 };
191
192 reboot {
193 compatible = "syscon-reboot";
194 regmap = <&timer>;
195 offset = <0x34>;
196 mask = <1>;
197 };
198 };
199};
1/*
2 * Broadcom BCM63138 DSL SoCs Device Tree
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7
8#include "skeleton.dtsi"
9
10/ {
11 compatible = "brcm,bcm63138";
12 model = "Broadcom BCM63138 DSL SoC";
13 interrupt-parent = <&gic>;
14
15 aliases {
16 uart0 = &serial0;
17 uart1 = &serial1;
18 };
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
28 reg = <0>;
29 enable-method = "brcm,bcm63138";
30 };
31
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a9";
35 next-level-cache = <&L2>;
36 reg = <1>;
37 enable-method = "brcm,bcm63138";
38 resets = <&pmb0 4 1>;
39 };
40 };
41
42 clocks {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 /* UBUS peripheral clock */
47 periph_clk: periph_clk {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <50000000>;
51 clock-output-names = "periph";
52 };
53
54 /* peripheral clock for system timer */
55 axi_clk: axi_clk {
56 #clock-cells = <0>;
57 compatible = "fixed-factor-clock";
58 clocks = <&armpll>;
59 clock-div = <2>;
60 clock-mult = <1>;
61 };
62
63 /* APB bus clock */
64 apb_clk: apb_clk {
65 #clock-cells = <0>;
66 compatible = "fixed-factor-clock";
67 clocks = <&armpll>;
68 clock-div = <4>;
69 clock-mult = <1>;
70 };
71 };
72
73 /* ARM bus */
74 axi@80000000 {
75 compatible = "simple-bus";
76 ranges = <0 0x80000000 0x784000>;
77 #address-cells = <1>;
78 #size-cells = <1>;
79
80 L2: cache-controller@1d000 {
81 compatible = "arm,pl310-cache";
82 reg = <0x1d000 0x1000>;
83 cache-unified;
84 cache-level = <2>;
85 cache-size = <524288>;
86 cache-sets = <1024>;
87 cache-line-size = <32>;
88 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
91 scu: scu@1e000 {
92 compatible = "arm,cortex-a9-scu";
93 reg = <0x1e000 0x100>;
94 };
95
96 gic: interrupt-controller@1e100 {
97 compatible = "arm,cortex-a9-gic";
98 reg = <0x1f000 0x1000
99 0x1e100 0x100>;
100 #interrupt-cells = <3>;
101 #address-cells = <0>;
102 interrupt-controller;
103 };
104
105 global_timer: timer@1e200 {
106 compatible = "arm,cortex-a9-global-timer";
107 reg = <0x1e200 0x20>;
108 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&axi_clk>;
110 };
111
112 local_timer: local-timer@1e600 {
113 compatible = "arm,cortex-a9-twd-timer";
114 reg = <0x1e600 0x20>;
115 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&axi_clk>;
117 };
118
119 twd_watchdog: watchdog@1e620 {
120 compatible = "arm,cortex-a9-twd-wdt";
121 reg = <0x1e620 0x20>;
122 interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
123 };
124
125 armpll: armpll {
126 #clock-cells = <0>;
127 compatible = "brcm,bcm63138-armpll";
128 clocks = <&periph_clk>;
129 reg = <0x20000 0xf00>;
130 };
131
132 pmb0: reset-controller@4800c0 {
133 compatible = "brcm,bcm63138-pmb";
134 reg = <0x4800c0 0x10>;
135 #reset-cells = <2>;
136 };
137
138 pmb1: reset-controller@4800e0 {
139 compatible = "brcm,bcm63138-pmb";
140 reg = <0x4800e0 0x10>;
141 #reset-cells = <2>;
142 };
143 };
144
145 /* Legacy UBUS base */
146 ubus@fffe8000 {
147 compatible = "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0 0xfffe8000 0x8100>;
151
152 timer: timer@80 {
153 compatible = "brcm,bcm6328-timer", "syscon";
154 reg = <0x80 0x3c>;
155 };
156
157 serial0: serial@600 {
158 compatible = "brcm,bcm6345-uart";
159 reg = <0x600 0x1b>;
160 interrupts = <GIC_SPI 32 0>;
161 clocks = <&periph_clk>;
162 clock-names = "periph";
163 status = "disabled";
164 };
165
166 serial1: serial@620 {
167 compatible = "brcm,bcm6345-uart";
168 reg = <0x620 0x1b>;
169 interrupts = <GIC_SPI 33 0>;
170 clocks = <&periph_clk>;
171 clock-names = "periph";
172 status = "disabled";
173 };
174
175 nand: nand@2000 {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
179 reg = <0x2000 0x600>, <0xf0 0x10>;
180 reg-names = "nand", "nand-int-base";
181 status = "disabled";
182 interrupts = <GIC_SPI 38 0>;
183 interrupt-names = "nand";
184 };
185
186 bootlut: bootlut@8000 {
187 compatible = "brcm,bcm63138-bootlut";
188 reg = <0x8000 0x50>;
189 };
190
191 reboot {
192 compatible = "syscon-reboot";
193 regmap = <&timer>;
194 offset = <0x34>;
195 mask = <1>;
196 };
197 };
198};