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1#include <dt-bindings/pinctrl/bcm2835.h>
2#include <dt-bindings/clock/bcm2835.h>
3#include <dt-bindings/clock/bcm2835-aux.h>
4#include <dt-bindings/gpio/gpio.h>
5#include <dt-bindings/interrupt-controller/irq.h>
6
7/* firmware-provided startup stubs live here, where the secondary CPUs are
8 * spinning.
9 */
10/memreserve/ 0x00000000 0x00001000;
11
12/* This include file covers the common peripherals and configuration between
13 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
14 * bcm2835.dtsi and bcm2836.dtsi.
15 */
16
17/ {
18 compatible = "brcm,bcm2835";
19 model = "BCM2835";
20 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 };
28
29 chosen {
30 stdout-path = "serial0:115200n8";
31 };
32
33 thermal-zones {
34 cpu_thermal: cpu-thermal {
35 polling-delay-passive = <0>;
36 polling-delay = <1000>;
37
38 thermal-sensors = <&thermal>;
39
40 trips {
41 cpu-crit {
42 temperature = <80000>;
43 hysteresis = <0>;
44 type = "critical";
45 };
46 };
47
48 cooling-maps {
49 };
50 };
51 };
52
53 soc {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57
58 timer@7e003000 {
59 compatible = "brcm,bcm2835-system-timer";
60 reg = <0x7e003000 0x1000>;
61 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
62 /* This could be a reference to BCM2835_CLOCK_TIMER,
63 * but we don't have the driver using the common clock
64 * support yet.
65 */
66 clock-frequency = <1000000>;
67 };
68
69 dma: dma@7e007000 {
70 compatible = "brcm,bcm2835-dma";
71 reg = <0x7e007000 0xf00>;
72 interrupts = <1 16>,
73 <1 17>,
74 <1 18>,
75 <1 19>,
76 <1 20>,
77 <1 21>,
78 <1 22>,
79 <1 23>,
80 <1 24>,
81 <1 25>,
82 <1 26>,
83 /* dma channel 11-14 share one irq */
84 <1 27>,
85 <1 27>,
86 <1 27>,
87 <1 27>,
88 /* unused shared irq for all channels */
89 <1 28>;
90 interrupt-names = "dma0",
91 "dma1",
92 "dma2",
93 "dma3",
94 "dma4",
95 "dma5",
96 "dma6",
97 "dma7",
98 "dma8",
99 "dma9",
100 "dma10",
101 "dma11",
102 "dma12",
103 "dma13",
104 "dma14",
105 "dma-shared-all";
106 #dma-cells = <1>;
107 brcm,dma-channel-mask = <0x7f35>;
108 };
109
110 intc: interrupt-controller@7e00b200 {
111 compatible = "brcm,bcm2835-armctrl-ic";
112 reg = <0x7e00b200 0x200>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 };
116
117 watchdog@7e100000 {
118 compatible = "brcm,bcm2835-pm-wdt";
119 reg = <0x7e100000 0x28>;
120 };
121
122 clocks: cprman@7e101000 {
123 compatible = "brcm,bcm2835-cprman";
124 #clock-cells = <1>;
125 reg = <0x7e101000 0x2000>;
126
127 /* CPRMAN derives almost everything from the
128 * platform's oscillator. However, the DSI
129 * pixel clocks come from the DSI analog PHY.
130 */
131 clocks = <&clk_osc>,
132 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
133 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
134 };
135
136 rng@7e104000 {
137 compatible = "brcm,bcm2835-rng";
138 reg = <0x7e104000 0x10>;
139 };
140
141 mailbox: mailbox@7e00b880 {
142 compatible = "brcm,bcm2835-mbox";
143 reg = <0x7e00b880 0x40>;
144 interrupts = <0 1>;
145 #mbox-cells = <0>;
146 };
147
148 gpio: gpio@7e200000 {
149 compatible = "brcm,bcm2835-gpio";
150 reg = <0x7e200000 0xb4>;
151 /*
152 * The GPIO IP block is designed for 3 banks of GPIOs.
153 * Each bank has a GPIO interrupt for itself.
154 * There is an overall "any bank" interrupt.
155 * In order, these are GIC interrupts 17, 18, 19, 20.
156 * Since the BCM2835 only has 2 banks, the 2nd bank
157 * interrupt output appears to be mirrored onto the
158 * 3rd bank's interrupt signal.
159 * So, a bank0 interrupt shows up on 17, 20, and
160 * a bank1 interrupt shows up on 18, 19, 20!
161 */
162 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
163
164 gpio-controller;
165 #gpio-cells = <2>;
166
167 interrupt-controller;
168 #interrupt-cells = <2>;
169
170 /* Defines pin muxing groups according to
171 * BCM2835-ARM-Peripherals.pdf page 102.
172 *
173 * While each pin can have its mux selected
174 * for various functions individually, some
175 * groups only make sense to switch to a
176 * particular function together.
177 */
178 dpi_gpio0: dpi_gpio0 {
179 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
180 12 13 14 15 16 17 18 19
181 20 21 22 23 24 25 26 27>;
182 brcm,function = <BCM2835_FSEL_ALT2>;
183 };
184 emmc_gpio22: emmc_gpio22 {
185 brcm,pins = <22 23 24 25 26 27>;
186 brcm,function = <BCM2835_FSEL_ALT3>;
187 };
188 emmc_gpio34: emmc_gpio34 {
189 brcm,pins = <34 35 36 37 38 39>;
190 brcm,function = <BCM2835_FSEL_ALT3>;
191 brcm,pull = <BCM2835_PUD_OFF
192 BCM2835_PUD_UP
193 BCM2835_PUD_UP
194 BCM2835_PUD_UP
195 BCM2835_PUD_UP
196 BCM2835_PUD_UP>;
197 };
198 emmc_gpio48: emmc_gpio48 {
199 brcm,pins = <48 49 50 51 52 53>;
200 brcm,function = <BCM2835_FSEL_ALT3>;
201 };
202
203 gpclk0_gpio4: gpclk0_gpio4 {
204 brcm,pins = <4>;
205 brcm,function = <BCM2835_FSEL_ALT0>;
206 };
207 gpclk1_gpio5: gpclk1_gpio5 {
208 brcm,pins = <5>;
209 brcm,function = <BCM2835_FSEL_ALT0>;
210 };
211 gpclk1_gpio42: gpclk1_gpio42 {
212 brcm,pins = <42>;
213 brcm,function = <BCM2835_FSEL_ALT0>;
214 };
215 gpclk1_gpio44: gpclk1_gpio44 {
216 brcm,pins = <44>;
217 brcm,function = <BCM2835_FSEL_ALT0>;
218 };
219 gpclk2_gpio6: gpclk2_gpio6 {
220 brcm,pins = <6>;
221 brcm,function = <BCM2835_FSEL_ALT0>;
222 };
223 gpclk2_gpio43: gpclk2_gpio43 {
224 brcm,pins = <43>;
225 brcm,function = <BCM2835_FSEL_ALT0>;
226 brcm,pull = <BCM2835_PUD_OFF>;
227 };
228
229 i2c0_gpio0: i2c0_gpio0 {
230 brcm,pins = <0 1>;
231 brcm,function = <BCM2835_FSEL_ALT0>;
232 };
233 i2c0_gpio28: i2c0_gpio28 {
234 brcm,pins = <28 29>;
235 brcm,function = <BCM2835_FSEL_ALT0>;
236 };
237 i2c0_gpio44: i2c0_gpio44 {
238 brcm,pins = <44 45>;
239 brcm,function = <BCM2835_FSEL_ALT1>;
240 };
241 i2c1_gpio2: i2c1_gpio2 {
242 brcm,pins = <2 3>;
243 brcm,function = <BCM2835_FSEL_ALT0>;
244 };
245 i2c1_gpio44: i2c1_gpio44 {
246 brcm,pins = <44 45>;
247 brcm,function = <BCM2835_FSEL_ALT2>;
248 };
249 i2c_slave_gpio18: i2c_slave_gpio18 {
250 brcm,pins = <18 19 20 21>;
251 brcm,function = <BCM2835_FSEL_ALT3>;
252 };
253
254 jtag_gpio4: jtag_gpio4 {
255 brcm,pins = <4 5 6 12 13>;
256 brcm,function = <BCM2835_FSEL_ALT5>;
257 };
258 jtag_gpio22: jtag_gpio22 {
259 brcm,pins = <22 23 24 25 26 27>;
260 brcm,function = <BCM2835_FSEL_ALT4>;
261 };
262
263 pcm_gpio18: pcm_gpio18 {
264 brcm,pins = <18 19 20 21>;
265 brcm,function = <BCM2835_FSEL_ALT0>;
266 };
267 pcm_gpio28: pcm_gpio28 {
268 brcm,pins = <28 29 30 31>;
269 brcm,function = <BCM2835_FSEL_ALT2>;
270 };
271
272 pwm0_gpio12: pwm0_gpio12 {
273 brcm,pins = <12>;
274 brcm,function = <BCM2835_FSEL_ALT0>;
275 };
276 pwm0_gpio18: pwm0_gpio18 {
277 brcm,pins = <18>;
278 brcm,function = <BCM2835_FSEL_ALT5>;
279 };
280 pwm0_gpio40: pwm0_gpio40 {
281 brcm,pins = <40>;
282 brcm,function = <BCM2835_FSEL_ALT0>;
283 };
284 pwm1_gpio13: pwm1_gpio13 {
285 brcm,pins = <13>;
286 brcm,function = <BCM2835_FSEL_ALT0>;
287 };
288 pwm1_gpio19: pwm1_gpio19 {
289 brcm,pins = <19>;
290 brcm,function = <BCM2835_FSEL_ALT5>;
291 };
292 pwm1_gpio41: pwm1_gpio41 {
293 brcm,pins = <41>;
294 brcm,function = <BCM2835_FSEL_ALT0>;
295 };
296 pwm1_gpio45: pwm1_gpio45 {
297 brcm,pins = <45>;
298 brcm,function = <BCM2835_FSEL_ALT0>;
299 };
300
301 sdhost_gpio48: sdhost_gpio48 {
302 brcm,pins = <48 49 50 51 52 53>;
303 brcm,function = <BCM2835_FSEL_ALT0>;
304 };
305
306 spi0_gpio7: spi0_gpio7 {
307 brcm,pins = <7 8 9 10 11>;
308 brcm,function = <BCM2835_FSEL_ALT0>;
309 };
310 spi0_gpio35: spi0_gpio35 {
311 brcm,pins = <35 36 37 38 39>;
312 brcm,function = <BCM2835_FSEL_ALT0>;
313 };
314 spi1_gpio16: spi1_gpio16 {
315 brcm,pins = <16 17 18 19 20 21>;
316 brcm,function = <BCM2835_FSEL_ALT4>;
317 };
318 spi2_gpio40: spi2_gpio40 {
319 brcm,pins = <40 41 42 43 44 45>;
320 brcm,function = <BCM2835_FSEL_ALT4>;
321 };
322
323 uart0_gpio14: uart0_gpio14 {
324 brcm,pins = <14 15>;
325 brcm,function = <BCM2835_FSEL_ALT0>;
326 };
327 /* Separate from the uart0_gpio14 group
328 * because it conflicts with spi1_gpio16, and
329 * people often run uart0 on the two pins
330 * without flow control.
331 */
332 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
333 brcm,pins = <16 17>;
334 brcm,function = <BCM2835_FSEL_ALT3>;
335 };
336 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
337 brcm,pins = <30 31>;
338 brcm,function = <BCM2835_FSEL_ALT3>;
339 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
340 };
341 uart0_gpio32: uart0_gpio32 {
342 brcm,pins = <32 33>;
343 brcm,function = <BCM2835_FSEL_ALT3>;
344 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
345 };
346 uart0_gpio36: uart0_gpio36 {
347 brcm,pins = <36 37>;
348 brcm,function = <BCM2835_FSEL_ALT2>;
349 };
350 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
351 brcm,pins = <38 39>;
352 brcm,function = <BCM2835_FSEL_ALT2>;
353 };
354
355 uart1_gpio14: uart1_gpio14 {
356 brcm,pins = <14 15>;
357 brcm,function = <BCM2835_FSEL_ALT5>;
358 };
359 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
360 brcm,pins = <16 17>;
361 brcm,function = <BCM2835_FSEL_ALT5>;
362 };
363 uart1_gpio32: uart1_gpio32 {
364 brcm,pins = <32 33>;
365 brcm,function = <BCM2835_FSEL_ALT5>;
366 };
367 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
368 brcm,pins = <30 31>;
369 brcm,function = <BCM2835_FSEL_ALT5>;
370 };
371 uart1_gpio40: uart1_gpio40 {
372 brcm,pins = <40 41>;
373 brcm,function = <BCM2835_FSEL_ALT5>;
374 };
375 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
376 brcm,pins = <42 43>;
377 brcm,function = <BCM2835_FSEL_ALT5>;
378 };
379 };
380
381 uart0: serial@7e201000 {
382 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
383 reg = <0x7e201000 0x1000>;
384 interrupts = <2 25>;
385 clocks = <&clocks BCM2835_CLOCK_UART>,
386 <&clocks BCM2835_CLOCK_VPU>;
387 clock-names = "uartclk", "apb_pclk";
388 arm,primecell-periphid = <0x00241011>;
389 };
390
391 sdhost: mmc@7e202000 {
392 compatible = "brcm,bcm2835-sdhost";
393 reg = <0x7e202000 0x100>;
394 interrupts = <2 24>;
395 clocks = <&clocks BCM2835_CLOCK_VPU>;
396 dmas = <&dma 13>;
397 dma-names = "rx-tx";
398 status = "disabled";
399 };
400
401 i2s: i2s@7e203000 {
402 compatible = "brcm,bcm2835-i2s";
403 reg = <0x7e203000 0x24>;
404 clocks = <&clocks BCM2835_CLOCK_PCM>;
405
406 dmas = <&dma 2>,
407 <&dma 3>;
408 dma-names = "tx", "rx";
409 status = "disabled";
410 };
411
412 spi: spi@7e204000 {
413 compatible = "brcm,bcm2835-spi";
414 reg = <0x7e204000 0x1000>;
415 interrupts = <2 22>;
416 clocks = <&clocks BCM2835_CLOCK_VPU>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
421
422 i2c0: i2c@7e205000 {
423 compatible = "brcm,bcm2835-i2c";
424 reg = <0x7e205000 0x1000>;
425 interrupts = <2 21>;
426 clocks = <&clocks BCM2835_CLOCK_VPU>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 status = "disabled";
430 };
431
432 pixelvalve@7e206000 {
433 compatible = "brcm,bcm2835-pixelvalve0";
434 reg = <0x7e206000 0x100>;
435 interrupts = <2 13>; /* pwa0 */
436 };
437
438 pixelvalve@7e207000 {
439 compatible = "brcm,bcm2835-pixelvalve1";
440 reg = <0x7e207000 0x100>;
441 interrupts = <2 14>; /* pwa1 */
442 };
443
444 dpi: dpi@7e208000 {
445 compatible = "brcm,bcm2835-dpi";
446 reg = <0x7e208000 0x8c>;
447 clocks = <&clocks BCM2835_CLOCK_VPU>,
448 <&clocks BCM2835_CLOCK_DPI>;
449 clock-names = "core", "pixel";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 status = "disabled";
453 };
454
455 dsi0: dsi@7e209000 {
456 compatible = "brcm,bcm2835-dsi0";
457 reg = <0x7e209000 0x78>;
458 interrupts = <2 4>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 #clock-cells = <1>;
462
463 clocks = <&clocks BCM2835_PLLA_DSI0>,
464 <&clocks BCM2835_CLOCK_DSI0E>,
465 <&clocks BCM2835_CLOCK_DSI0P>;
466 clock-names = "phy", "escape", "pixel";
467
468 clock-output-names = "dsi0_byte",
469 "dsi0_ddr2",
470 "dsi0_ddr";
471
472 };
473
474 thermal: thermal@7e212000 {
475 compatible = "brcm,bcm2835-thermal";
476 reg = <0x7e212000 0x8>;
477 clocks = <&clocks BCM2835_CLOCK_TSENS>;
478 #thermal-sensor-cells = <0>;
479 status = "disabled";
480 };
481
482 aux: aux@7e215000 {
483 compatible = "brcm,bcm2835-aux";
484 #clock-cells = <1>;
485 reg = <0x7e215000 0x8>;
486 clocks = <&clocks BCM2835_CLOCK_VPU>;
487 };
488
489 uart1: serial@7e215040 {
490 compatible = "brcm,bcm2835-aux-uart";
491 reg = <0x7e215040 0x40>;
492 interrupts = <1 29>;
493 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
494 status = "disabled";
495 };
496
497 spi1: spi@7e215080 {
498 compatible = "brcm,bcm2835-aux-spi";
499 reg = <0x7e215080 0x40>;
500 interrupts = <1 29>;
501 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
502 #address-cells = <1>;
503 #size-cells = <0>;
504 status = "disabled";
505 };
506
507 spi2: spi@7e2150c0 {
508 compatible = "brcm,bcm2835-aux-spi";
509 reg = <0x7e2150c0 0x40>;
510 interrupts = <1 29>;
511 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 status = "disabled";
515 };
516
517 pwm: pwm@7e20c000 {
518 compatible = "brcm,bcm2835-pwm";
519 reg = <0x7e20c000 0x28>;
520 clocks = <&clocks BCM2835_CLOCK_PWM>;
521 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
522 assigned-clock-rates = <10000000>;
523 #pwm-cells = <2>;
524 status = "disabled";
525 };
526
527 sdhci: sdhci@7e300000 {
528 compatible = "brcm,bcm2835-sdhci";
529 reg = <0x7e300000 0x100>;
530 interrupts = <2 30>;
531 clocks = <&clocks BCM2835_CLOCK_EMMC>;
532 status = "disabled";
533 };
534
535 hvs@7e400000 {
536 compatible = "brcm,bcm2835-hvs";
537 reg = <0x7e400000 0x6000>;
538 interrupts = <2 1>;
539 };
540
541 dsi1: dsi@7e700000 {
542 compatible = "brcm,bcm2835-dsi1";
543 reg = <0x7e700000 0x8c>;
544 interrupts = <2 12>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 #clock-cells = <1>;
548
549 clocks = <&clocks BCM2835_PLLD_DSI1>,
550 <&clocks BCM2835_CLOCK_DSI1E>,
551 <&clocks BCM2835_CLOCK_DSI1P>;
552 clock-names = "phy", "escape", "pixel";
553
554 clock-output-names = "dsi1_byte",
555 "dsi1_ddr2",
556 "dsi1_ddr";
557
558 status = "disabled";
559 };
560
561 i2c1: i2c@7e804000 {
562 compatible = "brcm,bcm2835-i2c";
563 reg = <0x7e804000 0x1000>;
564 interrupts = <2 21>;
565 clocks = <&clocks BCM2835_CLOCK_VPU>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 status = "disabled";
569 };
570
571 i2c2: i2c@7e805000 {
572 compatible = "brcm,bcm2835-i2c";
573 reg = <0x7e805000 0x1000>;
574 interrupts = <2 21>;
575 clocks = <&clocks BCM2835_CLOCK_VPU>;
576 #address-cells = <1>;
577 #size-cells = <0>;
578 status = "disabled";
579 };
580
581 vec: vec@7e806000 {
582 compatible = "brcm,bcm2835-vec";
583 reg = <0x7e806000 0x1000>;
584 clocks = <&clocks BCM2835_CLOCK_VEC>;
585 interrupts = <2 27>;
586 status = "disabled";
587 };
588
589 pixelvalve@7e807000 {
590 compatible = "brcm,bcm2835-pixelvalve2";
591 reg = <0x7e807000 0x100>;
592 interrupts = <2 10>; /* pixelvalve */
593 };
594
595 hdmi: hdmi@7e902000 {
596 compatible = "brcm,bcm2835-hdmi";
597 reg = <0x7e902000 0x600>,
598 <0x7e808000 0x100>;
599 interrupts = <2 8>, <2 9>;
600 ddc = <&i2c2>;
601 clocks = <&clocks BCM2835_PLLH_PIX>,
602 <&clocks BCM2835_CLOCK_HSM>;
603 clock-names = "pixel", "hdmi";
604 dmas = <&dma 17>;
605 dma-names = "audio-rx";
606 status = "disabled";
607 };
608
609 usb: usb@7e980000 {
610 compatible = "brcm,bcm2835-usb";
611 reg = <0x7e980000 0x10000>;
612 interrupts = <1 9>;
613 #address-cells = <1>;
614 #size-cells = <0>;
615 clocks = <&clk_usb>;
616 clock-names = "otg";
617 phys = <&usbphy>;
618 phy-names = "usb2-phy";
619 };
620
621 v3d: v3d@7ec00000 {
622 compatible = "brcm,bcm2835-v3d";
623 reg = <0x7ec00000 0x1000>;
624 interrupts = <1 10>;
625 };
626
627 vc4: gpu {
628 compatible = "brcm,bcm2835-vc4";
629 };
630 };
631
632 clocks {
633 compatible = "simple-bus";
634 #address-cells = <1>;
635 #size-cells = <0>;
636
637 /* The oscillator is the root of the clock tree. */
638 clk_osc: clock@3 {
639 compatible = "fixed-clock";
640 reg = <3>;
641 #clock-cells = <0>;
642 clock-output-names = "osc";
643 clock-frequency = <19200000>;
644 };
645
646 clk_usb: clock@4 {
647 compatible = "fixed-clock";
648 reg = <4>;
649 #clock-cells = <0>;
650 clock-output-names = "otg";
651 clock-frequency = <480000000>;
652 };
653 };
654
655 usbphy: phy {
656 compatible = "usb-nop-xceiv";
657 #phy-cells = <0>;
658 };
659};
1#include <dt-bindings/pinctrl/bcm2835.h>
2#include <dt-bindings/clock/bcm2835.h>
3#include <dt-bindings/clock/bcm2835-aux.h>
4#include <dt-bindings/gpio/gpio.h>
5
6/* This include file covers the common peripherals and configuration between
7 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
8 * bcm2835.dtsi and bcm2836.dtsi.
9 */
10
11/ {
12 compatible = "brcm,bcm2835";
13 model = "BCM2835";
14 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 chosen {
19 bootargs = "earlyprintk console=ttyAMA0";
20 };
21
22 soc {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 timer@7e003000 {
28 compatible = "brcm,bcm2835-system-timer";
29 reg = <0x7e003000 0x1000>;
30 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
31 /* This could be a reference to BCM2835_CLOCK_TIMER,
32 * but we don't have the driver using the common clock
33 * support yet.
34 */
35 clock-frequency = <1000000>;
36 };
37
38 dma: dma@7e007000 {
39 compatible = "brcm,bcm2835-dma";
40 reg = <0x7e007000 0xf00>;
41 interrupts = <1 16>,
42 <1 17>,
43 <1 18>,
44 <1 19>,
45 <1 20>,
46 <1 21>,
47 <1 22>,
48 <1 23>,
49 <1 24>,
50 <1 25>,
51 <1 26>,
52 /* dma channel 11-14 share one irq */
53 <1 27>,
54 <1 27>,
55 <1 27>,
56 <1 27>,
57 /* unused shared irq for all channels */
58 <1 28>;
59 interrupt-names = "dma0",
60 "dma1",
61 "dma2",
62 "dma3",
63 "dma4",
64 "dma5",
65 "dma6",
66 "dma7",
67 "dma8",
68 "dma9",
69 "dma10",
70 "dma11",
71 "dma12",
72 "dma13",
73 "dma14",
74 "dma-shared-all";
75 #dma-cells = <1>;
76 brcm,dma-channel-mask = <0x7f35>;
77 };
78
79 intc: interrupt-controller@7e00b200 {
80 compatible = "brcm,bcm2835-armctrl-ic";
81 reg = <0x7e00b200 0x200>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
84 };
85
86 watchdog@7e100000 {
87 compatible = "brcm,bcm2835-pm-wdt";
88 reg = <0x7e100000 0x28>;
89 };
90
91 clocks: cprman@7e101000 {
92 compatible = "brcm,bcm2835-cprman";
93 #clock-cells = <1>;
94 reg = <0x7e101000 0x2000>;
95
96 /* CPRMAN derives everything from the platform's
97 * oscillator.
98 */
99 clocks = <&clk_osc>;
100 };
101
102 rng@7e104000 {
103 compatible = "brcm,bcm2835-rng";
104 reg = <0x7e104000 0x10>;
105 };
106
107 mailbox: mailbox@7e00b880 {
108 compatible = "brcm,bcm2835-mbox";
109 reg = <0x7e00b880 0x40>;
110 interrupts = <0 1>;
111 #mbox-cells = <0>;
112 };
113
114 gpio: gpio@7e200000 {
115 compatible = "brcm,bcm2835-gpio";
116 reg = <0x7e200000 0xb4>;
117 /*
118 * The GPIO IP block is designed for 3 banks of GPIOs.
119 * Each bank has a GPIO interrupt for itself.
120 * There is an overall "any bank" interrupt.
121 * In order, these are GIC interrupts 17, 18, 19, 20.
122 * Since the BCM2835 only has 2 banks, the 2nd bank
123 * interrupt output appears to be mirrored onto the
124 * 3rd bank's interrupt signal.
125 * So, a bank0 interrupt shows up on 17, 20, and
126 * a bank1 interrupt shows up on 18, 19, 20!
127 */
128 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
129
130 gpio-controller;
131 #gpio-cells = <2>;
132
133 interrupt-controller;
134 #interrupt-cells = <2>;
135
136 /* Defines pin muxing groups according to
137 * BCM2835-ARM-Peripherals.pdf page 102.
138 *
139 * While each pin can have its mux selected
140 * for various functions individually, some
141 * groups only make sense to switch to a
142 * particular function together.
143 */
144 dpi_gpio0: dpi_gpio0 {
145 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
146 12 13 14 15 16 17 18 19
147 20 21 22 23 24 25 26 27>;
148 brcm,function = <BCM2835_FSEL_ALT2>;
149 };
150 emmc_gpio22: emmc_gpio22 {
151 brcm,pins = <22 23 24 25 26 27>;
152 brcm,function = <BCM2835_FSEL_ALT3>;
153 };
154 emmc_gpio34: emmc_gpio34 {
155 brcm,pins = <34 35 36 37 38 39>;
156 brcm,function = <BCM2835_FSEL_ALT3>;
157 brcm,pull = <BCM2835_PUD_OFF
158 BCM2835_PUD_UP
159 BCM2835_PUD_UP
160 BCM2835_PUD_UP
161 BCM2835_PUD_UP
162 BCM2835_PUD_UP>;
163 };
164 emmc_gpio48: emmc_gpio48 {
165 brcm,pins = <48 49 50 51 52 53>;
166 brcm,function = <BCM2835_FSEL_ALT3>;
167 };
168
169 gpclk0_gpio4: gpclk0_gpio4 {
170 brcm,pins = <4>;
171 brcm,function = <BCM2835_FSEL_ALT0>;
172 };
173 gpclk1_gpio5: gpclk1_gpio5 {
174 brcm,pins = <5>;
175 brcm,function = <BCM2835_FSEL_ALT0>;
176 };
177 gpclk1_gpio42: gpclk1_gpio42 {
178 brcm,pins = <42>;
179 brcm,function = <BCM2835_FSEL_ALT0>;
180 };
181 gpclk1_gpio44: gpclk1_gpio44 {
182 brcm,pins = <44>;
183 brcm,function = <BCM2835_FSEL_ALT0>;
184 };
185 gpclk2_gpio6: gpclk2_gpio6 {
186 brcm,pins = <6>;
187 brcm,function = <BCM2835_FSEL_ALT0>;
188 };
189 gpclk2_gpio43: gpclk2_gpio43 {
190 brcm,pins = <43>;
191 brcm,function = <BCM2835_FSEL_ALT0>;
192 };
193
194 i2c0_gpio0: i2c0_gpio0 {
195 brcm,pins = <0 1>;
196 brcm,function = <BCM2835_FSEL_ALT0>;
197 };
198 i2c0_gpio32: i2c0_gpio32 {
199 brcm,pins = <32 34>;
200 brcm,function = <BCM2835_FSEL_ALT0>;
201 };
202 i2c0_gpio44: i2c0_gpio44 {
203 brcm,pins = <44 45>;
204 brcm,function = <BCM2835_FSEL_ALT1>;
205 };
206 i2c1_gpio2: i2c1_gpio2 {
207 brcm,pins = <2 3>;
208 brcm,function = <BCM2835_FSEL_ALT0>;
209 };
210 i2c1_gpio44: i2c1_gpio44 {
211 brcm,pins = <44 45>;
212 brcm,function = <BCM2835_FSEL_ALT2>;
213 };
214 i2c_slave_gpio18: i2c_slave_gpio18 {
215 brcm,pins = <18 19 20 21>;
216 brcm,function = <BCM2835_FSEL_ALT3>;
217 };
218
219 jtag_gpio4: jtag_gpio4 {
220 brcm,pins = <4 5 6 12 13>;
221 brcm,function = <BCM2835_FSEL_ALT4>;
222 };
223 jtag_gpio22: jtag_gpio22 {
224 brcm,pins = <22 23 24 25 26 27>;
225 brcm,function = <BCM2835_FSEL_ALT4>;
226 };
227
228 pcm_gpio18: pcm_gpio18 {
229 brcm,pins = <18 19 20 21>;
230 brcm,function = <BCM2835_FSEL_ALT0>;
231 };
232 pcm_gpio28: pcm_gpio28 {
233 brcm,pins = <28 29 30 31>;
234 brcm,function = <BCM2835_FSEL_ALT2>;
235 };
236
237 pwm0_gpio12: pwm0_gpio12 {
238 brcm,pins = <12>;
239 brcm,function = <BCM2835_FSEL_ALT0>;
240 };
241 pwm0_gpio18: pwm0_gpio18 {
242 brcm,pins = <18>;
243 brcm,function = <BCM2835_FSEL_ALT5>;
244 };
245 pwm0_gpio40: pwm0_gpio40 {
246 brcm,pins = <40>;
247 brcm,function = <BCM2835_FSEL_ALT0>;
248 };
249 pwm1_gpio13: pwm1_gpio13 {
250 brcm,pins = <13>;
251 brcm,function = <BCM2835_FSEL_ALT0>;
252 };
253 pwm1_gpio19: pwm1_gpio19 {
254 brcm,pins = <19>;
255 brcm,function = <BCM2835_FSEL_ALT5>;
256 };
257 pwm1_gpio41: pwm1_gpio41 {
258 brcm,pins = <41>;
259 brcm,function = <BCM2835_FSEL_ALT0>;
260 };
261 pwm1_gpio45: pwm1_gpio45 {
262 brcm,pins = <45>;
263 brcm,function = <BCM2835_FSEL_ALT0>;
264 };
265
266 sdhost_gpio48: sdhost_gpio48 {
267 brcm,pins = <48 49 50 51 52 53>;
268 brcm,function = <BCM2835_FSEL_ALT0>;
269 };
270
271 spi0_gpio7: spi0_gpio7 {
272 brcm,pins = <7 8 9 10 11>;
273 brcm,function = <BCM2835_FSEL_ALT0>;
274 };
275 spi0_gpio35: spi0_gpio35 {
276 brcm,pins = <35 36 37 38 39>;
277 brcm,function = <BCM2835_FSEL_ALT0>;
278 };
279 spi1_gpio16: spi1_gpio16 {
280 brcm,pins = <16 17 18 19 20 21>;
281 brcm,function = <BCM2835_FSEL_ALT4>;
282 };
283 spi2_gpio40: spi2_gpio40 {
284 brcm,pins = <40 41 42 43 44 45>;
285 brcm,function = <BCM2835_FSEL_ALT4>;
286 };
287
288 uart0_gpio14: uart0_gpio14 {
289 brcm,pins = <14 15>;
290 brcm,function = <BCM2835_FSEL_ALT0>;
291 };
292 /* Separate from the uart0_gpio14 group
293 * because it conflicts with spi1_gpio16, and
294 * people often run uart0 on the two pins
295 * without flow contrl.
296 */
297 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
298 brcm,pins = <16 17>;
299 brcm,function = <BCM2835_FSEL_ALT3>;
300 };
301 uart0_gpio30: uart0_gpio30 {
302 brcm,pins = <30 31>;
303 brcm,function = <BCM2835_FSEL_ALT3>;
304 };
305 uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
306 brcm,pins = <32 33>;
307 brcm,function = <BCM2835_FSEL_ALT3>;
308 };
309
310 uart1_gpio14: uart1_gpio14 {
311 brcm,pins = <14 15>;
312 brcm,function = <BCM2835_FSEL_ALT5>;
313 };
314 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
315 brcm,pins = <16 17>;
316 brcm,function = <BCM2835_FSEL_ALT5>;
317 };
318 uart1_gpio32: uart1_gpio32 {
319 brcm,pins = <32 33>;
320 brcm,function = <BCM2835_FSEL_ALT5>;
321 };
322 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
323 brcm,pins = <30 31>;
324 brcm,function = <BCM2835_FSEL_ALT5>;
325 };
326 uart1_gpio36: uart1_gpio36 {
327 brcm,pins = <36 37 38 39>;
328 brcm,function = <BCM2835_FSEL_ALT2>;
329 };
330 uart1_gpio40: uart1_gpio40 {
331 brcm,pins = <40 41>;
332 brcm,function = <BCM2835_FSEL_ALT5>;
333 };
334 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
335 brcm,pins = <42 43>;
336 brcm,function = <BCM2835_FSEL_ALT5>;
337 };
338 };
339
340 uart0: serial@7e201000 {
341 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
342 reg = <0x7e201000 0x1000>;
343 interrupts = <2 25>;
344 clocks = <&clocks BCM2835_CLOCK_UART>,
345 <&clocks BCM2835_CLOCK_VPU>;
346 clock-names = "uartclk", "apb_pclk";
347 arm,primecell-periphid = <0x00241011>;
348 };
349
350 i2s: i2s@7e203000 {
351 compatible = "brcm,bcm2835-i2s";
352 reg = <0x7e203000 0x20>,
353 <0x7e101098 0x02>;
354
355 dmas = <&dma 2>,
356 <&dma 3>;
357 dma-names = "tx", "rx";
358 status = "disabled";
359 };
360
361 spi: spi@7e204000 {
362 compatible = "brcm,bcm2835-spi";
363 reg = <0x7e204000 0x1000>;
364 interrupts = <2 22>;
365 clocks = <&clocks BCM2835_CLOCK_VPU>;
366 #address-cells = <1>;
367 #size-cells = <0>;
368 status = "disabled";
369 };
370
371 i2c0: i2c@7e205000 {
372 compatible = "brcm,bcm2835-i2c";
373 reg = <0x7e205000 0x1000>;
374 interrupts = <2 21>;
375 clocks = <&clocks BCM2835_CLOCK_VPU>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 status = "disabled";
379 };
380
381 pixelvalve@7e206000 {
382 compatible = "brcm,bcm2835-pixelvalve0";
383 reg = <0x7e206000 0x100>;
384 interrupts = <2 13>; /* pwa0 */
385 };
386
387 pixelvalve@7e207000 {
388 compatible = "brcm,bcm2835-pixelvalve1";
389 reg = <0x7e207000 0x100>;
390 interrupts = <2 14>; /* pwa1 */
391 };
392
393 thermal: thermal@7e212000 {
394 compatible = "brcm,bcm2835-thermal";
395 reg = <0x7e212000 0x8>;
396 clocks = <&clocks BCM2835_CLOCK_TSENS>;
397 status = "disabled";
398 };
399
400 aux: aux@0x7e215000 {
401 compatible = "brcm,bcm2835-aux";
402 #clock-cells = <1>;
403 reg = <0x7e215000 0x8>;
404 clocks = <&clocks BCM2835_CLOCK_VPU>;
405 };
406
407 uart1: serial@7e215040 {
408 compatible = "brcm,bcm2835-aux-uart";
409 reg = <0x7e215040 0x40>;
410 interrupts = <1 29>;
411 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
412 status = "disabled";
413 };
414
415 spi1: spi@7e215080 {
416 compatible = "brcm,bcm2835-aux-spi";
417 reg = <0x7e215080 0x40>;
418 interrupts = <1 29>;
419 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 status = "disabled";
423 };
424
425 spi2: spi@7e2150c0 {
426 compatible = "brcm,bcm2835-aux-spi";
427 reg = <0x7e2150c0 0x40>;
428 interrupts = <1 29>;
429 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 status = "disabled";
433 };
434
435 pwm: pwm@7e20c000 {
436 compatible = "brcm,bcm2835-pwm";
437 reg = <0x7e20c000 0x28>;
438 clocks = <&clocks BCM2835_CLOCK_PWM>;
439 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
440 assigned-clock-rates = <10000000>;
441 #pwm-cells = <2>;
442 status = "disabled";
443 };
444
445 sdhci: sdhci@7e300000 {
446 compatible = "brcm,bcm2835-sdhci";
447 reg = <0x7e300000 0x100>;
448 interrupts = <2 30>;
449 clocks = <&clocks BCM2835_CLOCK_EMMC>;
450 status = "disabled";
451 };
452
453 hvs@7e400000 {
454 compatible = "brcm,bcm2835-hvs";
455 reg = <0x7e400000 0x6000>;
456 interrupts = <2 1>;
457 };
458
459 i2c1: i2c@7e804000 {
460 compatible = "brcm,bcm2835-i2c";
461 reg = <0x7e804000 0x1000>;
462 interrupts = <2 21>;
463 clocks = <&clocks BCM2835_CLOCK_VPU>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 status = "disabled";
467 };
468
469 i2c2: i2c@7e805000 {
470 compatible = "brcm,bcm2835-i2c";
471 reg = <0x7e805000 0x1000>;
472 interrupts = <2 21>;
473 clocks = <&clocks BCM2835_CLOCK_VPU>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
479 pixelvalve@7e807000 {
480 compatible = "brcm,bcm2835-pixelvalve2";
481 reg = <0x7e807000 0x100>;
482 interrupts = <2 10>; /* pixelvalve */
483 };
484
485 hdmi: hdmi@7e902000 {
486 compatible = "brcm,bcm2835-hdmi";
487 reg = <0x7e902000 0x600>,
488 <0x7e808000 0x100>;
489 interrupts = <2 8>, <2 9>;
490 ddc = <&i2c2>;
491 clocks = <&clocks BCM2835_PLLH_PIX>,
492 <&clocks BCM2835_CLOCK_HSM>;
493 clock-names = "pixel", "hdmi";
494 status = "disabled";
495 };
496
497 usb: usb@7e980000 {
498 compatible = "brcm,bcm2835-usb";
499 reg = <0x7e980000 0x10000>;
500 interrupts = <1 9>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 clocks = <&clk_usb>;
504 clock-names = "otg";
505 };
506
507 v3d: v3d@7ec00000 {
508 compatible = "brcm,bcm2835-v3d";
509 reg = <0x7ec00000 0x1000>;
510 interrupts = <1 10>;
511 };
512
513 vc4: gpu {
514 compatible = "brcm,bcm2835-vc4";
515 };
516 };
517
518 clocks {
519 compatible = "simple-bus";
520 #address-cells = <1>;
521 #size-cells = <0>;
522
523 /* The oscillator is the root of the clock tree. */
524 clk_osc: clock@3 {
525 compatible = "fixed-clock";
526 reg = <3>;
527 #clock-cells = <0>;
528 clock-output-names = "osc";
529 clock-frequency = <19200000>;
530 };
531
532 clk_usb: clock@4 {
533 compatible = "fixed-clock";
534 reg = <4>;
535 #clock-cells = <0>;
536 clock-output-names = "otg";
537 clock-frequency = <480000000>;
538 };
539 };
540};