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1/* SPDX-License-Identifier: GPL-2.0+ */
2/* Copyright (C) 2018 Microchip Technology Inc. */
3
4#ifndef _LAN743X_H
5#define _LAN743X_H
6
7#define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
8#define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
9#define DRIVER_NAME "lan743x"
10
11/* Register Definitions */
12#define ID_REV (0x00)
13#define ID_REV_IS_VALID_CHIP_ID_(id_rev) \
14 (((id_rev) & 0xFFF00000) == 0x74300000)
15#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
16#define ID_REV_CHIP_REV_A0_ (0x00000000)
17#define ID_REV_CHIP_REV_B0_ (0x00000010)
18
19#define FPGA_REV (0x04)
20#define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
21#define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
22
23#define HW_CFG (0x010)
24#define HW_CFG_LRST_ BIT(1)
25
26#define PMT_CTL (0x014)
27#define PMT_CTL_READY_ BIT(7)
28#define PMT_CTL_ETH_PHY_RST_ BIT(4)
29
30#define DP_SEL (0x024)
31#define DP_SEL_DPRDY_ BIT(31)
32#define DP_SEL_MASK_ (0x0000001F)
33#define DP_SEL_RFE_RAM (0x00000001)
34
35#define DP_SEL_VHF_HASH_LEN (16)
36#define DP_SEL_VHF_VLAN_LEN (128)
37
38#define DP_CMD (0x028)
39#define DP_CMD_WRITE_ (0x00000001)
40
41#define DP_ADDR (0x02C)
42
43#define DP_DATA_0 (0x030)
44
45#define FCT_RX_CTL (0xAC)
46#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
47#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
48#define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel))
49
50#define FCT_TX_CTL (0xC4)
51#define FCT_TX_CTL_EN_(channel) BIT(28 + (channel))
52#define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel))
53#define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel))
54
55#define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
56#define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
57#define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \
58 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
59#define FCT_FLOW_CTL_REQ_EN_ BIT(7)
60#define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
61#define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \
62 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
63
64#define MAC_CR (0x100)
65#define MAC_CR_ADD_ BIT(12)
66#define MAC_CR_ASD_ BIT(11)
67#define MAC_CR_CNTR_RST_ BIT(5)
68#define MAC_CR_RST_ BIT(0)
69
70#define MAC_RX (0x104)
71#define MAC_RX_MAX_SIZE_SHIFT_ (16)
72#define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
73#define MAC_RX_RXD_ BIT(1)
74#define MAC_RX_RXEN_ BIT(0)
75
76#define MAC_TX (0x108)
77#define MAC_TX_TXD_ BIT(1)
78#define MAC_TX_TXEN_ BIT(0)
79
80#define MAC_FLOW (0x10C)
81#define MAC_FLOW_CR_TX_FCEN_ BIT(30)
82#define MAC_FLOW_CR_RX_FCEN_ BIT(29)
83#define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
84
85#define MAC_RX_ADDRH (0x118)
86
87#define MAC_RX_ADDRL (0x11C)
88
89#define MAC_MII_ACC (0x120)
90#define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
91#define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
92#define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)
93#define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
94#define MAC_MII_ACC_MII_READ_ (0x00000000)
95#define MAC_MII_ACC_MII_WRITE_ (0x00000002)
96#define MAC_MII_ACC_MII_BUSY_ BIT(0)
97
98#define MAC_MII_DATA (0x124)
99
100/* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
101#define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
102#define RFE_ADDR_FILT_HI_VALID_ BIT(31)
103
104/* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
105#define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
106
107#define RFE_CTL (0x508)
108#define RFE_CTL_AB_ BIT(10)
109#define RFE_CTL_AM_ BIT(9)
110#define RFE_CTL_AU_ BIT(8)
111#define RFE_CTL_MCAST_HASH_ BIT(3)
112#define RFE_CTL_DA_PERFECT_ BIT(1)
113
114#define INT_STS (0x780)
115#define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))
116#define INT_BIT_ALL_RX_ (0x0F000000)
117#define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))
118#define INT_BIT_ALL_TX_ (0x000F0000)
119#define INT_BIT_SW_GP_ BIT(9)
120#define INT_BIT_ALL_OTHER_ (0x00000280)
121#define INT_BIT_MAS_ BIT(0)
122
123#define INT_SET (0x784)
124
125#define INT_EN_SET (0x788)
126
127#define INT_EN_CLR (0x78C)
128
129#define INT_STS_R2C (0x790)
130
131#define INT_VEC_EN_SET (0x794)
132#define INT_VEC_EN_CLR (0x798)
133#define INT_VEC_EN_AUTO_CLR (0x79C)
134#define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
135
136#define INT_VEC_MAP0 (0x7A0)
137#define INT_VEC_MAP0_RX_VEC_(channel, vector) \
138 (((u32)(vector)) << ((channel) << 2))
139
140#define INT_VEC_MAP1 (0x7A4)
141#define INT_VEC_MAP1_TX_VEC_(channel, vector) \
142 (((u32)(vector)) << ((channel) << 2))
143
144#define INT_VEC_MAP2 (0x7A8)
145
146#define INT_MOD_MAP0 (0x7B0)
147
148#define INT_MOD_MAP1 (0x7B4)
149
150#define INT_MOD_MAP2 (0x7B8)
151
152#define INT_MOD_CFG0 (0x7C0)
153#define INT_MOD_CFG1 (0x7C4)
154#define INT_MOD_CFG2 (0x7C8)
155#define INT_MOD_CFG3 (0x7CC)
156#define INT_MOD_CFG4 (0x7D0)
157#define INT_MOD_CFG5 (0x7D4)
158#define INT_MOD_CFG6 (0x7D8)
159#define INT_MOD_CFG7 (0x7DC)
160
161#define DMAC_CFG (0xC00)
162#define DMAC_CFG_COAL_EN_ BIT(16)
163#define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
164#define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
165#define DMAC_CFG_MAX_READ_REQ_SET_(val) \
166 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
167#define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
168#define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
169#define DMAC_CFG_MAX_DSPACE_64_ BIT(1)
170#define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
171
172#define DMAC_COAL_CFG (0xC04)
173#define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
174#define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \
175 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
176#define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19)
177#define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18)
178#define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17)
179#define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16)
180#define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
181#define DMAC_COAL_CFG_TX_THRES_SET_(val) \
182 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
183#define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
184#define DMAC_COAL_CFG_RX_THRES_SET_(val) \
185 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
186
187#define DMAC_OBFF_CFG (0xC08)
188#define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
189#define DMAC_OBFF_TX_THRES_SET_(val) \
190 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
191#define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
192#define DMAC_OBFF_RX_THRES_SET_(val) \
193 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
194
195#define DMAC_CMD (0xC0C)
196#define DMAC_CMD_SWR_ BIT(31)
197#define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel))
198#define DMAC_CMD_START_T_(channel) BIT(20 + (channel))
199#define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel))
200#define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel))
201#define DMAC_CMD_START_R_(channel) BIT(4 + (channel))
202#define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
203
204#define DMAC_INT_STS (0xC10)
205#define DMAC_INT_EN_SET (0xC14)
206#define DMAC_INT_EN_CLR (0xC18)
207#define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel))
208#define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
209
210#define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
211#define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30)
212#define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
213#define RX_CFG_A_RX_WB_THRES_SET_(val) \
214 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
215#define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
216#define RX_CFG_A_RX_PF_THRES_SET_(val) \
217 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
218#define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
219#define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \
220 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
221#define RX_CFG_A_RX_HP_WB_EN_ BIT(5)
222
223#define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
224#define RX_CFG_B_TS_ALL_RX_ BIT(29)
225#define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
226#define RX_CFG_B_RX_PAD_0_ (0x00000000)
227#define RX_CFG_B_RX_PAD_2_ (0x02000000)
228#define RX_CFG_B_RDMABL_512_ (0x00040000)
229#define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
230
231#define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
232
233#define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
234
235#define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
236
237#define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
238
239#define RX_HEAD(channel) (0xC58 + ((channel) << 6))
240
241#define RX_TAIL(channel) (0xC5C + ((channel) << 6))
242#define RX_TAIL_SET_TOP_INT_EN_ BIT(30)
243#define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
244
245#define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
246#define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6)
247#define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)
248#define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3)
249#define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
250
251#define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
252#define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30)
253#define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
254#define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
255#define TX_CFG_A_TX_PF_THRES_SET_(value) \
256 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
257#define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
258#define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \
259 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
260#define TX_CFG_A_TX_HP_WB_EN_ BIT(5)
261#define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
262#define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \
263 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
264
265#define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
266#define TX_CFG_B_TDMABL_512_ (0x00040000)
267#define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
268
269#define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
270
271#define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
272
273#define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
274
275#define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
276
277#define TX_HEAD(channel) (0xD58 + ((channel) << 6))
278
279#define TX_TAIL(channel) (0xD5C + ((channel) << 6))
280#define TX_TAIL_SET_DMAC_INT_EN_ BIT(31)
281#define TX_TAIL_SET_TOP_INT_EN_ BIT(30)
282#define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
283
284#define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
285#define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6)
286#define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5)
287#define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)
288#define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)
289#define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
290
291/* MAC statistics registers */
292#define STAT_RX_FCS_ERRORS (0x1200)
293#define STAT_RX_ALIGNMENT_ERRORS (0x1204)
294#define STAT_RX_JABBER_ERRORS (0x120C)
295#define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
296#define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
297#define STAT_RX_DROPPED_FRAMES (0x1218)
298#define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
299#define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
300#define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
301#define STAT_RX_MULTICAST_FRAMES (0x1230)
302#define STAT_RX_TOTAL_FRAMES (0x1254)
303
304#define STAT_TX_FCS_ERRORS (0x1280)
305#define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
306#define STAT_TX_CARRIER_ERRORS (0x1288)
307#define STAT_TX_SINGLE_COLLISIONS (0x1290)
308#define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
309#define STAT_TX_EXCESSIVE_COLLISION (0x1298)
310#define STAT_TX_LATE_COLLISIONS (0x129C)
311#define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
312#define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
313#define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
314#define STAT_TX_MULTICAST_FRAMES (0x12B4)
315#define STAT_TX_TOTAL_FRAMES (0x12D8)
316
317/* End of Register definitions */
318
319#define LAN743X_MAX_RX_CHANNELS (4)
320#define LAN743X_MAX_TX_CHANNELS (1)
321struct lan743x_adapter;
322
323#define LAN743X_USED_RX_CHANNELS (4)
324#define LAN743X_USED_TX_CHANNELS (1)
325#define LAN743X_INT_MOD (400)
326
327#if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)
328#error Invalid LAN743X_USED_RX_CHANNELS
329#endif
330#if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)
331#error Invalid LAN743X_USED_TX_CHANNELS
332#endif
333
334/* PCI */
335/* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */
336#define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR
337#define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
338
339#define PCI_CONFIG_LENGTH (0x1000)
340
341/* CSR */
342#define CSR_LENGTH (0x2000)
343
344#define LAN743X_CSR_FLAG_IS_A0 BIT(0)
345#define LAN743X_CSR_FLAG_IS_B0 BIT(1)
346#define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8)
347
348struct lan743x_csr {
349 u32 flags;
350 u8 __iomem *csr_address;
351 u32 id_rev;
352 u32 fpga_rev;
353};
354
355/* INTERRUPTS */
356typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);
357
358#define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
359#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1)
360#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2)
361#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3)
362#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4)
363#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5)
364#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6)
365#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7)
366#define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8)
367#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9)
368#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10)
369#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11)
370#define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12)
371#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13)
372#define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14)
373#define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15)
374
375struct lan743x_vector {
376 int irq;
377 u32 flags;
378 struct lan743x_adapter *adapter;
379 int vector_index;
380 u32 int_mask;
381 lan743x_vector_handler handler;
382 void *context;
383};
384
385#define LAN743X_MAX_VECTOR_COUNT (8)
386
387struct lan743x_intr {
388 int flags;
389
390 unsigned int irq;
391
392 struct lan743x_vector vector_list[LAN743X_MAX_VECTOR_COUNT];
393 int number_of_vectors;
394 bool using_vectors;
395
396 int software_isr_flag;
397};
398
399#define LAN743X_MAX_FRAME_SIZE (9 * 1024)
400
401/* PHY */
402struct lan743x_phy {
403 bool fc_autoneg;
404 u8 fc_request_control;
405};
406
407/* TX */
408struct lan743x_tx_descriptor;
409struct lan743x_tx_buffer_info;
410
411#define GPIO_QUEUE_STARTED (0)
412#define GPIO_TX_FUNCTION (1)
413#define GPIO_TX_COMPLETION (2)
414#define GPIO_TX_FRAGMENT (3)
415
416#define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
417
418struct lan743x_tx {
419 struct lan743x_adapter *adapter;
420 u32 vector_flags;
421 int channel_number;
422
423 int ring_size;
424 size_t ring_allocation_size;
425 struct lan743x_tx_descriptor *ring_cpu_ptr;
426 dma_addr_t ring_dma_ptr;
427 /* ring_lock: used to prevent concurrent access to tx ring */
428 spinlock_t ring_lock;
429 u32 frame_flags;
430 u32 frame_first;
431 u32 frame_data0;
432 u32 frame_tail;
433
434 struct lan743x_tx_buffer_info *buffer_info;
435
436 u32 *head_cpu_ptr;
437 dma_addr_t head_dma_ptr;
438 int last_head;
439 int last_tail;
440
441 struct napi_struct napi;
442
443 struct sk_buff *overflow_skb;
444};
445
446/* RX */
447struct lan743x_rx_descriptor;
448struct lan743x_rx_buffer_info;
449
450struct lan743x_rx {
451 struct lan743x_adapter *adapter;
452 u32 vector_flags;
453 int channel_number;
454
455 int ring_size;
456 size_t ring_allocation_size;
457 struct lan743x_rx_descriptor *ring_cpu_ptr;
458 dma_addr_t ring_dma_ptr;
459
460 struct lan743x_rx_buffer_info *buffer_info;
461
462 u32 *head_cpu_ptr;
463 dma_addr_t head_dma_ptr;
464 u32 last_head;
465 u32 last_tail;
466
467 struct napi_struct napi;
468
469 u32 frame_count;
470};
471
472struct lan743x_adapter {
473 struct net_device *netdev;
474 struct mii_bus *mdiobus;
475 int msg_enable;
476 struct pci_dev *pdev;
477 struct lan743x_csr csr;
478 struct lan743x_intr intr;
479
480 /* lock, used to prevent concurrent access to data port */
481 struct mutex dp_lock;
482
483 u8 mac_address[ETH_ALEN];
484
485 struct lan743x_phy phy;
486 struct lan743x_tx tx[LAN743X_MAX_TX_CHANNELS];
487 struct lan743x_rx rx[LAN743X_MAX_RX_CHANNELS];
488};
489
490#define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel))
491
492#define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
493#define INTR_FLAG_MSI_ENABLED BIT(8)
494#define INTR_FLAG_MSIX_ENABLED BIT(9)
495
496#define MAC_MII_READ 1
497#define MAC_MII_WRITE 0
498
499#define PHY_FLAG_OPENED BIT(0)
500#define PHY_FLAG_ATTACHED BIT(1)
501
502#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
503#define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
504#else
505#define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
506#endif
507#define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
508#define DMA_DESCRIPTOR_SPACING_16 (16)
509#define DMA_DESCRIPTOR_SPACING_32 (32)
510#define DMA_DESCRIPTOR_SPACING_64 (64)
511#define DMA_DESCRIPTOR_SPACING_128 (128)
512#define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES)
513
514#define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \
515 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
516#define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
517#define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
518#define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)
519#define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
520
521/* TX Descriptor bits */
522#define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
523#define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
524#define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
525#define TX_DESC_DATA0_FS_ (0x20000000)
526#define TX_DESC_DATA0_LS_ (0x10000000)
527#define TX_DESC_DATA0_EXT_ (0x08000000)
528#define TX_DESC_DATA0_IOC_ (0x04000000)
529#define TX_DESC_DATA0_ICE_ (0x00400000)
530#define TX_DESC_DATA0_IPE_ (0x00200000)
531#define TX_DESC_DATA0_TPE_ (0x00100000)
532#define TX_DESC_DATA0_FCS_ (0x00020000)
533#define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
534#define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
535#define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
536#define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
537
538struct lan743x_tx_descriptor {
539 u32 data0;
540 u32 data1;
541 u32 data2;
542 u32 data3;
543} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
544
545#define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
546#define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)
547#define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3)
548struct lan743x_tx_buffer_info {
549 int flags;
550 struct sk_buff *skb;
551 dma_addr_t dma_ptr;
552 unsigned int buffer_length;
553};
554
555#define LAN743X_TX_RING_SIZE (50)
556
557/* OWN bit is set. ie, Descs are owned by RX DMAC */
558#define RX_DESC_DATA0_OWN_ (0x00008000)
559/* OWN bit is clear. ie, Descs are owned by host */
560#define RX_DESC_DATA0_FS_ (0x80000000)
561#define RX_DESC_DATA0_LS_ (0x40000000)
562#define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
563#define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \
564 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)
565#define RX_DESC_DATA0_EXT_ (0x00004000)
566#define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
567#define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
568
569#if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
570#error NET_IP_ALIGN must be 0 or 2
571#endif
572
573#define RX_HEAD_PADDING NET_IP_ALIGN
574
575struct lan743x_rx_descriptor {
576 u32 data0;
577 u32 data1;
578 u32 data2;
579 u32 data3;
580} __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
581
582#define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
583struct lan743x_rx_buffer_info {
584 int flags;
585 struct sk_buff *skb;
586
587 dma_addr_t dma_ptr;
588 unsigned int buffer_length;
589};
590
591#define LAN743X_RX_RING_SIZE (65)
592
593#define RX_PROCESS_RESULT_NOTHING_TO_DO (0)
594#define RX_PROCESS_RESULT_PACKET_RECEIVED (1)
595#define RX_PROCESS_RESULT_PACKET_DROPPED (2)
596
597#endif /* _LAN743X_H */