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1// SPDX-License-Identifier: GPL-2.0
2/* Register definitions for Gemini GMAC Ethernet device driver
3 *
4 * Copyright (C) 2006 Storlink, Corp.
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
7 * Copytight (C) 2017 Linus Walleij <linus.walleij@linaro.org>
8 */
9#ifndef _GEMINI_ETHERNET_H
10#define _GEMINI_ETHERNET_H
11
12#include <linux/bitops.h>
13
14/* Base Registers */
15#define TOE_NONTOE_QUE_HDR_BASE 0x2000
16#define TOE_TOE_QUE_HDR_BASE 0x3000
17
18/* Queue ID */
19#define TOE_SW_FREE_QID 0x00
20#define TOE_HW_FREE_QID 0x01
21#define TOE_GMAC0_SW_TXQ0_QID 0x02
22#define TOE_GMAC0_SW_TXQ1_QID 0x03
23#define TOE_GMAC0_SW_TXQ2_QID 0x04
24#define TOE_GMAC0_SW_TXQ3_QID 0x05
25#define TOE_GMAC0_SW_TXQ4_QID 0x06
26#define TOE_GMAC0_SW_TXQ5_QID 0x07
27#define TOE_GMAC0_HW_TXQ0_QID 0x08
28#define TOE_GMAC0_HW_TXQ1_QID 0x09
29#define TOE_GMAC0_HW_TXQ2_QID 0x0A
30#define TOE_GMAC0_HW_TXQ3_QID 0x0B
31#define TOE_GMAC1_SW_TXQ0_QID 0x12
32#define TOE_GMAC1_SW_TXQ1_QID 0x13
33#define TOE_GMAC1_SW_TXQ2_QID 0x14
34#define TOE_GMAC1_SW_TXQ3_QID 0x15
35#define TOE_GMAC1_SW_TXQ4_QID 0x16
36#define TOE_GMAC1_SW_TXQ5_QID 0x17
37#define TOE_GMAC1_HW_TXQ0_QID 0x18
38#define TOE_GMAC1_HW_TXQ1_QID 0x19
39#define TOE_GMAC1_HW_TXQ2_QID 0x1A
40#define TOE_GMAC1_HW_TXQ3_QID 0x1B
41#define TOE_GMAC0_DEFAULT_QID 0x20
42#define TOE_GMAC1_DEFAULT_QID 0x21
43#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */
44#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */
45
46/* TOE DMA Queue Size should be 2^n, n = 6...12
47 * TOE DMA Queues are the following queue types:
48 * SW Free Queue, HW Free Queue,
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
50 * The base address and descriptor number are configured at
51 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
52 */
53#define GET_WPTR(addr) readw((addr) + 2)
54#define GET_RPTR(addr) readw((addr))
55#define SET_WPTR(addr, data) writew((data), (addr) + 2)
56#define SET_RPTR(addr, data) writew((data), (addr))
57#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
58#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60#define __RWPTR_MASK(order) ((1 << (order)) - 1)
61#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order)))
62#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order)))
63#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \
64 __RWPTR_MASK((order)))
65
66/* Global registers */
67#define GLOBAL_TOE_VERSION_REG 0x0000
68#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
69#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
70#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
71#define GLOBAL_SWFQ_RWPTR_REG 0x0014
72#define GLOBAL_HWFQ_RWPTR_REG 0x0018
73#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
74#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
75#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
76#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
77#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
78#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
79#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
80#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
81#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
82#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
83#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
84#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
85#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
86#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
87#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
88#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
89#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
90
91/* GMAC 0/1 DMA/TOE register */
92#define GMAC_DMA_CTRL_REG 0x0000
93#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
94#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
95#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
96#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
97#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
98#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
99#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
100#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
101#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
102#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
103#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
104#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
105#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
106#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
107#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
108#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
109#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
110#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
111#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
112#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
113#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
114#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
115#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
116#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
117#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
118#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
119#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
120#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
121#define GMAC_HASH_ENGINE_REG0 0x0070
122#define GMAC_HASH_ENGINE_REG1 0x0074
123/* matching rule 0 Control register 0 */
124#define GMAC_MR0CR0 0x0078
125#define GMAC_MR0CR1 0x007C
126#define GMAC_MR0CR2 0x0080
127#define GMAC_MR1CR0 0x0084
128#define GMAC_MR1CR1 0x0088
129#define GMAC_MR1CR2 0x008C
130#define GMAC_MR2CR0 0x0090
131#define GMAC_MR2CR1 0x0094
132#define GMAC_MR2CR2 0x0098
133#define GMAC_MR3CR0 0x009C
134#define GMAC_MR3CR1 0x00A0
135#define GMAC_MR3CR2 0x00A4
136/* Support Protocol Register 0 */
137#define GMAC_SPR0 0x00A8
138#define GMAC_SPR1 0x00AC
139#define GMAC_SPR2 0x00B0
140#define GMAC_SPR3 0x00B4
141#define GMAC_SPR4 0x00B8
142#define GMAC_SPR5 0x00BC
143#define GMAC_SPR6 0x00C0
144#define GMAC_SPR7 0x00C4
145/* GMAC Hash/Rx/Tx AHB Weighting register */
146#define GMAC_AHB_WEIGHT_REG 0x00C8
147
148/* TOE GMAC 0/1 register */
149#define GMAC_STA_ADD0 0x0000
150#define GMAC_STA_ADD1 0x0004
151#define GMAC_STA_ADD2 0x0008
152#define GMAC_RX_FLTR 0x000c
153#define GMAC_MCAST_FIL0 0x0010
154#define GMAC_MCAST_FIL1 0x0014
155#define GMAC_CONFIG0 0x0018
156#define GMAC_CONFIG1 0x001c
157#define GMAC_CONFIG2 0x0020
158#define GMAC_CONFIG3 0x0024
159#define GMAC_RESERVED 0x0028
160#define GMAC_STATUS 0x002c
161#define GMAC_IN_DISCARDS 0x0030
162#define GMAC_IN_ERRORS 0x0034
163#define GMAC_IN_MCAST 0x0038
164#define GMAC_IN_BCAST 0x003c
165#define GMAC_IN_MAC1 0x0040 /* for STA 1 MAC Address */
166#define GMAC_IN_MAC2 0x0044 /* for STA 2 MAC Address */
167
168#define RX_STATS_NUM 6
169
170/* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */
171union dma_q_base_size {
172 unsigned int bits32;
173 unsigned int base_size;
174};
175
176#define DMA_Q_BASE_MASK (~0x0f)
177
178/* DMA SKB Buffer register (offset 0x0008) */
179union dma_skb_size {
180 unsigned int bits32;
181 struct bit_0008 {
182 unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
183 unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
184 } bits;
185};
186
187/* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */
188union dma_rwptr {
189 unsigned int bits32;
190 struct bit_000c {
191 unsigned int rptr : 16; /* Read Ptr, RO */
192 unsigned int wptr : 16; /* Write Ptr, RW */
193 } bits;
194};
195
196/* Interrupt Status Register 0 (offset 0x0020)
197 * Interrupt Mask Register 0 (offset 0x0024)
198 * Interrupt Select Register 0 (offset 0x0028)
199 */
200#define GMAC1_TXDERR_INT_BIT BIT(31)
201#define GMAC1_TXPERR_INT_BIT BIT(30)
202#define GMAC0_TXDERR_INT_BIT BIT(29)
203#define GMAC0_TXPERR_INT_BIT BIT(28)
204#define GMAC1_RXDERR_INT_BIT BIT(27)
205#define GMAC1_RXPERR_INT_BIT BIT(26)
206#define GMAC0_RXDERR_INT_BIT BIT(25)
207#define GMAC0_RXPERR_INT_BIT BIT(24)
208#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
209#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
210#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
211#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
212#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
213#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
214#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
215#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
216#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
217#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
218#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
219#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
220#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
221#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
222#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
223#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
224#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
225#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
226#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
227#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
228#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
229#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
230#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
231#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
232
233/* Interrupt Status Register 1 (offset 0x0030)
234 * Interrupt Mask Register 1 (offset 0x0034)
235 * Interrupt Select Register 1 (offset 0x0038)
236 */
237#define TOE_IQ3_FULL_INT_BIT BIT(31)
238#define TOE_IQ2_FULL_INT_BIT BIT(30)
239#define TOE_IQ1_FULL_INT_BIT BIT(29)
240#define TOE_IQ0_FULL_INT_BIT BIT(28)
241#define TOE_IQ3_INT_BIT BIT(27)
242#define TOE_IQ2_INT_BIT BIT(26)
243#define TOE_IQ1_INT_BIT BIT(25)
244#define TOE_IQ0_INT_BIT BIT(24)
245#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
246#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
247#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
248#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
249#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
250#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
251#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
252#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
253#define CLASS_RX_INT_BIT(x) BIT((x + 2))
254#define DEFAULT_Q1_INT_BIT BIT(1)
255#define DEFAULT_Q0_INT_BIT BIT(0)
256
257#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
258 TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
259#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
260 TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
261#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
262#define TOE_CLASS_RX_INT_BITS 0xfffc
263
264/* Interrupt Status Register 2 (offset 0x0040)
265 * Interrupt Mask Register 2 (offset 0x0044)
266 * Interrupt Select Register 2 (offset 0x0048)
267 */
268#define TOE_QL_FULL_INT_BIT(x) BIT(x)
269
270/* Interrupt Status Register 3 (offset 0x0050)
271 * Interrupt Mask Register 3 (offset 0x0054)
272 * Interrupt Select Register 3 (offset 0x0058)
273 */
274#define TOE_QH_FULL_INT_BIT(x) BIT(x - 32)
275
276/* Interrupt Status Register 4 (offset 0x0060)
277 * Interrupt Mask Register 4 (offset 0x0064)
278 * Interrupt Select Register 4 (offset 0x0068)
279 */
280#define GMAC1_RESERVED_INT_BIT BIT(31)
281#define GMAC1_MIB_INT_BIT BIT(30)
282#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
283#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
284#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
285#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
286#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
287#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
288#define GMAC0_RESERVED_INT_BIT BIT(23)
289#define GMAC0_MIB_INT_BIT BIT(22)
290#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
291#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
292#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
293#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
294#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
295#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
296#define CLASS_RX_FULL_INT_BIT(x) BIT(x + 2)
297#define HWFQ_EMPTY_INT_BIT BIT(1)
298#define SWFQ_EMPTY_INT_BIT BIT(0)
299
300#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
301 GMAC0_RX_PAUSE_ON_INT_BIT | \
302 GMAC0_TX_PAUSE_ON_INT_BIT | \
303 GMAC0_RX_PAUSE_OFF_INT_BIT | \
304 GMAC0_TX_PAUSE_OFF_INT_BIT | \
305 GMAC0_RX_OVERRUN_INT_BIT | \
306 GMAC0_STATUS_CHANGE_INT_BIT)
307#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
308 GMAC1_RX_PAUSE_ON_INT_BIT | \
309 GMAC1_TX_PAUSE_ON_INT_BIT | \
310 GMAC1_RX_PAUSE_OFF_INT_BIT | \
311 GMAC1_TX_PAUSE_OFF_INT_BIT | \
312 GMAC1_RX_OVERRUN_INT_BIT | \
313 GMAC1_STATUS_CHANGE_INT_BIT)
314
315#define CLASS_RX_FULL_INT_BITS 0xfffc
316
317/* GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) */
318union queue_threshold {
319 unsigned int bits32;
320 struct bit_0070_2 {
321 /* 7:0 Software Free Queue Empty Threshold */
322 unsigned int swfq_empty:8;
323 /* 15:8 Hardware Free Queue Empty Threshold */
324 unsigned int hwfq_empty:8;
325 /* 23:16 */
326 unsigned int intrq:8;
327 /* 31:24 */
328 unsigned int toe_class:8;
329 } bits;
330};
331
332/* GMAC DMA Control Register
333 * GMAC0 offset 0x8000
334 * GMAC1 offset 0xC000
335 */
336union gmac_dma_ctrl {
337 unsigned int bits32;
338 struct bit_8000 {
339 /* bit 1:0 Peripheral Bus Width */
340 unsigned int td_bus:2;
341 /* bit 3:2 TxDMA max burst size for every AHB request */
342 unsigned int td_burst_size:2;
343 /* bit 7:4 TxDMA protection control */
344 unsigned int td_prot:4;
345 /* bit 9:8 Peripheral Bus Width */
346 unsigned int rd_bus:2;
347 /* bit 11:10 DMA max burst size for every AHB request */
348 unsigned int rd_burst_size:2;
349 /* bit 15:12 DMA Protection Control */
350 unsigned int rd_prot:4;
351 /* bit 17:16 */
352 unsigned int rd_insert_bytes:2;
353 /* bit 27:18 */
354 unsigned int reserved:10;
355 /* bit 28 1: Drop, 0: Accept */
356 unsigned int drop_small_ack:1;
357 /* bit 29 Loopback TxDMA to RxDMA */
358 unsigned int loopback:1;
359 /* bit 30 Tx DMA Enable */
360 unsigned int td_enable:1;
361 /* bit 31 Rx DMA Enable */
362 unsigned int rd_enable:1;
363 } bits;
364};
365
366/* GMAC Tx Weighting Control Register 0
367 * GMAC0 offset 0x8004
368 * GMAC1 offset 0xC004
369 */
370union gmac_tx_wcr0 {
371 unsigned int bits32;
372 struct bit_8004 {
373 /* bit 5:0 HW TX Queue 3 */
374 unsigned int hw_tq0:6;
375 /* bit 11:6 HW TX Queue 2 */
376 unsigned int hw_tq1:6;
377 /* bit 17:12 HW TX Queue 1 */
378 unsigned int hw_tq2:6;
379 /* bit 23:18 HW TX Queue 0 */
380 unsigned int hw_tq3:6;
381 /* bit 31:24 */
382 unsigned int reserved:8;
383 } bits;
384};
385
386/* GMAC Tx Weighting Control Register 1
387 * GMAC0 offset 0x8008
388 * GMAC1 offset 0xC008
389 */
390union gmac_tx_wcr1 {
391 unsigned int bits32;
392 struct bit_8008 {
393 /* bit 4:0 SW TX Queue 0 */
394 unsigned int sw_tq0:5;
395 /* bit 9:5 SW TX Queue 1 */
396 unsigned int sw_tq1:5;
397 /* bit 14:10 SW TX Queue 2 */
398 unsigned int sw_tq2:5;
399 /* bit 19:15 SW TX Queue 3 */
400 unsigned int sw_tq3:5;
401 /* bit 24:20 SW TX Queue 4 */
402 unsigned int sw_tq4:5;
403 /* bit 29:25 SW TX Queue 5 */
404 unsigned int sw_tq5:5;
405 /* bit 31:30 */
406 unsigned int reserved:2;
407 } bits;
408};
409
410/* GMAC DMA Tx Description Word 0 Register
411 * GMAC0 offset 0x8040
412 * GMAC1 offset 0xC040
413 */
414union gmac_txdesc_0 {
415 unsigned int bits32;
416 struct bit_8040 {
417 /* bit 15:0 Transfer size */
418 unsigned int buffer_size:16;
419 /* bit 21:16 number of descriptors used for the current frame */
420 unsigned int desc_count:6;
421 /* bit 22 Tx Status, 1: Successful 0: Failed */
422 unsigned int status_tx_ok:1;
423 /* bit 28:23 Tx Status, Reserved bits */
424 unsigned int status_rvd:6;
425 /* bit 29 protocol error during processing this descriptor */
426 unsigned int perr:1;
427 /* bit 30 data error during processing this descriptor */
428 unsigned int derr:1;
429 /* bit 31 */
430 unsigned int reserved:1;
431 } bits;
432};
433
434/* GMAC DMA Tx Description Word 1 Register
435 * GMAC0 offset 0x8044
436 * GMAC1 offset 0xC044
437 */
438union gmac_txdesc_1 {
439 unsigned int bits32;
440 struct txdesc_word1 {
441 /* bit 15: 0 Tx Frame Byte Count */
442 unsigned int byte_count:16;
443 /* bit 16 TSS segmentation use MTU setting */
444 unsigned int mtu_enable:1;
445 /* bit 17 IPV4 Header Checksum Enable */
446 unsigned int ip_chksum:1;
447 /* bit 18 IPV6 Tx Enable */
448 unsigned int ipv6_enable:1;
449 /* bit 19 TCP Checksum Enable */
450 unsigned int tcp_chksum:1;
451 /* bit 20 UDP Checksum Enable */
452 unsigned int udp_chksum:1;
453 /* bit 21 Bypass HW offload engine */
454 unsigned int bypass_tss:1;
455 /* bit 22 Don't update IP length field */
456 unsigned int ip_fixed_len:1;
457 /* bit 31:23 Tx Flag, Reserved */
458 unsigned int reserved:9;
459 } bits;
460};
461
462#define TSS_IP_FIXED_LEN_BIT BIT(22)
463#define TSS_BYPASS_BIT BIT(21)
464#define TSS_UDP_CHKSUM_BIT BIT(20)
465#define TSS_TCP_CHKSUM_BIT BIT(19)
466#define TSS_IPV6_ENABLE_BIT BIT(18)
467#define TSS_IP_CHKSUM_BIT BIT(17)
468#define TSS_MTU_ENABLE_BIT BIT(16)
469
470#define TSS_CHECKUM_ENABLE \
471 (TSS_IP_CHKSUM_BIT | TSS_IPV6_ENABLE_BIT | \
472 TSS_TCP_CHKSUM_BIT | TSS_UDP_CHKSUM_BIT)
473
474/* GMAC DMA Tx Description Word 2 Register
475 * GMAC0 offset 0x8048
476 * GMAC1 offset 0xC048
477 */
478union gmac_txdesc_2 {
479 unsigned int bits32;
480 unsigned int buf_adr;
481};
482
483/* GMAC DMA Tx Description Word 3 Register
484 * GMAC0 offset 0x804C
485 * GMAC1 offset 0xC04C
486 */
487union gmac_txdesc_3 {
488 unsigned int bits32;
489 struct txdesc_word3 {
490 /* bit 12: 0 Tx Frame Byte Count */
491 unsigned int mtu_size:13;
492 /* bit 28:13 */
493 unsigned int reserved:16;
494 /* bit 29 End of frame interrupt enable */
495 unsigned int eofie:1;
496 /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
497 unsigned int sof_eof:2;
498 } bits;
499};
500
501#define SOF_EOF_BIT_MASK 0x3fffffff
502#define SOF_BIT 0x80000000
503#define EOF_BIT 0x40000000
504#define EOFIE_BIT BIT(29)
505#define MTU_SIZE_BIT_MASK 0x1fff
506
507/* GMAC Tx Descriptor */
508struct gmac_txdesc {
509 union gmac_txdesc_0 word0;
510 union gmac_txdesc_1 word1;
511 union gmac_txdesc_2 word2;
512 union gmac_txdesc_3 word3;
513};
514
515/* GMAC DMA Rx Description Word 0 Register
516 * GMAC0 offset 0x8060
517 * GMAC1 offset 0xC060
518 */
519union gmac_rxdesc_0 {
520 unsigned int bits32;
521 struct bit_8060 {
522 /* bit 15:0 number of descriptors used for the current frame */
523 unsigned int buffer_size:16;
524 /* bit 21:16 number of descriptors used for the current frame */
525 unsigned int desc_count:6;
526 /* bit 24:22 Status of rx frame */
527 unsigned int status:4;
528 /* bit 28:26 Check Sum Status */
529 unsigned int chksum_status:3;
530 /* bit 29 protocol error during processing this descriptor */
531 unsigned int perr:1;
532 /* bit 30 data error during processing this descriptor */
533 unsigned int derr:1;
534 /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
535 unsigned int drop:1;
536 } bits;
537};
538
539#define GMAC_RXDESC_0_T_derr BIT(30)
540#define GMAC_RXDESC_0_T_perr BIT(29)
541#define GMAC_RXDESC_0_T_chksum_status(x) BIT(x + 26)
542#define GMAC_RXDESC_0_T_status(x) BIT(x + 22)
543#define GMAC_RXDESC_0_T_desc_count(x) BIT(x + 16)
544
545#define RX_CHKSUM_IP_UDP_TCP_OK 0
546#define RX_CHKSUM_IP_OK_ONLY 1
547#define RX_CHKSUM_NONE 2
548#define RX_CHKSUM_IP_ERR_UNKNOWN 4
549#define RX_CHKSUM_IP_ERR 5
550#define RX_CHKSUM_TCP_UDP_ERR 6
551#define RX_CHKSUM_NUM 8
552
553#define RX_STATUS_GOOD_FRAME 0
554#define RX_STATUS_TOO_LONG_GOOD_CRC 1
555#define RX_STATUS_RUNT_FRAME 2
556#define RX_STATUS_SFD_NOT_FOUND 3
557#define RX_STATUS_CRC_ERROR 4
558#define RX_STATUS_TOO_LONG_BAD_CRC 5
559#define RX_STATUS_ALIGNMENT_ERROR 6
560#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
561#define RX_STATUS_RX_ERR 8
562#define RX_STATUS_DA_FILTERED 9
563#define RX_STATUS_BUFFER_FULL 10
564#define RX_STATUS_NUM 16
565
566#define RX_ERROR_LENGTH(s) \
567 ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
568 (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
569 (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
570#define RX_ERROR_OVER(s) \
571 ((s) == RX_STATUS_BUFFER_FULL)
572#define RX_ERROR_CRC(s) \
573 ((s) == RX_STATUS_CRC_ERROR || \
574 (s) == RX_STATUS_TOO_LONG_BAD_CRC)
575#define RX_ERROR_FRAME(s) \
576 ((s) == RX_STATUS_ALIGNMENT_ERROR || \
577 (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
578#define RX_ERROR_FIFO(s) \
579 (0)
580
581/* GMAC DMA Rx Description Word 1 Register
582 * GMAC0 offset 0x8064
583 * GMAC1 offset 0xC064
584 */
585union gmac_rxdesc_1 {
586 unsigned int bits32;
587 struct rxdesc_word1 {
588 /* bit 15: 0 Rx Frame Byte Count */
589 unsigned int byte_count:16;
590 /* bit 31:16 Software ID */
591 unsigned int sw_id:16;
592 } bits;
593};
594
595/* GMAC DMA Rx Description Word 2 Register
596 * GMAC0 offset 0x8068
597 * GMAC1 offset 0xC068
598 */
599union gmac_rxdesc_2 {
600 unsigned int bits32;
601 unsigned int buf_adr;
602};
603
604#define RX_INSERT_NONE 0
605#define RX_INSERT_1_BYTE 1
606#define RX_INSERT_2_BYTE 2
607#define RX_INSERT_3_BYTE 3
608
609/* GMAC DMA Rx Description Word 3 Register
610 * GMAC0 offset 0x806C
611 * GMAC1 offset 0xC06C
612 */
613union gmac_rxdesc_3 {
614 unsigned int bits32;
615 struct rxdesc_word3 {
616 /* bit 7: 0 L3 data offset */
617 unsigned int l3_offset:8;
618 /* bit 15: 8 L4 data offset */
619 unsigned int l4_offset:8;
620 /* bit 23: 16 L7 data offset */
621 unsigned int l7_offset:8;
622 /* bit 24 Duplicated ACK detected */
623 unsigned int dup_ack:1;
624 /* bit 25 abnormal case found */
625 unsigned int abnormal:1;
626 /* bit 26 IPV4 option or IPV6 extension header */
627 unsigned int option:1;
628 /* bit 27 Out of Sequence packet */
629 unsigned int out_of_seq:1;
630 /* bit 28 Control Flag is present */
631 unsigned int ctrl_flag:1;
632 /* bit 29 End of frame interrupt enable */
633 unsigned int eofie:1;
634 /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
635 unsigned int sof_eof:2;
636 } bits;
637};
638
639/* GMAC Rx Descriptor, this is simply fitted over the queue registers */
640struct gmac_rxdesc {
641 union gmac_rxdesc_0 word0;
642 union gmac_rxdesc_1 word1;
643 union gmac_rxdesc_2 word2;
644 union gmac_rxdesc_3 word3;
645};
646
647/* GMAC Matching Rule Control Register 0
648 * GMAC0 offset 0x8078
649 * GMAC1 offset 0xC078
650 */
651#define MR_L2_BIT BIT(31)
652#define MR_L3_BIT BIT(30)
653#define MR_L4_BIT BIT(29)
654#define MR_L7_BIT BIT(28)
655#define MR_PORT_BIT BIT(27)
656#define MR_PRIORITY_BIT BIT(26)
657#define MR_DA_BIT BIT(23)
658#define MR_SA_BIT BIT(22)
659#define MR_ETHER_TYPE_BIT BIT(21)
660#define MR_VLAN_BIT BIT(20)
661#define MR_PPPOE_BIT BIT(19)
662#define MR_IP_VER_BIT BIT(15)
663#define MR_IP_HDR_LEN_BIT BIT(14)
664#define MR_FLOW_LABLE_BIT BIT(13)
665#define MR_TOS_TRAFFIC_BIT BIT(12)
666#define MR_SPR_BIT(x) BIT(x)
667#define MR_SPR_BITS 0xff
668
669/* GMAC_AHB_WEIGHT registers
670 * GMAC0 offset 0x80C8
671 * GMAC1 offset 0xC0C8
672 */
673union gmac_ahb_weight {
674 unsigned int bits32;
675 struct bit_80C8 {
676 /* 4:0 */
677 unsigned int hash_weight:5;
678 /* 9:5 */
679 unsigned int rx_weight:5;
680 /* 14:10 */
681 unsigned int tx_weight:5;
682 /* 19:15 Rx Data Pre Request FIFO Threshold */
683 unsigned int pre_req:5;
684 /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
685 unsigned int tq_dv_threshold:5;
686 /* 31:25 */
687 unsigned int reserved:7;
688 } bits;
689};
690
691/* GMAC RX FLTR
692 * GMAC0 Offset 0xA00C
693 * GMAC1 Offset 0xE00C
694 */
695union gmac_rx_fltr {
696 unsigned int bits32;
697 struct bit1_000c {
698 /* Enable receive of unicast frames that are sent to STA
699 * address
700 */
701 unsigned int unicast:1;
702 /* Enable receive of multicast frames that pass multicast
703 * filter
704 */
705 unsigned int multicast:1;
706 /* Enable receive of broadcast frames */
707 unsigned int broadcast:1;
708 /* Enable receive of all frames */
709 unsigned int promiscuous:1;
710 /* Enable receive of all error frames */
711 unsigned int error:1;
712 unsigned int reserved:27;
713 } bits;
714};
715
716/* GMAC Configuration 0
717 * GMAC0 Offset 0xA018
718 * GMAC1 Offset 0xE018
719 */
720union gmac_config0 {
721 unsigned int bits32;
722 struct bit1_0018 {
723 /* 0: disable transmit */
724 unsigned int dis_tx:1;
725 /* 1: disable receive */
726 unsigned int dis_rx:1;
727 /* 2: transmit data loopback enable */
728 unsigned int loop_back:1;
729 /* 3: flow control also trigged by Rx queues */
730 unsigned int flow_ctrl:1;
731 /* 4-7: adjust IFG from 96+/-56 */
732 unsigned int adj_ifg:4;
733 /* 8-10 maximum receive frame length allowed */
734 unsigned int max_len:3;
735 /* 11: disable back-off function */
736 unsigned int dis_bkoff:1;
737 /* 12: disable 16 collisions abort function */
738 unsigned int dis_col:1;
739 /* 13: speed up timers in simulation */
740 unsigned int sim_test:1;
741 /* 14: RX flow control enable */
742 unsigned int rx_fc_en:1;
743 /* 15: TX flow control enable */
744 unsigned int tx_fc_en:1;
745 /* 16: RGMII in-band status enable */
746 unsigned int rgmii_en:1;
747 /* 17: IPv4 RX Checksum enable */
748 unsigned int ipv4_rx_chksum:1;
749 /* 18: IPv6 RX Checksum enable */
750 unsigned int ipv6_rx_chksum:1;
751 /* 19: Remove Rx VLAN tag */
752 unsigned int rx_tag_remove:1;
753 /* 20 */
754 unsigned int rgmm_edge:1;
755 /* 21 */
756 unsigned int rxc_inv:1;
757 /* 22 */
758 unsigned int ipv6_exthdr_order:1;
759 /* 23 */
760 unsigned int rx_err_detect:1;
761 /* 24 */
762 unsigned int port0_chk_hwq:1;
763 /* 25 */
764 unsigned int port1_chk_hwq:1;
765 /* 26 */
766 unsigned int port0_chk_toeq:1;
767 /* 27 */
768 unsigned int port1_chk_toeq:1;
769 /* 28 */
770 unsigned int port0_chk_classq:1;
771 /* 29 */
772 unsigned int port1_chk_classq:1;
773 /* 30, 31 */
774 unsigned int reserved:2;
775 } bits;
776};
777
778#define CONFIG0_TX_RX_DISABLE (BIT(1) | BIT(0))
779#define CONFIG0_RX_CHKSUM (BIT(18) | BIT(17))
780#define CONFIG0_FLOW_RX BIT(14)
781#define CONFIG0_FLOW_TX BIT(15)
782#define CONFIG0_FLOW_TX_RX (BIT(14) | BIT(15))
783#define CONFIG0_FLOW_CTL (BIT(14) | BIT(15))
784
785#define CONFIG0_MAXLEN_SHIFT 8
786#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT)
787#define CONFIG0_MAXLEN_1536 0
788#define CONFIG0_MAXLEN_1518 1
789#define CONFIG0_MAXLEN_1522 2
790#define CONFIG0_MAXLEN_1542 3
791#define CONFIG0_MAXLEN_9k 4 /* 9212 */
792#define CONFIG0_MAXLEN_10k 5 /* 10236 */
793#define CONFIG0_MAXLEN_1518__6 6
794#define CONFIG0_MAXLEN_1518__7 7
795
796/* GMAC Configuration 1
797 * GMAC0 Offset 0xA01C
798 * GMAC1 Offset 0xE01C
799 */
800union gmac_config1 {
801 unsigned int bits32;
802 struct bit1_001c {
803 /* Flow control set threshold */
804 unsigned int set_threshold:8;
805 /* Flow control release threshold */
806 unsigned int rel_threshold:8;
807 unsigned int reserved:16;
808 } bits;
809};
810
811#define GMAC_FLOWCTRL_SET_MAX 32
812#define GMAC_FLOWCTRL_SET_MIN 0
813#define GMAC_FLOWCTRL_RELEASE_MAX 32
814#define GMAC_FLOWCTRL_RELEASE_MIN 0
815
816/* GMAC Configuration 2
817 * GMAC0 Offset 0xA020
818 * GMAC1 Offset 0xE020
819 */
820union gmac_config2 {
821 unsigned int bits32;
822 struct bit1_0020 {
823 /* Flow control set threshold */
824 unsigned int set_threshold:16;
825 /* Flow control release threshold */
826 unsigned int rel_threshold:16;
827 } bits;
828};
829
830/* GMAC Configuration 3
831 * GMAC0 Offset 0xA024
832 * GMAC1 Offset 0xE024
833 */
834union gmac_config3 {
835 unsigned int bits32;
836 struct bit1_0024 {
837 /* Flow control set threshold */
838 unsigned int set_threshold:16;
839 /* Flow control release threshold */
840 unsigned int rel_threshold:16;
841 } bits;
842};
843
844/* GMAC STATUS
845 * GMAC0 Offset 0xA02C
846 * GMAC1 Offset 0xE02C
847 */
848union gmac_status {
849 unsigned int bits32;
850 struct bit1_002c {
851 /* Link status */
852 unsigned int link:1;
853 /* Link speed(00->2.5M 01->25M 10->125M) */
854 unsigned int speed:2;
855 /* Duplex mode */
856 unsigned int duplex:1;
857 unsigned int reserved_1:1;
858 /* PHY interface type */
859 unsigned int mii_rmii:2;
860 unsigned int reserved_2:25;
861 } bits;
862};
863
864#define GMAC_SPEED_10 0
865#define GMAC_SPEED_100 1
866#define GMAC_SPEED_1000 2
867
868#define GMAC_PHY_MII 0
869#define GMAC_PHY_GMII 1
870#define GMAC_PHY_RGMII_100_10 2
871#define GMAC_PHY_RGMII_1000 3
872
873/* Queue Header
874 * (1) TOE Queue Header
875 * (2) Non-TOE Queue Header
876 * (3) Interrupt Queue Header
877 *
878 * memory Layout
879 * TOE Queue Header
880 * 0x60003000 +---------------------------+ 0x0000
881 * | TOE Queue 0 Header |
882 * | 8 * 4 Bytes |
883 * +---------------------------+ 0x0020
884 * | TOE Queue 1 Header |
885 * | 8 * 4 Bytes |
886 * +---------------------------+ 0x0040
887 * | ...... |
888 * | |
889 * +---------------------------+
890 *
891 * Non TOE Queue Header
892 * 0x60002000 +---------------------------+ 0x0000
893 * | Default Queue 0 Header |
894 * | 2 * 4 Bytes |
895 * +---------------------------+ 0x0008
896 * | Default Queue 1 Header |
897 * | 2 * 4 Bytes |
898 * +---------------------------+ 0x0010
899 * | Classification Queue 0 |
900 * | 2 * 4 Bytes |
901 * +---------------------------+
902 * | Classification Queue 1 |
903 * | 2 * 4 Bytes |
904 * +---------------------------+ (n * 8 + 0x10)
905 * | ... |
906 * | 2 * 4 Bytes |
907 * +---------------------------+ (13 * 8 + 0x10)
908 * | Classification Queue 13 |
909 * | 2 * 4 Bytes |
910 * +---------------------------+ 0x80
911 * | Interrupt Queue 0 |
912 * | 2 * 4 Bytes |
913 * +---------------------------+
914 * | Interrupt Queue 1 |
915 * | 2 * 4 Bytes |
916 * +---------------------------+
917 * | Interrupt Queue 2 |
918 * | 2 * 4 Bytes |
919 * +---------------------------+
920 * | Interrupt Queue 3 |
921 * | 2 * 4 Bytes |
922 * +---------------------------+
923 *
924 */
925#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
926#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
927#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
928#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
929#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
930#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
931#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
932
933/* NONTOE Queue Header Word 0 */
934union nontoe_qhdr0 {
935 unsigned int bits32;
936 unsigned int base_size;
937};
938
939#define NONTOE_QHDR0_BASE_MASK (~0x0f)
940
941/* NONTOE Queue Header Word 1 */
942union nontoe_qhdr1 {
943 unsigned int bits32;
944 struct bit_nonqhdr1 {
945 /* bit 15:0 */
946 unsigned int rptr:16;
947 /* bit 31:16 */
948 unsigned int wptr:16;
949 } bits;
950};
951
952/* Non-TOE Queue Header */
953struct nontoe_qhdr {
954 union nontoe_qhdr0 word0;
955 union nontoe_qhdr1 word1;
956};
957
958#endif /* _GEMINI_ETHERNET_H */