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1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <drm/drmP.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h>
19#include <drm/drm_of.h>
20#include <linux/clk.h>
21#include <linux/component.h>
22#include <linux/iopoll.h>
23#include <linux/irq.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/phy/phy.h>
27#include <linux/platform_device.h>
28#include <video/mipi_display.h>
29#include <video/videomode.h>
30
31#include "mtk_drm_ddp_comp.h"
32
33#define DSI_START 0x00
34
35#define DSI_INTEN 0x08
36
37#define DSI_INTSTA 0x0c
38#define LPRX_RD_RDY_INT_FLAG BIT(0)
39#define CMD_DONE_INT_FLAG BIT(1)
40#define TE_RDY_INT_FLAG BIT(2)
41#define VM_DONE_INT_FLAG BIT(3)
42#define EXT_TE_RDY_INT_FLAG BIT(4)
43#define DSI_BUSY BIT(31)
44
45#define DSI_CON_CTRL 0x10
46#define DSI_RESET BIT(0)
47#define DSI_EN BIT(1)
48
49#define DSI_MODE_CTRL 0x14
50#define MODE (3)
51#define CMD_MODE 0
52#define SYNC_PULSE_MODE 1
53#define SYNC_EVENT_MODE 2
54#define BURST_MODE 3
55#define FRM_MODE BIT(16)
56#define MIX_MODE BIT(17)
57
58#define DSI_TXRX_CTRL 0x18
59#define VC_NUM BIT(1)
60#define LANE_NUM (0xf << 2)
61#define DIS_EOT BIT(6)
62#define NULL_EN BIT(7)
63#define TE_FREERUN BIT(8)
64#define EXT_TE_EN BIT(9)
65#define EXT_TE_EDGE BIT(10)
66#define MAX_RTN_SIZE (0xf << 12)
67#define HSTX_CKLP_EN BIT(16)
68
69#define DSI_PSCTRL 0x1c
70#define DSI_PS_WC 0x3fff
71#define DSI_PS_SEL (3 << 16)
72#define PACKED_PS_16BIT_RGB565 (0 << 16)
73#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
74#define PACKED_PS_18BIT_RGB666 (2 << 16)
75#define PACKED_PS_24BIT_RGB888 (3 << 16)
76
77#define DSI_VSA_NL 0x20
78#define DSI_VBP_NL 0x24
79#define DSI_VFP_NL 0x28
80#define DSI_VACT_NL 0x2C
81#define DSI_HSA_WC 0x50
82#define DSI_HBP_WC 0x54
83#define DSI_HFP_WC 0x58
84
85#define DSI_CMDQ_SIZE 0x60
86#define CMDQ_SIZE 0x3f
87
88#define DSI_HSTX_CKL_WC 0x64
89
90#define DSI_RX_DATA0 0x74
91#define DSI_RX_DATA1 0x78
92#define DSI_RX_DATA2 0x7c
93#define DSI_RX_DATA3 0x80
94
95#define DSI_RACK 0x84
96#define RACK BIT(0)
97
98#define DSI_PHY_LCCON 0x104
99#define LC_HS_TX_EN BIT(0)
100#define LC_ULPM_EN BIT(1)
101#define LC_WAKEUP_EN BIT(2)
102
103#define DSI_PHY_LD0CON 0x108
104#define LD0_HS_TX_EN BIT(0)
105#define LD0_ULPM_EN BIT(1)
106#define LD0_WAKEUP_EN BIT(2)
107
108#define DSI_PHY_TIMECON0 0x110
109#define LPX (0xff << 0)
110#define HS_PREP (0xff << 8)
111#define HS_ZERO (0xff << 16)
112#define HS_TRAIL (0xff << 24)
113
114#define DSI_PHY_TIMECON1 0x114
115#define TA_GO (0xff << 0)
116#define TA_SURE (0xff << 8)
117#define TA_GET (0xff << 16)
118#define DA_HS_EXIT (0xff << 24)
119
120#define DSI_PHY_TIMECON2 0x118
121#define CONT_DET (0xff << 0)
122#define CLK_ZERO (0xff << 16)
123#define CLK_TRAIL (0xff << 24)
124
125#define DSI_PHY_TIMECON3 0x11c
126#define CLK_HS_PREP (0xff << 0)
127#define CLK_HS_POST (0xff << 8)
128#define CLK_HS_EXIT (0xff << 16)
129
130#define DSI_VM_CMD_CON 0x130
131#define VM_CMD_EN BIT(0)
132#define TS_VFP_EN BIT(5)
133
134#define DSI_CMDQ0 0x180
135#define CONFIG (0xff << 0)
136#define SHORT_PACKET 0
137#define LONG_PACKET 2
138#define BTA BIT(2)
139#define DATA_ID (0xff << 8)
140#define DATA_0 (0xff << 16)
141#define DATA_1 (0xff << 24)
142
143#define T_LPX 5
144#define T_HS_PREP 6
145#define T_HS_TRAIL 8
146#define T_HS_EXIT 7
147#define T_HS_ZERO 10
148
149#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
150
151#define MTK_DSI_HOST_IS_READ(type) \
152 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
153 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
154 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
155 (type == MIPI_DSI_DCS_READ))
156
157struct phy;
158
159struct mtk_dsi {
160 struct mtk_ddp_comp ddp_comp;
161 struct device *dev;
162 struct mipi_dsi_host host;
163 struct drm_encoder encoder;
164 struct drm_connector conn;
165 struct drm_panel *panel;
166 struct drm_bridge *bridge;
167 struct phy *phy;
168
169 void __iomem *regs;
170
171 struct clk *engine_clk;
172 struct clk *digital_clk;
173 struct clk *hs_clk;
174
175 u32 data_rate;
176
177 unsigned long mode_flags;
178 enum mipi_dsi_pixel_format format;
179 unsigned int lanes;
180 struct videomode vm;
181 int refcount;
182 bool enabled;
183 u32 irq_data;
184 wait_queue_head_t irq_wait_queue;
185};
186
187static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
188{
189 return container_of(e, struct mtk_dsi, encoder);
190}
191
192static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
193{
194 return container_of(c, struct mtk_dsi, conn);
195}
196
197static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
198{
199 return container_of(h, struct mtk_dsi, host);
200}
201
202static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
203{
204 u32 temp = readl(dsi->regs + offset);
205
206 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
207}
208
209static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
210{
211 u32 timcon0, timcon1, timcon2, timcon3;
212 u32 ui, cycle_time;
213
214 ui = 1000 / dsi->data_rate + 0x01;
215 cycle_time = 8000 / dsi->data_rate + 0x01;
216
217 timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
218 timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
219 T_HS_EXIT << 24;
220 timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
221 (NS_TO_CYCLE(0x150, cycle_time) << 16);
222 timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
223 NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
224
225 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
226 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
227 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
228 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
229}
230
231static void mtk_dsi_enable(struct mtk_dsi *dsi)
232{
233 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
234}
235
236static void mtk_dsi_disable(struct mtk_dsi *dsi)
237{
238 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
239}
240
241static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
242{
243 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
244 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
245}
246
247static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
248{
249 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
250 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
251}
252
253static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
254{
255 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
256 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
257 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
258}
259
260static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
261{
262 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
263 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
264}
265
266static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
267{
268 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
269 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
270 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
271}
272
273static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
274{
275 u32 tmp_reg1;
276
277 tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
278 return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
279}
280
281static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
282{
283 if (enter && !mtk_dsi_clk_hs_state(dsi))
284 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
285 else if (!enter && mtk_dsi_clk_hs_state(dsi))
286 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
287}
288
289static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
290{
291 u32 vid_mode = CMD_MODE;
292
293 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
294 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
295 vid_mode = BURST_MODE;
296 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
297 vid_mode = SYNC_PULSE_MODE;
298 else
299 vid_mode = SYNC_EVENT_MODE;
300 }
301
302 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
303}
304
305static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
306{
307 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
308 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
309}
310
311static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
312{
313 struct videomode *vm = &dsi->vm;
314 u32 dsi_buf_bpp, ps_wc;
315 u32 ps_bpp_mode;
316
317 if (dsi->format == MIPI_DSI_FMT_RGB565)
318 dsi_buf_bpp = 2;
319 else
320 dsi_buf_bpp = 3;
321
322 ps_wc = vm->hactive * dsi_buf_bpp;
323 ps_bpp_mode = ps_wc;
324
325 switch (dsi->format) {
326 case MIPI_DSI_FMT_RGB888:
327 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
328 break;
329 case MIPI_DSI_FMT_RGB666:
330 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
331 break;
332 case MIPI_DSI_FMT_RGB666_PACKED:
333 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
334 break;
335 case MIPI_DSI_FMT_RGB565:
336 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
337 break;
338 }
339
340 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
341 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
342 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
343}
344
345static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
346{
347 u32 tmp_reg;
348
349 switch (dsi->lanes) {
350 case 1:
351 tmp_reg = 1 << 2;
352 break;
353 case 2:
354 tmp_reg = 3 << 2;
355 break;
356 case 3:
357 tmp_reg = 7 << 2;
358 break;
359 case 4:
360 tmp_reg = 0xf << 2;
361 break;
362 default:
363 tmp_reg = 0xf << 2;
364 break;
365 }
366
367 tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
368 tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
369
370 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
371}
372
373static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
374{
375 u32 dsi_tmp_buf_bpp;
376 u32 tmp_reg;
377
378 switch (dsi->format) {
379 case MIPI_DSI_FMT_RGB888:
380 tmp_reg = PACKED_PS_24BIT_RGB888;
381 dsi_tmp_buf_bpp = 3;
382 break;
383 case MIPI_DSI_FMT_RGB666:
384 tmp_reg = LOOSELY_PS_18BIT_RGB666;
385 dsi_tmp_buf_bpp = 3;
386 break;
387 case MIPI_DSI_FMT_RGB666_PACKED:
388 tmp_reg = PACKED_PS_18BIT_RGB666;
389 dsi_tmp_buf_bpp = 3;
390 break;
391 case MIPI_DSI_FMT_RGB565:
392 tmp_reg = PACKED_PS_16BIT_RGB565;
393 dsi_tmp_buf_bpp = 2;
394 break;
395 default:
396 tmp_reg = PACKED_PS_24BIT_RGB888;
397 dsi_tmp_buf_bpp = 3;
398 break;
399 }
400
401 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
402 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
403}
404
405static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
406{
407 u32 horizontal_sync_active_byte;
408 u32 horizontal_backporch_byte;
409 u32 horizontal_frontporch_byte;
410 u32 dsi_tmp_buf_bpp;
411
412 struct videomode *vm = &dsi->vm;
413
414 if (dsi->format == MIPI_DSI_FMT_RGB565)
415 dsi_tmp_buf_bpp = 2;
416 else
417 dsi_tmp_buf_bpp = 3;
418
419 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
420 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
421 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
422 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
423
424 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
425
426 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
427 horizontal_backporch_byte =
428 (vm->hback_porch * dsi_tmp_buf_bpp - 10);
429 else
430 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
431 dsi_tmp_buf_bpp - 10);
432
433 horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
434
435 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
436 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
437 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
438
439 mtk_dsi_ps_control(dsi);
440}
441
442static void mtk_dsi_start(struct mtk_dsi *dsi)
443{
444 writel(0, dsi->regs + DSI_START);
445 writel(1, dsi->regs + DSI_START);
446}
447
448static void mtk_dsi_stop(struct mtk_dsi *dsi)
449{
450 writel(0, dsi->regs + DSI_START);
451}
452
453static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
454{
455 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
456}
457
458static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
459{
460 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
461
462 writel(inten, dsi->regs + DSI_INTEN);
463}
464
465static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
466{
467 dsi->irq_data |= irq_bit;
468}
469
470static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
471{
472 dsi->irq_data &= ~irq_bit;
473}
474
475static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
476 unsigned int timeout)
477{
478 s32 ret = 0;
479 unsigned long jiffies = msecs_to_jiffies(timeout);
480
481 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
482 dsi->irq_data & irq_flag,
483 jiffies);
484 if (ret == 0) {
485 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
486
487 mtk_dsi_enable(dsi);
488 mtk_dsi_reset_engine(dsi);
489 }
490
491 return ret;
492}
493
494static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
495{
496 struct mtk_dsi *dsi = dev_id;
497 u32 status, tmp;
498 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
499
500 status = readl(dsi->regs + DSI_INTSTA) & flag;
501
502 if (status) {
503 do {
504 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
505 tmp = readl(dsi->regs + DSI_INTSTA);
506 } while (tmp & DSI_BUSY);
507
508 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
509 mtk_dsi_irq_data_set(dsi, status);
510 wake_up_interruptible(&dsi->irq_wait_queue);
511 }
512
513 return IRQ_HANDLED;
514}
515
516static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
517{
518 mtk_dsi_irq_data_clear(dsi, irq_flag);
519 mtk_dsi_set_cmd_mode(dsi);
520
521 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
522 DRM_ERROR("failed to switch cmd mode\n");
523 return -ETIME;
524 } else {
525 return 0;
526 }
527}
528
529static int mtk_dsi_poweron(struct mtk_dsi *dsi)
530{
531 struct device *dev = dsi->dev;
532 int ret;
533 u64 pixel_clock, total_bits;
534 u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
535
536 if (++dsi->refcount != 1)
537 return 0;
538
539 switch (dsi->format) {
540 case MIPI_DSI_FMT_RGB565:
541 bit_per_pixel = 16;
542 break;
543 case MIPI_DSI_FMT_RGB666_PACKED:
544 bit_per_pixel = 18;
545 break;
546 case MIPI_DSI_FMT_RGB666:
547 case MIPI_DSI_FMT_RGB888:
548 default:
549 bit_per_pixel = 24;
550 break;
551 }
552
553 /**
554 * vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
555 * htotal_time = htotal * byte_per_pixel / num_lanes
556 * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
557 * mipi_ratio = (htotal_time + overhead_time) / htotal_time
558 * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
559 */
560 pixel_clock = dsi->vm.pixelclock * 1000;
561 htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
562 dsi->vm.hsync_len;
563 htotal_bits = htotal * bit_per_pixel;
564
565 overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
566 T_HS_EXIT;
567 overhead_bits = overhead_cycles * dsi->lanes * 8;
568 total_bits = htotal_bits + overhead_bits;
569
570 dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
571 htotal * dsi->lanes);
572
573 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
574 if (ret < 0) {
575 dev_err(dev, "Failed to set data rate: %d\n", ret);
576 goto err_refcount;
577 }
578
579 phy_power_on(dsi->phy);
580
581 ret = clk_prepare_enable(dsi->engine_clk);
582 if (ret < 0) {
583 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
584 goto err_phy_power_off;
585 }
586
587 ret = clk_prepare_enable(dsi->digital_clk);
588 if (ret < 0) {
589 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
590 goto err_disable_engine_clk;
591 }
592
593 mtk_dsi_enable(dsi);
594 mtk_dsi_reset_engine(dsi);
595 mtk_dsi_phy_timconfig(dsi);
596
597 mtk_dsi_rxtx_control(dsi);
598 mtk_dsi_ps_control_vact(dsi);
599 mtk_dsi_set_vm_cmd(dsi);
600 mtk_dsi_config_vdo_timing(dsi);
601 mtk_dsi_set_interrupt_enable(dsi);
602
603 mtk_dsi_clk_ulp_mode_leave(dsi);
604 mtk_dsi_lane0_ulp_mode_leave(dsi);
605 mtk_dsi_clk_hs_mode(dsi, 0);
606
607 if (dsi->panel) {
608 if (drm_panel_prepare(dsi->panel)) {
609 DRM_ERROR("failed to prepare the panel\n");
610 goto err_disable_digital_clk;
611 }
612 }
613
614 return 0;
615err_disable_digital_clk:
616 clk_disable_unprepare(dsi->digital_clk);
617err_disable_engine_clk:
618 clk_disable_unprepare(dsi->engine_clk);
619err_phy_power_off:
620 phy_power_off(dsi->phy);
621err_refcount:
622 dsi->refcount--;
623 return ret;
624}
625
626static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
627{
628 if (WARN_ON(dsi->refcount == 0))
629 return;
630
631 if (--dsi->refcount != 0)
632 return;
633
634 if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
635 if (dsi->panel) {
636 if (drm_panel_unprepare(dsi->panel)) {
637 DRM_ERROR("failed to unprepare the panel\n");
638 return;
639 }
640 }
641 }
642
643 mtk_dsi_reset_engine(dsi);
644 mtk_dsi_lane0_ulp_mode_enter(dsi);
645 mtk_dsi_clk_ulp_mode_enter(dsi);
646
647 mtk_dsi_disable(dsi);
648
649 clk_disable_unprepare(dsi->engine_clk);
650 clk_disable_unprepare(dsi->digital_clk);
651
652 phy_power_off(dsi->phy);
653}
654
655static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
656{
657 int ret;
658
659 if (dsi->enabled)
660 return;
661
662 ret = mtk_dsi_poweron(dsi);
663 if (ret < 0) {
664 DRM_ERROR("failed to power on dsi\n");
665 return;
666 }
667
668 mtk_dsi_set_mode(dsi);
669 mtk_dsi_clk_hs_mode(dsi, 1);
670
671 mtk_dsi_start(dsi);
672
673 if (dsi->panel) {
674 if (drm_panel_enable(dsi->panel)) {
675 DRM_ERROR("failed to enable the panel\n");
676 goto err_dsi_power_off;
677 }
678 }
679
680 dsi->enabled = true;
681
682 return;
683err_dsi_power_off:
684 mtk_dsi_stop(dsi);
685 mtk_dsi_poweroff(dsi);
686}
687
688static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
689{
690 if (!dsi->enabled)
691 return;
692
693 if (dsi->panel) {
694 if (drm_panel_disable(dsi->panel)) {
695 DRM_ERROR("failed to disable the panel\n");
696 return;
697 }
698 }
699
700 mtk_dsi_stop(dsi);
701 mtk_dsi_poweroff(dsi);
702
703 dsi->enabled = false;
704}
705
706static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
707{
708 drm_encoder_cleanup(encoder);
709}
710
711static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
712 .destroy = mtk_dsi_encoder_destroy,
713};
714
715static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
716 const struct drm_display_mode *mode,
717 struct drm_display_mode *adjusted_mode)
718{
719 return true;
720}
721
722static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
723 struct drm_display_mode *mode,
724 struct drm_display_mode *adjusted)
725{
726 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
727
728 dsi->vm.pixelclock = adjusted->clock;
729 dsi->vm.hactive = adjusted->hdisplay;
730 dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end;
731 dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay;
732 dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start;
733
734 dsi->vm.vactive = adjusted->vdisplay;
735 dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end;
736 dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay;
737 dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start;
738}
739
740static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
741{
742 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
743
744 mtk_output_dsi_disable(dsi);
745}
746
747static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
748{
749 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
750
751 mtk_output_dsi_enable(dsi);
752}
753
754static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
755{
756 struct mtk_dsi *dsi = connector_to_dsi(connector);
757
758 return drm_panel_get_modes(dsi->panel);
759}
760
761static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
762 .mode_fixup = mtk_dsi_encoder_mode_fixup,
763 .mode_set = mtk_dsi_encoder_mode_set,
764 .disable = mtk_dsi_encoder_disable,
765 .enable = mtk_dsi_encoder_enable,
766};
767
768static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
769 .fill_modes = drm_helper_probe_single_connector_modes,
770 .destroy = drm_connector_cleanup,
771 .reset = drm_atomic_helper_connector_reset,
772 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
773 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
774};
775
776static const struct drm_connector_helper_funcs
777 mtk_dsi_connector_helper_funcs = {
778 .get_modes = mtk_dsi_connector_get_modes,
779};
780
781static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
782{
783 int ret;
784
785 ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
786 DRM_MODE_CONNECTOR_DSI);
787 if (ret) {
788 DRM_ERROR("Failed to connector init to drm\n");
789 return ret;
790 }
791
792 drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
793
794 dsi->conn.dpms = DRM_MODE_DPMS_OFF;
795 drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder);
796
797 if (dsi->panel) {
798 ret = drm_panel_attach(dsi->panel, &dsi->conn);
799 if (ret) {
800 DRM_ERROR("Failed to attach panel to drm\n");
801 goto err_connector_cleanup;
802 }
803 }
804
805 return 0;
806
807err_connector_cleanup:
808 drm_connector_cleanup(&dsi->conn);
809 return ret;
810}
811
812static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
813{
814 int ret;
815
816 ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
817 DRM_MODE_ENCODER_DSI, NULL);
818 if (ret) {
819 DRM_ERROR("Failed to encoder init to drm\n");
820 return ret;
821 }
822 drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
823
824 /*
825 * Currently display data paths are statically assigned to a crtc each.
826 * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
827 */
828 dsi->encoder.possible_crtcs = 1;
829
830 /* If there's a bridge, attach to it and let it create the connector */
831 ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
832 if (ret) {
833 DRM_ERROR("Failed to attach bridge to drm\n");
834
835 /* Otherwise create our own connector and attach to a panel */
836 ret = mtk_dsi_create_connector(drm, dsi);
837 if (ret)
838 goto err_encoder_cleanup;
839 }
840
841 return 0;
842
843err_encoder_cleanup:
844 drm_encoder_cleanup(&dsi->encoder);
845 return ret;
846}
847
848static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
849{
850 drm_encoder_cleanup(&dsi->encoder);
851 /* Skip connector cleanup if creation was delegated to the bridge */
852 if (dsi->conn.dev)
853 drm_connector_cleanup(&dsi->conn);
854}
855
856static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
857{
858 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
859
860 mtk_dsi_poweron(dsi);
861}
862
863static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
864{
865 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
866
867 mtk_dsi_poweroff(dsi);
868}
869
870static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
871 .start = mtk_dsi_ddp_start,
872 .stop = mtk_dsi_ddp_stop,
873};
874
875static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
876 struct mipi_dsi_device *device)
877{
878 struct mtk_dsi *dsi = host_to_dsi(host);
879
880 dsi->lanes = device->lanes;
881 dsi->format = device->format;
882 dsi->mode_flags = device->mode_flags;
883
884 if (dsi->conn.dev)
885 drm_helper_hpd_irq_event(dsi->conn.dev);
886
887 return 0;
888}
889
890static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
891 struct mipi_dsi_device *device)
892{
893 struct mtk_dsi *dsi = host_to_dsi(host);
894
895 if (dsi->conn.dev)
896 drm_helper_hpd_irq_event(dsi->conn.dev);
897
898 return 0;
899}
900
901static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
902{
903 int ret;
904 u32 val;
905
906 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
907 4, 2000000);
908 if (ret) {
909 DRM_WARN("polling dsi wait not busy timeout!\n");
910
911 mtk_dsi_enable(dsi);
912 mtk_dsi_reset_engine(dsi);
913 }
914}
915
916static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
917{
918 switch (type) {
919 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
920 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
921 return 1;
922 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
923 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
924 return 2;
925 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
926 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
927 return read_data[1] + read_data[2] * 16;
928 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
929 DRM_INFO("type is 0x02, try again\n");
930 break;
931 default:
932 DRM_INFO("type(0x%x) not recognized\n", type);
933 break;
934 }
935
936 return 0;
937}
938
939static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
940{
941 const char *tx_buf = msg->tx_buf;
942 u8 config, cmdq_size, cmdq_off, type = msg->type;
943 u32 reg_val, cmdq_mask, i;
944
945 if (MTK_DSI_HOST_IS_READ(type))
946 config = BTA;
947 else
948 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
949
950 if (msg->tx_len > 2) {
951 cmdq_size = 1 + (msg->tx_len + 3) / 4;
952 cmdq_off = 4;
953 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
954 reg_val = (msg->tx_len << 16) | (type << 8) | config;
955 } else {
956 cmdq_size = 1;
957 cmdq_off = 2;
958 cmdq_mask = CONFIG | DATA_ID;
959 reg_val = (type << 8) | config;
960 }
961
962 for (i = 0; i < msg->tx_len; i++)
963 writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
964
965 mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
966 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
967}
968
969static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
970 const struct mipi_dsi_msg *msg, u8 flag)
971{
972 mtk_dsi_wait_for_idle(dsi);
973 mtk_dsi_irq_data_clear(dsi, flag);
974 mtk_dsi_cmdq(dsi, msg);
975 mtk_dsi_start(dsi);
976
977 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
978 return -ETIME;
979 else
980 return 0;
981}
982
983static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
984 const struct mipi_dsi_msg *msg)
985{
986 struct mtk_dsi *dsi = host_to_dsi(host);
987 u32 recv_cnt, i;
988 u8 read_data[16];
989 void *src_addr;
990 u8 irq_flag = CMD_DONE_INT_FLAG;
991
992 if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
993 DRM_ERROR("dsi engine is not command mode\n");
994 return -EINVAL;
995 }
996
997 if (MTK_DSI_HOST_IS_READ(msg->type))
998 irq_flag |= LPRX_RD_RDY_INT_FLAG;
999
1000 if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
1001 return -ETIME;
1002
1003 if (!MTK_DSI_HOST_IS_READ(msg->type))
1004 return 0;
1005
1006 if (!msg->rx_buf) {
1007 DRM_ERROR("dsi receive buffer size may be NULL\n");
1008 return -EINVAL;
1009 }
1010
1011 for (i = 0; i < 16; i++)
1012 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1013
1014 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1015
1016 if (recv_cnt > 2)
1017 src_addr = &read_data[4];
1018 else
1019 src_addr = &read_data[1];
1020
1021 if (recv_cnt > 10)
1022 recv_cnt = 10;
1023
1024 if (recv_cnt > msg->rx_len)
1025 recv_cnt = msg->rx_len;
1026
1027 if (recv_cnt)
1028 memcpy(msg->rx_buf, src_addr, recv_cnt);
1029
1030 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1031 recv_cnt, *((u8 *)(msg->tx_buf)));
1032
1033 return recv_cnt;
1034}
1035
1036static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1037 .attach = mtk_dsi_host_attach,
1038 .detach = mtk_dsi_host_detach,
1039 .transfer = mtk_dsi_host_transfer,
1040};
1041
1042static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
1043{
1044 int ret;
1045 struct drm_device *drm = data;
1046 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1047
1048 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1049 if (ret < 0) {
1050 dev_err(dev, "Failed to register component %pOF: %d\n",
1051 dev->of_node, ret);
1052 return ret;
1053 }
1054
1055 ret = mipi_dsi_host_register(&dsi->host);
1056 if (ret < 0) {
1057 dev_err(dev, "failed to register DSI host: %d\n", ret);
1058 goto err_ddp_comp_unregister;
1059 }
1060
1061 ret = mtk_dsi_create_conn_enc(drm, dsi);
1062 if (ret) {
1063 DRM_ERROR("Encoder create failed with %d\n", ret);
1064 goto err_unregister;
1065 }
1066
1067 return 0;
1068
1069err_unregister:
1070 mipi_dsi_host_unregister(&dsi->host);
1071err_ddp_comp_unregister:
1072 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1073 return ret;
1074}
1075
1076static void mtk_dsi_unbind(struct device *dev, struct device *master,
1077 void *data)
1078{
1079 struct drm_device *drm = data;
1080 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1081
1082 mtk_dsi_destroy_conn_enc(dsi);
1083 mipi_dsi_host_unregister(&dsi->host);
1084 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1085}
1086
1087static const struct component_ops mtk_dsi_component_ops = {
1088 .bind = mtk_dsi_bind,
1089 .unbind = mtk_dsi_unbind,
1090};
1091
1092static int mtk_dsi_probe(struct platform_device *pdev)
1093{
1094 struct mtk_dsi *dsi;
1095 struct device *dev = &pdev->dev;
1096 struct resource *regs;
1097 int irq_num;
1098 int comp_id;
1099 int ret;
1100
1101 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1102 if (!dsi)
1103 return -ENOMEM;
1104
1105 dsi->host.ops = &mtk_dsi_ops;
1106 dsi->host.dev = dev;
1107
1108 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1109 &dsi->panel, &dsi->bridge);
1110 if (ret)
1111 return ret;
1112
1113 dsi->engine_clk = devm_clk_get(dev, "engine");
1114 if (IS_ERR(dsi->engine_clk)) {
1115 ret = PTR_ERR(dsi->engine_clk);
1116 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1117 return ret;
1118 }
1119
1120 dsi->digital_clk = devm_clk_get(dev, "digital");
1121 if (IS_ERR(dsi->digital_clk)) {
1122 ret = PTR_ERR(dsi->digital_clk);
1123 dev_err(dev, "Failed to get digital clock: %d\n", ret);
1124 return ret;
1125 }
1126
1127 dsi->hs_clk = devm_clk_get(dev, "hs");
1128 if (IS_ERR(dsi->hs_clk)) {
1129 ret = PTR_ERR(dsi->hs_clk);
1130 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1131 return ret;
1132 }
1133
1134 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1135 dsi->regs = devm_ioremap_resource(dev, regs);
1136 if (IS_ERR(dsi->regs)) {
1137 ret = PTR_ERR(dsi->regs);
1138 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1139 return ret;
1140 }
1141
1142 dsi->phy = devm_phy_get(dev, "dphy");
1143 if (IS_ERR(dsi->phy)) {
1144 ret = PTR_ERR(dsi->phy);
1145 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1146 return ret;
1147 }
1148
1149 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1150 if (comp_id < 0) {
1151 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1152 return comp_id;
1153 }
1154
1155 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1156 &mtk_dsi_funcs);
1157 if (ret) {
1158 dev_err(dev, "Failed to initialize component: %d\n", ret);
1159 return ret;
1160 }
1161
1162 irq_num = platform_get_irq(pdev, 0);
1163 if (irq_num < 0) {
1164 dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1165 return -EPROBE_DEFER;
1166 }
1167
1168 irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1169 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1170 IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1171 if (ret) {
1172 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1173 return -EPROBE_DEFER;
1174 }
1175
1176 init_waitqueue_head(&dsi->irq_wait_queue);
1177
1178 platform_set_drvdata(pdev, dsi);
1179
1180 return component_add(&pdev->dev, &mtk_dsi_component_ops);
1181}
1182
1183static int mtk_dsi_remove(struct platform_device *pdev)
1184{
1185 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1186
1187 mtk_output_dsi_disable(dsi);
1188 component_del(&pdev->dev, &mtk_dsi_component_ops);
1189
1190 return 0;
1191}
1192
1193static const struct of_device_id mtk_dsi_of_match[] = {
1194 { .compatible = "mediatek,mt2701-dsi" },
1195 { .compatible = "mediatek,mt8173-dsi" },
1196 { },
1197};
1198
1199struct platform_driver mtk_dsi_driver = {
1200 .probe = mtk_dsi_probe,
1201 .remove = mtk_dsi_remove,
1202 .driver = {
1203 .name = "mtk-dsi",
1204 .of_match_table = mtk_dsi_of_match,
1205 },
1206};
1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <drm/drmP.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_crtc_helper.h>
17#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h>
19#include <linux/clk.h>
20#include <linux/component.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/of_graph.h>
24#include <linux/phy/phy.h>
25#include <linux/platform_device.h>
26#include <video/videomode.h>
27
28#include "mtk_drm_ddp_comp.h"
29
30#define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
31#define DSI_HOST_FIFO_DEPTH 64
32
33#define DSI_START 0x00
34
35#define DSI_CON_CTRL 0x10
36#define DSI_RESET BIT(0)
37#define DSI_EN BIT(1)
38
39#define DSI_MODE_CTRL 0x14
40#define MODE (3)
41#define CMD_MODE 0
42#define SYNC_PULSE_MODE 1
43#define SYNC_EVENT_MODE 2
44#define BURST_MODE 3
45#define FRM_MODE BIT(16)
46#define MIX_MODE BIT(17)
47
48#define DSI_TXRX_CTRL 0x18
49#define VC_NUM (2 << 0)
50#define LANE_NUM (0xf << 2)
51#define DIS_EOT BIT(6)
52#define NULL_EN BIT(7)
53#define TE_FREERUN BIT(8)
54#define EXT_TE_EN BIT(9)
55#define EXT_TE_EDGE BIT(10)
56#define MAX_RTN_SIZE (0xf << 12)
57#define HSTX_CKLP_EN BIT(16)
58
59#define DSI_PSCTRL 0x1c
60#define DSI_PS_WC 0x3fff
61#define DSI_PS_SEL (3 << 16)
62#define PACKED_PS_16BIT_RGB565 (0 << 16)
63#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
64#define PACKED_PS_18BIT_RGB666 (2 << 16)
65#define PACKED_PS_24BIT_RGB888 (3 << 16)
66
67#define DSI_VSA_NL 0x20
68#define DSI_VBP_NL 0x24
69#define DSI_VFP_NL 0x28
70#define DSI_VACT_NL 0x2C
71#define DSI_HSA_WC 0x50
72#define DSI_HBP_WC 0x54
73#define DSI_HFP_WC 0x58
74
75#define DSI_HSTX_CKL_WC 0x64
76
77#define DSI_PHY_LCCON 0x104
78#define LC_HS_TX_EN BIT(0)
79#define LC_ULPM_EN BIT(1)
80#define LC_WAKEUP_EN BIT(2)
81
82#define DSI_PHY_LD0CON 0x108
83#define LD0_HS_TX_EN BIT(0)
84#define LD0_ULPM_EN BIT(1)
85#define LD0_WAKEUP_EN BIT(2)
86
87#define DSI_PHY_TIMECON0 0x110
88#define LPX (0xff << 0)
89#define HS_PREP (0xff << 8)
90#define HS_ZERO (0xff << 16)
91#define HS_TRAIL (0xff << 24)
92
93#define DSI_PHY_TIMECON1 0x114
94#define TA_GO (0xff << 0)
95#define TA_SURE (0xff << 8)
96#define TA_GET (0xff << 16)
97#define DA_HS_EXIT (0xff << 24)
98
99#define DSI_PHY_TIMECON2 0x118
100#define CONT_DET (0xff << 0)
101#define CLK_ZERO (0xff << 16)
102#define CLK_TRAIL (0xff << 24)
103
104#define DSI_PHY_TIMECON3 0x11c
105#define CLK_HS_PREP (0xff << 0)
106#define CLK_HS_POST (0xff << 8)
107#define CLK_HS_EXIT (0xff << 16)
108
109#define T_LPX 5
110#define T_HS_PREP 6
111#define T_HS_TRAIL 8
112#define T_HS_EXIT 7
113#define T_HS_ZERO 10
114
115#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
116
117struct phy;
118
119struct mtk_dsi {
120 struct mtk_ddp_comp ddp_comp;
121 struct device *dev;
122 struct mipi_dsi_host host;
123 struct drm_encoder encoder;
124 struct drm_connector conn;
125 struct drm_panel *panel;
126 struct drm_bridge *bridge;
127 struct phy *phy;
128
129 void __iomem *regs;
130
131 struct clk *engine_clk;
132 struct clk *digital_clk;
133 struct clk *hs_clk;
134
135 u32 data_rate;
136
137 unsigned long mode_flags;
138 enum mipi_dsi_pixel_format format;
139 unsigned int lanes;
140 struct videomode vm;
141 int refcount;
142 bool enabled;
143};
144
145static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
146{
147 return container_of(e, struct mtk_dsi, encoder);
148}
149
150static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
151{
152 return container_of(c, struct mtk_dsi, conn);
153}
154
155static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
156{
157 return container_of(h, struct mtk_dsi, host);
158}
159
160static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
161{
162 u32 temp = readl(dsi->regs + offset);
163
164 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
165}
166
167static void dsi_phy_timconfig(struct mtk_dsi *dsi)
168{
169 u32 timcon0, timcon1, timcon2, timcon3;
170 u32 ui, cycle_time;
171
172 ui = 1000 / dsi->data_rate + 0x01;
173 cycle_time = 8000 / dsi->data_rate + 0x01;
174
175 timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
176 timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
177 T_HS_EXIT << 24;
178 timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
179 (NS_TO_CYCLE(0x150, cycle_time) << 16);
180 timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
181 NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
182
183 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
184 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
185 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
186 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
187}
188
189static void mtk_dsi_enable(struct mtk_dsi *dsi)
190{
191 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
192}
193
194static void mtk_dsi_disable(struct mtk_dsi *dsi)
195{
196 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
197}
198
199static void mtk_dsi_reset(struct mtk_dsi *dsi)
200{
201 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
202 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
203}
204
205static int mtk_dsi_poweron(struct mtk_dsi *dsi)
206{
207 struct device *dev = dsi->dev;
208 int ret;
209 u64 pixel_clock, total_bits;
210 u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
211
212 if (++dsi->refcount != 1)
213 return 0;
214
215 switch (dsi->format) {
216 case MIPI_DSI_FMT_RGB565:
217 bit_per_pixel = 16;
218 break;
219 case MIPI_DSI_FMT_RGB666_PACKED:
220 bit_per_pixel = 18;
221 break;
222 case MIPI_DSI_FMT_RGB666:
223 case MIPI_DSI_FMT_RGB888:
224 default:
225 bit_per_pixel = 24;
226 break;
227 }
228
229 /**
230 * vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
231 * htotal_time = htotal * byte_per_pixel / num_lanes
232 * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
233 * mipi_ratio = (htotal_time + overhead_time) / htotal_time
234 * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
235 */
236 pixel_clock = dsi->vm.pixelclock * 1000;
237 htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
238 dsi->vm.hsync_len;
239 htotal_bits = htotal * bit_per_pixel;
240
241 overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
242 T_HS_EXIT;
243 overhead_bits = overhead_cycles * dsi->lanes * 8;
244 total_bits = htotal_bits + overhead_bits;
245
246 dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
247 htotal * dsi->lanes);
248
249 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
250 if (ret < 0) {
251 dev_err(dev, "Failed to set data rate: %d\n", ret);
252 goto err_refcount;
253 }
254
255 phy_power_on(dsi->phy);
256
257 ret = clk_prepare_enable(dsi->engine_clk);
258 if (ret < 0) {
259 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
260 goto err_phy_power_off;
261 }
262
263 ret = clk_prepare_enable(dsi->digital_clk);
264 if (ret < 0) {
265 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
266 goto err_disable_engine_clk;
267 }
268
269 mtk_dsi_enable(dsi);
270 mtk_dsi_reset(dsi);
271 dsi_phy_timconfig(dsi);
272
273 return 0;
274
275err_disable_engine_clk:
276 clk_disable_unprepare(dsi->engine_clk);
277err_phy_power_off:
278 phy_power_off(dsi->phy);
279err_refcount:
280 dsi->refcount--;
281 return ret;
282}
283
284static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
285{
286 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
287 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
288}
289
290static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
291{
292 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
293 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
294 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
295}
296
297static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
298{
299 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
300 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
301}
302
303static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
304{
305 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
306 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
307 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
308}
309
310static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
311{
312 u32 tmp_reg1;
313
314 tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
315 return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
316}
317
318static void dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
319{
320 if (enter && !dsi_clk_hs_state(dsi))
321 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
322 else if (!enter && dsi_clk_hs_state(dsi))
323 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
324}
325
326static void dsi_set_mode(struct mtk_dsi *dsi)
327{
328 u32 vid_mode = CMD_MODE;
329
330 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
331 vid_mode = SYNC_PULSE_MODE;
332
333 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
334 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
335 vid_mode = BURST_MODE;
336 }
337
338 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
339}
340
341static void dsi_ps_control_vact(struct mtk_dsi *dsi)
342{
343 struct videomode *vm = &dsi->vm;
344 u32 dsi_buf_bpp, ps_wc;
345 u32 ps_bpp_mode;
346
347 if (dsi->format == MIPI_DSI_FMT_RGB565)
348 dsi_buf_bpp = 2;
349 else
350 dsi_buf_bpp = 3;
351
352 ps_wc = vm->hactive * dsi_buf_bpp;
353 ps_bpp_mode = ps_wc;
354
355 switch (dsi->format) {
356 case MIPI_DSI_FMT_RGB888:
357 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
358 break;
359 case MIPI_DSI_FMT_RGB666:
360 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
361 break;
362 case MIPI_DSI_FMT_RGB666_PACKED:
363 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
364 break;
365 case MIPI_DSI_FMT_RGB565:
366 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
367 break;
368 }
369
370 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
371 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
372 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
373}
374
375static void dsi_rxtx_control(struct mtk_dsi *dsi)
376{
377 u32 tmp_reg;
378
379 switch (dsi->lanes) {
380 case 1:
381 tmp_reg = 1 << 2;
382 break;
383 case 2:
384 tmp_reg = 3 << 2;
385 break;
386 case 3:
387 tmp_reg = 7 << 2;
388 break;
389 case 4:
390 tmp_reg = 0xf << 2;
391 break;
392 default:
393 tmp_reg = 0xf << 2;
394 break;
395 }
396
397 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
398}
399
400static void dsi_ps_control(struct mtk_dsi *dsi)
401{
402 unsigned int dsi_tmp_buf_bpp;
403 u32 tmp_reg;
404
405 switch (dsi->format) {
406 case MIPI_DSI_FMT_RGB888:
407 tmp_reg = PACKED_PS_24BIT_RGB888;
408 dsi_tmp_buf_bpp = 3;
409 break;
410 case MIPI_DSI_FMT_RGB666:
411 tmp_reg = LOOSELY_PS_18BIT_RGB666;
412 dsi_tmp_buf_bpp = 3;
413 break;
414 case MIPI_DSI_FMT_RGB666_PACKED:
415 tmp_reg = PACKED_PS_18BIT_RGB666;
416 dsi_tmp_buf_bpp = 3;
417 break;
418 case MIPI_DSI_FMT_RGB565:
419 tmp_reg = PACKED_PS_16BIT_RGB565;
420 dsi_tmp_buf_bpp = 2;
421 break;
422 default:
423 tmp_reg = PACKED_PS_24BIT_RGB888;
424 dsi_tmp_buf_bpp = 3;
425 break;
426 }
427
428 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
429 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
430}
431
432static void dsi_config_vdo_timing(struct mtk_dsi *dsi)
433{
434 unsigned int horizontal_sync_active_byte;
435 unsigned int horizontal_backporch_byte;
436 unsigned int horizontal_frontporch_byte;
437 unsigned int dsi_tmp_buf_bpp;
438
439 struct videomode *vm = &dsi->vm;
440
441 if (dsi->format == MIPI_DSI_FMT_RGB565)
442 dsi_tmp_buf_bpp = 2;
443 else
444 dsi_tmp_buf_bpp = 3;
445
446 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
447 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
448 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
449 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
450
451 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
452
453 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
454 horizontal_backporch_byte =
455 (vm->hback_porch * dsi_tmp_buf_bpp - 10);
456 else
457 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
458 dsi_tmp_buf_bpp - 10);
459
460 horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
461
462 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
463 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
464 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
465
466 dsi_ps_control(dsi);
467}
468
469static void mtk_dsi_start(struct mtk_dsi *dsi)
470{
471 writel(0, dsi->regs + DSI_START);
472 writel(1, dsi->regs + DSI_START);
473}
474
475static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
476{
477 if (WARN_ON(dsi->refcount == 0))
478 return;
479
480 if (--dsi->refcount != 0)
481 return;
482
483 dsi_lane0_ulp_mode_enter(dsi);
484 dsi_clk_ulp_mode_enter(dsi);
485
486 mtk_dsi_disable(dsi);
487
488 clk_disable_unprepare(dsi->engine_clk);
489 clk_disable_unprepare(dsi->digital_clk);
490
491 phy_power_off(dsi->phy);
492}
493
494static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
495{
496 int ret;
497
498 if (dsi->enabled)
499 return;
500
501 if (dsi->panel) {
502 if (drm_panel_prepare(dsi->panel)) {
503 DRM_ERROR("failed to setup the panel\n");
504 return;
505 }
506 }
507
508 ret = mtk_dsi_poweron(dsi);
509 if (ret < 0) {
510 DRM_ERROR("failed to power on dsi\n");
511 return;
512 }
513
514 dsi_rxtx_control(dsi);
515
516 dsi_clk_ulp_mode_leave(dsi);
517 dsi_lane0_ulp_mode_leave(dsi);
518 dsi_clk_hs_mode(dsi, 0);
519 dsi_set_mode(dsi);
520
521 dsi_ps_control_vact(dsi);
522 dsi_config_vdo_timing(dsi);
523
524 dsi_set_mode(dsi);
525 dsi_clk_hs_mode(dsi, 1);
526
527 mtk_dsi_start(dsi);
528
529 dsi->enabled = true;
530}
531
532static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
533{
534 if (!dsi->enabled)
535 return;
536
537 if (dsi->panel) {
538 if (drm_panel_disable(dsi->panel)) {
539 DRM_ERROR("failed to disable the panel\n");
540 return;
541 }
542 }
543
544 mtk_dsi_poweroff(dsi);
545
546 dsi->enabled = false;
547}
548
549static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
550{
551 drm_encoder_cleanup(encoder);
552}
553
554static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
555 .destroy = mtk_dsi_encoder_destroy,
556};
557
558static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
559 const struct drm_display_mode *mode,
560 struct drm_display_mode *adjusted_mode)
561{
562 return true;
563}
564
565static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
566 struct drm_display_mode *mode,
567 struct drm_display_mode *adjusted)
568{
569 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
570
571 dsi->vm.pixelclock = adjusted->clock;
572 dsi->vm.hactive = adjusted->hdisplay;
573 dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end;
574 dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay;
575 dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start;
576
577 dsi->vm.vactive = adjusted->vdisplay;
578 dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end;
579 dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay;
580 dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start;
581}
582
583static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
584{
585 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
586
587 mtk_output_dsi_disable(dsi);
588}
589
590static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
591{
592 struct mtk_dsi *dsi = encoder_to_dsi(encoder);
593
594 mtk_output_dsi_enable(dsi);
595}
596
597static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
598{
599 struct mtk_dsi *dsi = connector_to_dsi(connector);
600
601 return drm_panel_get_modes(dsi->panel);
602}
603
604static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
605 .mode_fixup = mtk_dsi_encoder_mode_fixup,
606 .mode_set = mtk_dsi_encoder_mode_set,
607 .disable = mtk_dsi_encoder_disable,
608 .enable = mtk_dsi_encoder_enable,
609};
610
611static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
612 .dpms = drm_atomic_helper_connector_dpms,
613 .fill_modes = drm_helper_probe_single_connector_modes,
614 .destroy = drm_connector_cleanup,
615 .reset = drm_atomic_helper_connector_reset,
616 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
617 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
618};
619
620static const struct drm_connector_helper_funcs
621 mtk_dsi_connector_helper_funcs = {
622 .get_modes = mtk_dsi_connector_get_modes,
623};
624
625static int mtk_drm_attach_bridge(struct drm_bridge *bridge,
626 struct drm_encoder *encoder)
627{
628 int ret;
629
630 if (!bridge)
631 return -ENOENT;
632
633 encoder->bridge = bridge;
634 bridge->encoder = encoder;
635 ret = drm_bridge_attach(encoder->dev, bridge);
636 if (ret) {
637 DRM_ERROR("Failed to attach bridge to drm\n");
638 encoder->bridge = NULL;
639 bridge->encoder = NULL;
640 }
641
642 return ret;
643}
644
645static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
646{
647 int ret;
648
649 ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
650 DRM_MODE_CONNECTOR_DSI);
651 if (ret) {
652 DRM_ERROR("Failed to connector init to drm\n");
653 return ret;
654 }
655
656 drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
657
658 dsi->conn.dpms = DRM_MODE_DPMS_OFF;
659 drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder);
660
661 if (dsi->panel) {
662 ret = drm_panel_attach(dsi->panel, &dsi->conn);
663 if (ret) {
664 DRM_ERROR("Failed to attach panel to drm\n");
665 goto err_connector_cleanup;
666 }
667 }
668
669 return 0;
670
671err_connector_cleanup:
672 drm_connector_cleanup(&dsi->conn);
673 return ret;
674}
675
676static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
677{
678 int ret;
679
680 ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
681 DRM_MODE_ENCODER_DSI, NULL);
682 if (ret) {
683 DRM_ERROR("Failed to encoder init to drm\n");
684 return ret;
685 }
686 drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
687
688 /*
689 * Currently display data paths are statically assigned to a crtc each.
690 * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
691 */
692 dsi->encoder.possible_crtcs = 1;
693
694 /* If there's a bridge, attach to it and let it create the connector */
695 ret = mtk_drm_attach_bridge(dsi->bridge, &dsi->encoder);
696 if (ret) {
697 /* Otherwise create our own connector and attach to a panel */
698 ret = mtk_dsi_create_connector(drm, dsi);
699 if (ret)
700 goto err_encoder_cleanup;
701 }
702
703 return 0;
704
705err_encoder_cleanup:
706 drm_encoder_cleanup(&dsi->encoder);
707 return ret;
708}
709
710static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
711{
712 drm_encoder_cleanup(&dsi->encoder);
713 /* Skip connector cleanup if creation was delegated to the bridge */
714 if (dsi->conn.dev)
715 drm_connector_cleanup(&dsi->conn);
716}
717
718static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
719{
720 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
721
722 mtk_dsi_poweron(dsi);
723}
724
725static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
726{
727 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
728
729 mtk_dsi_poweroff(dsi);
730}
731
732static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
733 .start = mtk_dsi_ddp_start,
734 .stop = mtk_dsi_ddp_stop,
735};
736
737static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
738 struct mipi_dsi_device *device)
739{
740 struct mtk_dsi *dsi = host_to_dsi(host);
741
742 dsi->lanes = device->lanes;
743 dsi->format = device->format;
744 dsi->mode_flags = device->mode_flags;
745
746 if (dsi->conn.dev)
747 drm_helper_hpd_irq_event(dsi->conn.dev);
748
749 return 0;
750}
751
752static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
753 struct mipi_dsi_device *device)
754{
755 struct mtk_dsi *dsi = host_to_dsi(host);
756
757 if (dsi->conn.dev)
758 drm_helper_hpd_irq_event(dsi->conn.dev);
759
760 return 0;
761}
762
763static const struct mipi_dsi_host_ops mtk_dsi_ops = {
764 .attach = mtk_dsi_host_attach,
765 .detach = mtk_dsi_host_detach,
766};
767
768static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
769{
770 int ret;
771 struct drm_device *drm = data;
772 struct mtk_dsi *dsi = dev_get_drvdata(dev);
773
774 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
775 if (ret < 0) {
776 dev_err(dev, "Failed to register component %s: %d\n",
777 dev->of_node->full_name, ret);
778 return ret;
779 }
780
781 ret = mipi_dsi_host_register(&dsi->host);
782 if (ret < 0) {
783 dev_err(dev, "failed to register DSI host: %d\n", ret);
784 goto err_ddp_comp_unregister;
785 }
786
787 ret = mtk_dsi_create_conn_enc(drm, dsi);
788 if (ret) {
789 DRM_ERROR("Encoder create failed with %d\n", ret);
790 goto err_unregister;
791 }
792
793 return 0;
794
795err_unregister:
796 mipi_dsi_host_unregister(&dsi->host);
797err_ddp_comp_unregister:
798 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
799 return ret;
800}
801
802static void mtk_dsi_unbind(struct device *dev, struct device *master,
803 void *data)
804{
805 struct drm_device *drm = data;
806 struct mtk_dsi *dsi = dev_get_drvdata(dev);
807
808 mtk_dsi_destroy_conn_enc(dsi);
809 mipi_dsi_host_unregister(&dsi->host);
810 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
811}
812
813static const struct component_ops mtk_dsi_component_ops = {
814 .bind = mtk_dsi_bind,
815 .unbind = mtk_dsi_unbind,
816};
817
818static int mtk_dsi_probe(struct platform_device *pdev)
819{
820 struct mtk_dsi *dsi;
821 struct device *dev = &pdev->dev;
822 struct device_node *remote_node, *endpoint;
823 struct resource *regs;
824 int comp_id;
825 int ret;
826
827 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
828 if (!dsi)
829 return -ENOMEM;
830
831 dsi->host.ops = &mtk_dsi_ops;
832 dsi->host.dev = dev;
833
834 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
835 if (endpoint) {
836 remote_node = of_graph_get_remote_port_parent(endpoint);
837 if (!remote_node) {
838 dev_err(dev, "No panel connected\n");
839 return -ENODEV;
840 }
841
842 dsi->bridge = of_drm_find_bridge(remote_node);
843 dsi->panel = of_drm_find_panel(remote_node);
844 of_node_put(remote_node);
845 if (!dsi->bridge && !dsi->panel) {
846 dev_info(dev, "Waiting for bridge or panel driver\n");
847 return -EPROBE_DEFER;
848 }
849 }
850
851 dsi->engine_clk = devm_clk_get(dev, "engine");
852 if (IS_ERR(dsi->engine_clk)) {
853 ret = PTR_ERR(dsi->engine_clk);
854 dev_err(dev, "Failed to get engine clock: %d\n", ret);
855 return ret;
856 }
857
858 dsi->digital_clk = devm_clk_get(dev, "digital");
859 if (IS_ERR(dsi->digital_clk)) {
860 ret = PTR_ERR(dsi->digital_clk);
861 dev_err(dev, "Failed to get digital clock: %d\n", ret);
862 return ret;
863 }
864
865 dsi->hs_clk = devm_clk_get(dev, "hs");
866 if (IS_ERR(dsi->hs_clk)) {
867 ret = PTR_ERR(dsi->hs_clk);
868 dev_err(dev, "Failed to get hs clock: %d\n", ret);
869 return ret;
870 }
871
872 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
873 dsi->regs = devm_ioremap_resource(dev, regs);
874 if (IS_ERR(dsi->regs)) {
875 ret = PTR_ERR(dsi->regs);
876 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
877 return ret;
878 }
879
880 dsi->phy = devm_phy_get(dev, "dphy");
881 if (IS_ERR(dsi->phy)) {
882 ret = PTR_ERR(dsi->phy);
883 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
884 return ret;
885 }
886
887 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
888 if (comp_id < 0) {
889 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
890 return comp_id;
891 }
892
893 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
894 &mtk_dsi_funcs);
895 if (ret) {
896 dev_err(dev, "Failed to initialize component: %d\n", ret);
897 return ret;
898 }
899
900 platform_set_drvdata(pdev, dsi);
901
902 return component_add(&pdev->dev, &mtk_dsi_component_ops);
903}
904
905static int mtk_dsi_remove(struct platform_device *pdev)
906{
907 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
908
909 mtk_output_dsi_disable(dsi);
910 component_del(&pdev->dev, &mtk_dsi_component_ops);
911
912 return 0;
913}
914
915static const struct of_device_id mtk_dsi_of_match[] = {
916 { .compatible = "mediatek,mt8173-dsi" },
917 { },
918};
919
920struct platform_driver mtk_dsi_driver = {
921 .probe = mtk_dsi_probe,
922 .remove = mtk_dsi_remove,
923 .driver = {
924 .name = "mtk-dsi",
925 .of_match_table = mtk_dsi_of_match,
926 },
927};