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1#include <linux/export.h>
2#include <linux/bitops.h>
3#include <linux/elf.h>
4#include <linux/mm.h>
5
6#include <linux/io.h>
7#include <linux/sched.h>
8#include <linux/sched/clock.h>
9#include <linux/random.h>
10#include <asm/processor.h>
11#include <asm/apic.h>
12#include <asm/cpu.h>
13#include <asm/spec-ctrl.h>
14#include <asm/smp.h>
15#include <asm/pci-direct.h>
16#include <asm/delay.h>
17
18#ifdef CONFIG_X86_64
19# include <asm/mmconfig.h>
20# include <asm/set_memory.h>
21#endif
22
23#include "cpu.h"
24
25static const int amd_erratum_383[];
26static const int amd_erratum_400[];
27static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
28
29/*
30 * nodes_per_socket: Stores the number of nodes per socket.
31 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
32 * Node Identifiers[10:8]
33 */
34static u32 nodes_per_socket = 1;
35
36static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
37{
38 u32 gprs[8] = { 0 };
39 int err;
40
41 WARN_ONCE((boot_cpu_data.x86 != 0xf),
42 "%s should only be used on K8!\n", __func__);
43
44 gprs[1] = msr;
45 gprs[7] = 0x9c5a203a;
46
47 err = rdmsr_safe_regs(gprs);
48
49 *p = gprs[0] | ((u64)gprs[2] << 32);
50
51 return err;
52}
53
54static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
55{
56 u32 gprs[8] = { 0 };
57
58 WARN_ONCE((boot_cpu_data.x86 != 0xf),
59 "%s should only be used on K8!\n", __func__);
60
61 gprs[0] = (u32)val;
62 gprs[1] = msr;
63 gprs[2] = val >> 32;
64 gprs[7] = 0x9c5a203a;
65
66 return wrmsr_safe_regs(gprs);
67}
68
69/*
70 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
71 * misexecution of code under Linux. Owners of such processors should
72 * contact AMD for precise details and a CPU swap.
73 *
74 * See http://www.multimania.com/poulot/k6bug.html
75 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
76 * (Publication # 21266 Issue Date: August 1998)
77 *
78 * The following test is erm.. interesting. AMD neglected to up
79 * the chip setting when fixing the bug but they also tweaked some
80 * performance at the same time..
81 */
82
83extern __visible void vide(void);
84__asm__(".globl vide\n"
85 ".type vide, @function\n"
86 ".align 4\n"
87 "vide: ret\n");
88
89static void init_amd_k5(struct cpuinfo_x86 *c)
90{
91#ifdef CONFIG_X86_32
92/*
93 * General Systems BIOSen alias the cpu frequency registers
94 * of the Elan at 0x000df000. Unfortunately, one of the Linux
95 * drivers subsequently pokes it, and changes the CPU speed.
96 * Workaround : Remove the unneeded alias.
97 */
98#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
99#define CBAR_ENB (0x80000000)
100#define CBAR_KEY (0X000000CB)
101 if (c->x86_model == 9 || c->x86_model == 10) {
102 if (inl(CBAR) & CBAR_ENB)
103 outl(0 | CBAR_KEY, CBAR);
104 }
105#endif
106}
107
108static void init_amd_k6(struct cpuinfo_x86 *c)
109{
110#ifdef CONFIG_X86_32
111 u32 l, h;
112 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
113
114 if (c->x86_model < 6) {
115 /* Based on AMD doc 20734R - June 2000 */
116 if (c->x86_model == 0) {
117 clear_cpu_cap(c, X86_FEATURE_APIC);
118 set_cpu_cap(c, X86_FEATURE_PGE);
119 }
120 return;
121 }
122
123 if (c->x86_model == 6 && c->x86_stepping == 1) {
124 const int K6_BUG_LOOP = 1000000;
125 int n;
126 void (*f_vide)(void);
127 u64 d, d2;
128
129 pr_info("AMD K6 stepping B detected - ");
130
131 /*
132 * It looks like AMD fixed the 2.6.2 bug and improved indirect
133 * calls at the same time.
134 */
135
136 n = K6_BUG_LOOP;
137 f_vide = vide;
138 OPTIMIZER_HIDE_VAR(f_vide);
139 d = rdtsc();
140 while (n--)
141 f_vide();
142 d2 = rdtsc();
143 d = d2-d;
144
145 if (d > 20*K6_BUG_LOOP)
146 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
147 else
148 pr_cont("probably OK (after B9730xxxx).\n");
149 }
150
151 /* K6 with old style WHCR */
152 if (c->x86_model < 8 ||
153 (c->x86_model == 8 && c->x86_stepping < 8)) {
154 /* We can only write allocate on the low 508Mb */
155 if (mbytes > 508)
156 mbytes = 508;
157
158 rdmsr(MSR_K6_WHCR, l, h);
159 if ((l&0x0000FFFF) == 0) {
160 unsigned long flags;
161 l = (1<<0)|((mbytes/4)<<1);
162 local_irq_save(flags);
163 wbinvd();
164 wrmsr(MSR_K6_WHCR, l, h);
165 local_irq_restore(flags);
166 pr_info("Enabling old style K6 write allocation for %d Mb\n",
167 mbytes);
168 }
169 return;
170 }
171
172 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
173 c->x86_model == 9 || c->x86_model == 13) {
174 /* The more serious chips .. */
175
176 if (mbytes > 4092)
177 mbytes = 4092;
178
179 rdmsr(MSR_K6_WHCR, l, h);
180 if ((l&0xFFFF0000) == 0) {
181 unsigned long flags;
182 l = ((mbytes>>2)<<22)|(1<<16);
183 local_irq_save(flags);
184 wbinvd();
185 wrmsr(MSR_K6_WHCR, l, h);
186 local_irq_restore(flags);
187 pr_info("Enabling new style K6 write allocation for %d Mb\n",
188 mbytes);
189 }
190
191 return;
192 }
193
194 if (c->x86_model == 10) {
195 /* AMD Geode LX is model 10 */
196 /* placeholder for any needed mods */
197 return;
198 }
199#endif
200}
201
202static void init_amd_k7(struct cpuinfo_x86 *c)
203{
204#ifdef CONFIG_X86_32
205 u32 l, h;
206
207 /*
208 * Bit 15 of Athlon specific MSR 15, needs to be 0
209 * to enable SSE on Palomino/Morgan/Barton CPU's.
210 * If the BIOS didn't enable it already, enable it here.
211 */
212 if (c->x86_model >= 6 && c->x86_model <= 10) {
213 if (!cpu_has(c, X86_FEATURE_XMM)) {
214 pr_info("Enabling disabled K7/SSE Support.\n");
215 msr_clear_bit(MSR_K7_HWCR, 15);
216 set_cpu_cap(c, X86_FEATURE_XMM);
217 }
218 }
219
220 /*
221 * It's been determined by AMD that Athlons since model 8 stepping 1
222 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
223 * As per AMD technical note 27212 0.2
224 */
225 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
226 rdmsr(MSR_K7_CLK_CTL, l, h);
227 if ((l & 0xfff00000) != 0x20000000) {
228 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
229 l, ((l & 0x000fffff)|0x20000000));
230 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
231 }
232 }
233
234 set_cpu_cap(c, X86_FEATURE_K7);
235
236 /* calling is from identify_secondary_cpu() ? */
237 if (!c->cpu_index)
238 return;
239
240 /*
241 * Certain Athlons might work (for various values of 'work') in SMP
242 * but they are not certified as MP capable.
243 */
244 /* Athlon 660/661 is valid. */
245 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
246 (c->x86_stepping == 1)))
247 return;
248
249 /* Duron 670 is valid */
250 if ((c->x86_model == 7) && (c->x86_stepping == 0))
251 return;
252
253 /*
254 * Athlon 662, Duron 671, and Athlon >model 7 have capability
255 * bit. It's worth noting that the A5 stepping (662) of some
256 * Athlon XP's have the MP bit set.
257 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
258 * more.
259 */
260 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
261 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
262 (c->x86_model > 7))
263 if (cpu_has(c, X86_FEATURE_MP))
264 return;
265
266 /* If we get here, not a certified SMP capable AMD system. */
267
268 /*
269 * Don't taint if we are running SMP kernel on a single non-MP
270 * approved Athlon
271 */
272 WARN_ONCE(1, "WARNING: This combination of AMD"
273 " processors is not suitable for SMP.\n");
274 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
275#endif
276}
277
278#ifdef CONFIG_NUMA
279/*
280 * To workaround broken NUMA config. Read the comment in
281 * srat_detect_node().
282 */
283static int nearby_node(int apicid)
284{
285 int i, node;
286
287 for (i = apicid - 1; i >= 0; i--) {
288 node = __apicid_to_node[i];
289 if (node != NUMA_NO_NODE && node_online(node))
290 return node;
291 }
292 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
293 node = __apicid_to_node[i];
294 if (node != NUMA_NO_NODE && node_online(node))
295 return node;
296 }
297 return first_node(node_online_map); /* Shouldn't happen */
298}
299#endif
300
301#ifdef CONFIG_SMP
302/*
303 * Fix up cpu_core_id for pre-F17h systems to be in the
304 * [0 .. cores_per_node - 1] range. Not really needed but
305 * kept so as not to break existing setups.
306 */
307static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
308{
309 u32 cus_per_node;
310
311 if (c->x86 >= 0x17)
312 return;
313
314 cus_per_node = c->x86_max_cores / nodes_per_socket;
315 c->cpu_core_id %= cus_per_node;
316}
317
318/*
319 * Fixup core topology information for
320 * (1) AMD multi-node processors
321 * Assumption: Number of cores in each internal node is the same.
322 * (2) AMD processors supporting compute units
323 */
324static void amd_get_topology(struct cpuinfo_x86 *c)
325{
326 u8 node_id;
327 int cpu = smp_processor_id();
328
329 /* get information required for multi-node processors */
330 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
331 u32 eax, ebx, ecx, edx;
332
333 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
334
335 node_id = ecx & 0xff;
336 smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
337
338 if (c->x86 == 0x15)
339 c->cu_id = ebx & 0xff;
340
341 if (c->x86 >= 0x17) {
342 c->cpu_core_id = ebx & 0xff;
343
344 if (smp_num_siblings > 1)
345 c->x86_max_cores /= smp_num_siblings;
346 }
347
348 /*
349 * We may have multiple LLCs if L3 caches exist, so check if we
350 * have an L3 cache by looking at the L3 cache CPUID leaf.
351 */
352 if (cpuid_edx(0x80000006)) {
353 if (c->x86 == 0x17) {
354 /*
355 * LLC is at the core complex level.
356 * Core complex id is ApicId[3].
357 */
358 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
359 } else {
360 /* LLC is at the node level. */
361 per_cpu(cpu_llc_id, cpu) = node_id;
362 }
363 }
364 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
365 u64 value;
366
367 rdmsrl(MSR_FAM10H_NODE_ID, value);
368 node_id = value & 7;
369
370 per_cpu(cpu_llc_id, cpu) = node_id;
371 } else
372 return;
373
374 if (nodes_per_socket > 1) {
375 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
376 legacy_fixup_core_id(c);
377 }
378}
379#endif
380
381/*
382 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
383 * Assumes number of cores is a power of two.
384 */
385static void amd_detect_cmp(struct cpuinfo_x86 *c)
386{
387#ifdef CONFIG_SMP
388 unsigned bits;
389 int cpu = smp_processor_id();
390
391 bits = c->x86_coreid_bits;
392 /* Low order bits define the core id (index of core in socket) */
393 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
394 /* Convert the initial APIC ID into the socket ID */
395 c->phys_proc_id = c->initial_apicid >> bits;
396 /* use socket ID also for last level cache */
397 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
398 amd_get_topology(c);
399#endif
400}
401
402u16 amd_get_nb_id(int cpu)
403{
404 u16 id = 0;
405#ifdef CONFIG_SMP
406 id = per_cpu(cpu_llc_id, cpu);
407#endif
408 return id;
409}
410EXPORT_SYMBOL_GPL(amd_get_nb_id);
411
412u32 amd_get_nodes_per_socket(void)
413{
414 return nodes_per_socket;
415}
416EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
417
418static void srat_detect_node(struct cpuinfo_x86 *c)
419{
420#ifdef CONFIG_NUMA
421 int cpu = smp_processor_id();
422 int node;
423 unsigned apicid = c->apicid;
424
425 node = numa_cpu_node(cpu);
426 if (node == NUMA_NO_NODE)
427 node = per_cpu(cpu_llc_id, cpu);
428
429 /*
430 * On multi-fabric platform (e.g. Numascale NumaChip) a
431 * platform-specific handler needs to be called to fixup some
432 * IDs of the CPU.
433 */
434 if (x86_cpuinit.fixup_cpu_id)
435 x86_cpuinit.fixup_cpu_id(c, node);
436
437 if (!node_online(node)) {
438 /*
439 * Two possibilities here:
440 *
441 * - The CPU is missing memory and no node was created. In
442 * that case try picking one from a nearby CPU.
443 *
444 * - The APIC IDs differ from the HyperTransport node IDs
445 * which the K8 northbridge parsing fills in. Assume
446 * they are all increased by a constant offset, but in
447 * the same order as the HT nodeids. If that doesn't
448 * result in a usable node fall back to the path for the
449 * previous case.
450 *
451 * This workaround operates directly on the mapping between
452 * APIC ID and NUMA node, assuming certain relationship
453 * between APIC ID, HT node ID and NUMA topology. As going
454 * through CPU mapping may alter the outcome, directly
455 * access __apicid_to_node[].
456 */
457 int ht_nodeid = c->initial_apicid;
458
459 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
460 node = __apicid_to_node[ht_nodeid];
461 /* Pick a nearby node */
462 if (!node_online(node))
463 node = nearby_node(apicid);
464 }
465 numa_set_node(cpu, node);
466#endif
467}
468
469static void early_init_amd_mc(struct cpuinfo_x86 *c)
470{
471#ifdef CONFIG_SMP
472 unsigned bits, ecx;
473
474 /* Multi core CPU? */
475 if (c->extended_cpuid_level < 0x80000008)
476 return;
477
478 ecx = cpuid_ecx(0x80000008);
479
480 c->x86_max_cores = (ecx & 0xff) + 1;
481
482 /* CPU telling us the core id bits shift? */
483 bits = (ecx >> 12) & 0xF;
484
485 /* Otherwise recompute */
486 if (bits == 0) {
487 while ((1 << bits) < c->x86_max_cores)
488 bits++;
489 }
490
491 c->x86_coreid_bits = bits;
492#endif
493}
494
495static void bsp_init_amd(struct cpuinfo_x86 *c)
496{
497
498#ifdef CONFIG_X86_64
499 if (c->x86 >= 0xf) {
500 unsigned long long tseg;
501
502 /*
503 * Split up direct mapping around the TSEG SMM area.
504 * Don't do it for gbpages because there seems very little
505 * benefit in doing so.
506 */
507 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
508 unsigned long pfn = tseg >> PAGE_SHIFT;
509
510 pr_debug("tseg: %010llx\n", tseg);
511 if (pfn_range_is_mapped(pfn, pfn + 1))
512 set_memory_4k((unsigned long)__va(tseg), 1);
513 }
514 }
515#endif
516
517 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
518
519 if (c->x86 > 0x10 ||
520 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
521 u64 val;
522
523 rdmsrl(MSR_K7_HWCR, val);
524 if (!(val & BIT(24)))
525 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
526 }
527 }
528
529 if (c->x86 == 0x15) {
530 unsigned long upperbit;
531 u32 cpuid, assoc;
532
533 cpuid = cpuid_edx(0x80000005);
534 assoc = cpuid >> 16 & 0xff;
535 upperbit = ((cpuid >> 24) << 10) / assoc;
536
537 va_align.mask = (upperbit - 1) & PAGE_MASK;
538 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
539
540 /* A random value per boot for bit slice [12:upper_bit) */
541 va_align.bits = get_random_int() & va_align.mask;
542 }
543
544 if (cpu_has(c, X86_FEATURE_MWAITX))
545 use_mwaitx_delay();
546
547 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
548 u32 ecx;
549
550 ecx = cpuid_ecx(0x8000001e);
551 nodes_per_socket = ((ecx >> 8) & 7) + 1;
552 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
553 u64 value;
554
555 rdmsrl(MSR_FAM10H_NODE_ID, value);
556 nodes_per_socket = ((value >> 3) & 7) + 1;
557 }
558
559 if (c->x86 >= 0x15 && c->x86 <= 0x17) {
560 unsigned int bit;
561
562 switch (c->x86) {
563 case 0x15: bit = 54; break;
564 case 0x16: bit = 33; break;
565 case 0x17: bit = 10; break;
566 default: return;
567 }
568 /*
569 * Try to cache the base value so further operations can
570 * avoid RMW. If that faults, do not enable SSBD.
571 */
572 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
573 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
574 setup_force_cpu_cap(X86_FEATURE_SSBD);
575 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
576 }
577 }
578}
579
580static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
581{
582 u64 msr;
583
584 /*
585 * BIOS support is required for SME and SEV.
586 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
587 * the SME physical address space reduction value.
588 * If BIOS has not enabled SME then don't advertise the
589 * SME feature (set in scattered.c).
590 * For SEV: If BIOS has not enabled SEV then don't advertise the
591 * SEV feature (set in scattered.c).
592 *
593 * In all cases, since support for SME and SEV requires long mode,
594 * don't advertise the feature under CONFIG_X86_32.
595 */
596 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
597 /* Check if memory encryption is enabled */
598 rdmsrl(MSR_K8_SYSCFG, msr);
599 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
600 goto clear_all;
601
602 /*
603 * Always adjust physical address bits. Even though this
604 * will be a value above 32-bits this is still done for
605 * CONFIG_X86_32 so that accurate values are reported.
606 */
607 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
608
609 if (IS_ENABLED(CONFIG_X86_32))
610 goto clear_all;
611
612 rdmsrl(MSR_K7_HWCR, msr);
613 if (!(msr & MSR_K7_HWCR_SMMLOCK))
614 goto clear_sev;
615
616 return;
617
618clear_all:
619 clear_cpu_cap(c, X86_FEATURE_SME);
620clear_sev:
621 clear_cpu_cap(c, X86_FEATURE_SEV);
622 }
623}
624
625static void early_init_amd(struct cpuinfo_x86 *c)
626{
627 u32 dummy;
628
629 early_init_amd_mc(c);
630
631 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
632
633 /*
634 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
635 * with P/T states and does not stop in deep C-states
636 */
637 if (c->x86_power & (1 << 8)) {
638 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
639 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
640 }
641
642 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
643 if (c->x86_power & BIT(12))
644 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
645
646#ifdef CONFIG_X86_64
647 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
648#else
649 /* Set MTRR capability flag if appropriate */
650 if (c->x86 == 5)
651 if (c->x86_model == 13 || c->x86_model == 9 ||
652 (c->x86_model == 8 && c->x86_stepping >= 8))
653 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
654#endif
655#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
656 /*
657 * ApicID can always be treated as an 8-bit value for AMD APIC versions
658 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
659 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
660 * after 16h.
661 */
662 if (boot_cpu_has(X86_FEATURE_APIC)) {
663 if (c->x86 > 0x16)
664 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
665 else if (c->x86 >= 0xf) {
666 /* check CPU config space for extended APIC ID */
667 unsigned int val;
668
669 val = read_pci_config(0, 24, 0, 0x68);
670 if ((val >> 17 & 0x3) == 0x3)
671 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
672 }
673 }
674#endif
675
676 /*
677 * This is only needed to tell the kernel whether to use VMCALL
678 * and VMMCALL. VMMCALL is never executed except under virt, so
679 * we can set it unconditionally.
680 */
681 set_cpu_cap(c, X86_FEATURE_VMMCALL);
682
683 /* F16h erratum 793, CVE-2013-6885 */
684 if (c->x86 == 0x16 && c->x86_model <= 0xf)
685 msr_set_bit(MSR_AMD64_LS_CFG, 15);
686
687 /*
688 * Check whether the machine is affected by erratum 400. This is
689 * used to select the proper idle routine and to enable the check
690 * whether the machine is affected in arch_post_acpi_init(), which
691 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
692 */
693 if (cpu_has_amd_erratum(c, amd_erratum_400))
694 set_cpu_bug(c, X86_BUG_AMD_E400);
695
696 early_detect_mem_encrypt(c);
697}
698
699static void init_amd_k8(struct cpuinfo_x86 *c)
700{
701 u32 level;
702 u64 value;
703
704 /* On C+ stepping K8 rep microcode works well for copy/memset */
705 level = cpuid_eax(1);
706 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
707 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
708
709 /*
710 * Some BIOSes incorrectly force this feature, but only K8 revision D
711 * (model = 0x14) and later actually support it.
712 * (AMD Erratum #110, docId: 25759).
713 */
714 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
715 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
716 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
717 value &= ~BIT_64(32);
718 wrmsrl_amd_safe(0xc001100d, value);
719 }
720 }
721
722 if (!c->x86_model_id[0])
723 strcpy(c->x86_model_id, "Hammer");
724
725#ifdef CONFIG_SMP
726 /*
727 * Disable TLB flush filter by setting HWCR.FFDIS on K8
728 * bit 6 of msr C001_0015
729 *
730 * Errata 63 for SH-B3 steppings
731 * Errata 122 for all steppings (F+ have it disabled by default)
732 */
733 msr_set_bit(MSR_K7_HWCR, 6);
734#endif
735 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
736}
737
738static void init_amd_gh(struct cpuinfo_x86 *c)
739{
740#ifdef CONFIG_MMCONF_FAM10H
741 /* do this for boot cpu */
742 if (c == &boot_cpu_data)
743 check_enable_amd_mmconf_dmi();
744
745 fam10h_check_enable_mmcfg();
746#endif
747
748 /*
749 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
750 * is always needed when GART is enabled, even in a kernel which has no
751 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
752 * If it doesn't, we do it here as suggested by the BKDG.
753 *
754 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
755 */
756 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
757
758 /*
759 * On family 10h BIOS may not have properly enabled WC+ support, causing
760 * it to be converted to CD memtype. This may result in performance
761 * degradation for certain nested-paging guests. Prevent this conversion
762 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
763 *
764 * NOTE: we want to use the _safe accessors so as not to #GP kvm
765 * guests on older kvm hosts.
766 */
767 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
768
769 if (cpu_has_amd_erratum(c, amd_erratum_383))
770 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
771}
772
773#define MSR_AMD64_DE_CFG 0xC0011029
774
775static void init_amd_ln(struct cpuinfo_x86 *c)
776{
777 /*
778 * Apply erratum 665 fix unconditionally so machines without a BIOS
779 * fix work.
780 */
781 msr_set_bit(MSR_AMD64_DE_CFG, 31);
782}
783
784static void init_amd_bd(struct cpuinfo_x86 *c)
785{
786 u64 value;
787
788 /* re-enable TopologyExtensions if switched off by BIOS */
789 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
790 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
791
792 if (msr_set_bit(0xc0011005, 54) > 0) {
793 rdmsrl(0xc0011005, value);
794 if (value & BIT_64(54)) {
795 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
796 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
797 }
798 }
799 }
800
801 /*
802 * The way access filter has a performance penalty on some workloads.
803 * Disable it on the affected CPUs.
804 */
805 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
806 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
807 value |= 0x1E;
808 wrmsrl_safe(MSR_F15H_IC_CFG, value);
809 }
810 }
811}
812
813static void init_amd_zn(struct cpuinfo_x86 *c)
814{
815 set_cpu_cap(c, X86_FEATURE_ZEN);
816 /*
817 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
818 * all up to and including B1.
819 */
820 if (c->x86_model <= 1 && c->x86_stepping <= 1)
821 set_cpu_cap(c, X86_FEATURE_CPB);
822}
823
824static void init_amd(struct cpuinfo_x86 *c)
825{
826 early_init_amd(c);
827
828 /*
829 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
830 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
831 */
832 clear_cpu_cap(c, 0*32+31);
833
834 if (c->x86 >= 0x10)
835 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
836
837 /* get apicid instead of initial apic id from cpuid */
838 c->apicid = hard_smp_processor_id();
839
840 /* K6s reports MCEs but don't actually have all the MSRs */
841 if (c->x86 < 6)
842 clear_cpu_cap(c, X86_FEATURE_MCE);
843
844 switch (c->x86) {
845 case 4: init_amd_k5(c); break;
846 case 5: init_amd_k6(c); break;
847 case 6: init_amd_k7(c); break;
848 case 0xf: init_amd_k8(c); break;
849 case 0x10: init_amd_gh(c); break;
850 case 0x12: init_amd_ln(c); break;
851 case 0x15: init_amd_bd(c); break;
852 case 0x17: init_amd_zn(c); break;
853 }
854
855 /*
856 * Enable workaround for FXSAVE leak on CPUs
857 * without a XSaveErPtr feature
858 */
859 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
860 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
861
862 cpu_detect_cache_sizes(c);
863
864 /* Multi core CPU? */
865 if (c->extended_cpuid_level >= 0x80000008) {
866 amd_detect_cmp(c);
867 srat_detect_node(c);
868 }
869
870#ifdef CONFIG_X86_32
871 detect_ht(c);
872#endif
873
874 init_amd_cacheinfo(c);
875
876 if (c->x86 >= 0xf)
877 set_cpu_cap(c, X86_FEATURE_K8);
878
879 if (cpu_has(c, X86_FEATURE_XMM2)) {
880 unsigned long long val;
881 int ret;
882
883 /*
884 * A serializing LFENCE has less overhead than MFENCE, so
885 * use it for execution serialization. On families which
886 * don't have that MSR, LFENCE is already serializing.
887 * msr_set_bit() uses the safe accessors, too, even if the MSR
888 * is not present.
889 */
890 msr_set_bit(MSR_F10H_DECFG,
891 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
892
893 /*
894 * Verify that the MSR write was successful (could be running
895 * under a hypervisor) and only then assume that LFENCE is
896 * serializing.
897 */
898 ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
899 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
900 /* A serializing LFENCE stops RDTSC speculation */
901 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
902 } else {
903 /* MFENCE stops RDTSC speculation */
904 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
905 }
906 }
907
908 /*
909 * Family 0x12 and above processors have APIC timer
910 * running in deep C states.
911 */
912 if (c->x86 > 0x11)
913 set_cpu_cap(c, X86_FEATURE_ARAT);
914
915 /* 3DNow or LM implies PREFETCHW */
916 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
917 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
918 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
919
920 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
921 if (!cpu_has(c, X86_FEATURE_XENPV))
922 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
923}
924
925#ifdef CONFIG_X86_32
926static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
927{
928 /* AMD errata T13 (order #21922) */
929 if ((c->x86 == 6)) {
930 /* Duron Rev A0 */
931 if (c->x86_model == 3 && c->x86_stepping == 0)
932 size = 64;
933 /* Tbird rev A1/A2 */
934 if (c->x86_model == 4 &&
935 (c->x86_stepping == 0 || c->x86_stepping == 1))
936 size = 256;
937 }
938 return size;
939}
940#endif
941
942static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
943{
944 u32 ebx, eax, ecx, edx;
945 u16 mask = 0xfff;
946
947 if (c->x86 < 0xf)
948 return;
949
950 if (c->extended_cpuid_level < 0x80000006)
951 return;
952
953 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
954
955 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
956 tlb_lli_4k[ENTRIES] = ebx & mask;
957
958 /*
959 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
960 * characteristics from the CPUID function 0x80000005 instead.
961 */
962 if (c->x86 == 0xf) {
963 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
964 mask = 0xff;
965 }
966
967 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
968 if (!((eax >> 16) & mask))
969 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
970 else
971 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
972
973 /* a 4M entry uses two 2M entries */
974 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
975
976 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
977 if (!(eax & mask)) {
978 /* Erratum 658 */
979 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
980 tlb_lli_2m[ENTRIES] = 1024;
981 } else {
982 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
983 tlb_lli_2m[ENTRIES] = eax & 0xff;
984 }
985 } else
986 tlb_lli_2m[ENTRIES] = eax & mask;
987
988 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
989}
990
991static const struct cpu_dev amd_cpu_dev = {
992 .c_vendor = "AMD",
993 .c_ident = { "AuthenticAMD" },
994#ifdef CONFIG_X86_32
995 .legacy_models = {
996 { .family = 4, .model_names =
997 {
998 [3] = "486 DX/2",
999 [7] = "486 DX/2-WB",
1000 [8] = "486 DX/4",
1001 [9] = "486 DX/4-WB",
1002 [14] = "Am5x86-WT",
1003 [15] = "Am5x86-WB"
1004 }
1005 },
1006 },
1007 .legacy_cache_size = amd_size_cache,
1008#endif
1009 .c_early_init = early_init_amd,
1010 .c_detect_tlb = cpu_detect_tlb_amd,
1011 .c_bsp_init = bsp_init_amd,
1012 .c_init = init_amd,
1013 .c_x86_vendor = X86_VENDOR_AMD,
1014};
1015
1016cpu_dev_register(amd_cpu_dev);
1017
1018/*
1019 * AMD errata checking
1020 *
1021 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1022 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1023 * have an OSVW id assigned, which it takes as first argument. Both take a
1024 * variable number of family-specific model-stepping ranges created by
1025 * AMD_MODEL_RANGE().
1026 *
1027 * Example:
1028 *
1029 * const int amd_erratum_319[] =
1030 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1031 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1032 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1033 */
1034
1035#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1036#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1037#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1038 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1039#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1040#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1041#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1042
1043static const int amd_erratum_400[] =
1044 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1045 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1046
1047static const int amd_erratum_383[] =
1048 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1049
1050
1051static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1052{
1053 int osvw_id = *erratum++;
1054 u32 range;
1055 u32 ms;
1056
1057 if (osvw_id >= 0 && osvw_id < 65536 &&
1058 cpu_has(cpu, X86_FEATURE_OSVW)) {
1059 u64 osvw_len;
1060
1061 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1062 if (osvw_id < osvw_len) {
1063 u64 osvw_bits;
1064
1065 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1066 osvw_bits);
1067 return osvw_bits & (1ULL << (osvw_id & 0x3f));
1068 }
1069 }
1070
1071 /* OSVW unavailable or ID unknown, match family-model-stepping range */
1072 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1073 while ((range = *erratum++))
1074 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1075 (ms >= AMD_MODEL_RANGE_START(range)) &&
1076 (ms <= AMD_MODEL_RANGE_END(range)))
1077 return true;
1078
1079 return false;
1080}
1081
1082void set_dr_addr_mask(unsigned long mask, int dr)
1083{
1084 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1085 return;
1086
1087 switch (dr) {
1088 case 0:
1089 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1090 break;
1091 case 1:
1092 case 2:
1093 case 3:
1094 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1095 break;
1096 default:
1097 break;
1098 }
1099}
1#include <linux/export.h>
2#include <linux/bitops.h>
3#include <linux/elf.h>
4#include <linux/mm.h>
5
6#include <linux/io.h>
7#include <linux/sched.h>
8#include <linux/random.h>
9#include <asm/processor.h>
10#include <asm/apic.h>
11#include <asm/cpu.h>
12#include <asm/smp.h>
13#include <asm/pci-direct.h>
14#include <asm/delay.h>
15
16#ifdef CONFIG_X86_64
17# include <asm/mmconfig.h>
18# include <asm/cacheflush.h>
19#endif
20
21#include "cpu.h"
22
23static const int amd_erratum_383[];
24static const int amd_erratum_400[];
25static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
26
27/*
28 * nodes_per_socket: Stores the number of nodes per socket.
29 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
30 * Node Identifiers[10:8]
31 */
32static u32 nodes_per_socket = 1;
33
34static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
35{
36 u32 gprs[8] = { 0 };
37 int err;
38
39 WARN_ONCE((boot_cpu_data.x86 != 0xf),
40 "%s should only be used on K8!\n", __func__);
41
42 gprs[1] = msr;
43 gprs[7] = 0x9c5a203a;
44
45 err = rdmsr_safe_regs(gprs);
46
47 *p = gprs[0] | ((u64)gprs[2] << 32);
48
49 return err;
50}
51
52static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
53{
54 u32 gprs[8] = { 0 };
55
56 WARN_ONCE((boot_cpu_data.x86 != 0xf),
57 "%s should only be used on K8!\n", __func__);
58
59 gprs[0] = (u32)val;
60 gprs[1] = msr;
61 gprs[2] = val >> 32;
62 gprs[7] = 0x9c5a203a;
63
64 return wrmsr_safe_regs(gprs);
65}
66
67/*
68 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
69 * misexecution of code under Linux. Owners of such processors should
70 * contact AMD for precise details and a CPU swap.
71 *
72 * See http://www.multimania.com/poulot/k6bug.html
73 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
74 * (Publication # 21266 Issue Date: August 1998)
75 *
76 * The following test is erm.. interesting. AMD neglected to up
77 * the chip setting when fixing the bug but they also tweaked some
78 * performance at the same time..
79 */
80
81extern __visible void vide(void);
82__asm__(".globl vide\n"
83 ".type vide, @function\n"
84 ".align 4\n"
85 "vide: ret\n");
86
87static void init_amd_k5(struct cpuinfo_x86 *c)
88{
89#ifdef CONFIG_X86_32
90/*
91 * General Systems BIOSen alias the cpu frequency registers
92 * of the Elan at 0x000df000. Unfortunately, one of the Linux
93 * drivers subsequently pokes it, and changes the CPU speed.
94 * Workaround : Remove the unneeded alias.
95 */
96#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
97#define CBAR_ENB (0x80000000)
98#define CBAR_KEY (0X000000CB)
99 if (c->x86_model == 9 || c->x86_model == 10) {
100 if (inl(CBAR) & CBAR_ENB)
101 outl(0 | CBAR_KEY, CBAR);
102 }
103#endif
104}
105
106static void init_amd_k6(struct cpuinfo_x86 *c)
107{
108#ifdef CONFIG_X86_32
109 u32 l, h;
110 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
111
112 if (c->x86_model < 6) {
113 /* Based on AMD doc 20734R - June 2000 */
114 if (c->x86_model == 0) {
115 clear_cpu_cap(c, X86_FEATURE_APIC);
116 set_cpu_cap(c, X86_FEATURE_PGE);
117 }
118 return;
119 }
120
121 if (c->x86_model == 6 && c->x86_mask == 1) {
122 const int K6_BUG_LOOP = 1000000;
123 int n;
124 void (*f_vide)(void);
125 u64 d, d2;
126
127 pr_info("AMD K6 stepping B detected - ");
128
129 /*
130 * It looks like AMD fixed the 2.6.2 bug and improved indirect
131 * calls at the same time.
132 */
133
134 n = K6_BUG_LOOP;
135 f_vide = vide;
136 d = rdtsc();
137 while (n--)
138 f_vide();
139 d2 = rdtsc();
140 d = d2-d;
141
142 if (d > 20*K6_BUG_LOOP)
143 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
144 else
145 pr_cont("probably OK (after B9730xxxx).\n");
146 }
147
148 /* K6 with old style WHCR */
149 if (c->x86_model < 8 ||
150 (c->x86_model == 8 && c->x86_mask < 8)) {
151 /* We can only write allocate on the low 508Mb */
152 if (mbytes > 508)
153 mbytes = 508;
154
155 rdmsr(MSR_K6_WHCR, l, h);
156 if ((l&0x0000FFFF) == 0) {
157 unsigned long flags;
158 l = (1<<0)|((mbytes/4)<<1);
159 local_irq_save(flags);
160 wbinvd();
161 wrmsr(MSR_K6_WHCR, l, h);
162 local_irq_restore(flags);
163 pr_info("Enabling old style K6 write allocation for %d Mb\n",
164 mbytes);
165 }
166 return;
167 }
168
169 if ((c->x86_model == 8 && c->x86_mask > 7) ||
170 c->x86_model == 9 || c->x86_model == 13) {
171 /* The more serious chips .. */
172
173 if (mbytes > 4092)
174 mbytes = 4092;
175
176 rdmsr(MSR_K6_WHCR, l, h);
177 if ((l&0xFFFF0000) == 0) {
178 unsigned long flags;
179 l = ((mbytes>>2)<<22)|(1<<16);
180 local_irq_save(flags);
181 wbinvd();
182 wrmsr(MSR_K6_WHCR, l, h);
183 local_irq_restore(flags);
184 pr_info("Enabling new style K6 write allocation for %d Mb\n",
185 mbytes);
186 }
187
188 return;
189 }
190
191 if (c->x86_model == 10) {
192 /* AMD Geode LX is model 10 */
193 /* placeholder for any needed mods */
194 return;
195 }
196#endif
197}
198
199static void init_amd_k7(struct cpuinfo_x86 *c)
200{
201#ifdef CONFIG_X86_32
202 u32 l, h;
203
204 /*
205 * Bit 15 of Athlon specific MSR 15, needs to be 0
206 * to enable SSE on Palomino/Morgan/Barton CPU's.
207 * If the BIOS didn't enable it already, enable it here.
208 */
209 if (c->x86_model >= 6 && c->x86_model <= 10) {
210 if (!cpu_has(c, X86_FEATURE_XMM)) {
211 pr_info("Enabling disabled K7/SSE Support.\n");
212 msr_clear_bit(MSR_K7_HWCR, 15);
213 set_cpu_cap(c, X86_FEATURE_XMM);
214 }
215 }
216
217 /*
218 * It's been determined by AMD that Athlons since model 8 stepping 1
219 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
220 * As per AMD technical note 27212 0.2
221 */
222 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
223 rdmsr(MSR_K7_CLK_CTL, l, h);
224 if ((l & 0xfff00000) != 0x20000000) {
225 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
226 l, ((l & 0x000fffff)|0x20000000));
227 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
228 }
229 }
230
231 set_cpu_cap(c, X86_FEATURE_K7);
232
233 /* calling is from identify_secondary_cpu() ? */
234 if (!c->cpu_index)
235 return;
236
237 /*
238 * Certain Athlons might work (for various values of 'work') in SMP
239 * but they are not certified as MP capable.
240 */
241 /* Athlon 660/661 is valid. */
242 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
243 (c->x86_mask == 1)))
244 return;
245
246 /* Duron 670 is valid */
247 if ((c->x86_model == 7) && (c->x86_mask == 0))
248 return;
249
250 /*
251 * Athlon 662, Duron 671, and Athlon >model 7 have capability
252 * bit. It's worth noting that the A5 stepping (662) of some
253 * Athlon XP's have the MP bit set.
254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
255 * more.
256 */
257 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
258 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
259 (c->x86_model > 7))
260 if (cpu_has(c, X86_FEATURE_MP))
261 return;
262
263 /* If we get here, not a certified SMP capable AMD system. */
264
265 /*
266 * Don't taint if we are running SMP kernel on a single non-MP
267 * approved Athlon
268 */
269 WARN_ONCE(1, "WARNING: This combination of AMD"
270 " processors is not suitable for SMP.\n");
271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
272#endif
273}
274
275#ifdef CONFIG_NUMA
276/*
277 * To workaround broken NUMA config. Read the comment in
278 * srat_detect_node().
279 */
280static int nearby_node(int apicid)
281{
282 int i, node;
283
284 for (i = apicid - 1; i >= 0; i--) {
285 node = __apicid_to_node[i];
286 if (node != NUMA_NO_NODE && node_online(node))
287 return node;
288 }
289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
290 node = __apicid_to_node[i];
291 if (node != NUMA_NO_NODE && node_online(node))
292 return node;
293 }
294 return first_node(node_online_map); /* Shouldn't happen */
295}
296#endif
297
298/*
299 * Fixup core topology information for
300 * (1) AMD multi-node processors
301 * Assumption: Number of cores in each internal node is the same.
302 * (2) AMD processors supporting compute units
303 */
304#ifdef CONFIG_SMP
305static void amd_get_topology(struct cpuinfo_x86 *c)
306{
307 u8 node_id;
308 int cpu = smp_processor_id();
309
310 /* get information required for multi-node processors */
311 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
312 u32 eax, ebx, ecx, edx;
313
314 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
315
316 node_id = ecx & 0xff;
317 smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
318
319 if (c->x86 == 0x15)
320 c->cu_id = ebx & 0xff;
321
322 if (c->x86 >= 0x17) {
323 c->cpu_core_id = ebx & 0xff;
324
325 if (smp_num_siblings > 1)
326 c->x86_max_cores /= smp_num_siblings;
327 }
328
329 /*
330 * We may have multiple LLCs if L3 caches exist, so check if we
331 * have an L3 cache by looking at the L3 cache CPUID leaf.
332 */
333 if (cpuid_edx(0x80000006)) {
334 if (c->x86 == 0x17) {
335 /*
336 * LLC is at the core complex level.
337 * Core complex id is ApicId[3].
338 */
339 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
340 } else {
341 /* LLC is at the node level. */
342 per_cpu(cpu_llc_id, cpu) = node_id;
343 }
344 }
345 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
346 u64 value;
347
348 rdmsrl(MSR_FAM10H_NODE_ID, value);
349 node_id = value & 7;
350
351 per_cpu(cpu_llc_id, cpu) = node_id;
352 } else
353 return;
354
355 /* fixup multi-node processor information */
356 if (nodes_per_socket > 1) {
357 u32 cus_per_node;
358
359 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
360 cus_per_node = c->x86_max_cores / nodes_per_socket;
361
362 /* core id has to be in the [0 .. cores_per_node - 1] range */
363 c->cpu_core_id %= cus_per_node;
364 }
365}
366#endif
367
368/*
369 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
370 * Assumes number of cores is a power of two.
371 */
372static void amd_detect_cmp(struct cpuinfo_x86 *c)
373{
374#ifdef CONFIG_SMP
375 unsigned bits;
376 int cpu = smp_processor_id();
377
378 bits = c->x86_coreid_bits;
379 /* Low order bits define the core id (index of core in socket) */
380 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
381 /* Convert the initial APIC ID into the socket ID */
382 c->phys_proc_id = c->initial_apicid >> bits;
383 /* use socket ID also for last level cache */
384 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
385 amd_get_topology(c);
386#endif
387}
388
389u16 amd_get_nb_id(int cpu)
390{
391 u16 id = 0;
392#ifdef CONFIG_SMP
393 id = per_cpu(cpu_llc_id, cpu);
394#endif
395 return id;
396}
397EXPORT_SYMBOL_GPL(amd_get_nb_id);
398
399u32 amd_get_nodes_per_socket(void)
400{
401 return nodes_per_socket;
402}
403EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
404
405static void srat_detect_node(struct cpuinfo_x86 *c)
406{
407#ifdef CONFIG_NUMA
408 int cpu = smp_processor_id();
409 int node;
410 unsigned apicid = c->apicid;
411
412 node = numa_cpu_node(cpu);
413 if (node == NUMA_NO_NODE)
414 node = per_cpu(cpu_llc_id, cpu);
415
416 /*
417 * On multi-fabric platform (e.g. Numascale NumaChip) a
418 * platform-specific handler needs to be called to fixup some
419 * IDs of the CPU.
420 */
421 if (x86_cpuinit.fixup_cpu_id)
422 x86_cpuinit.fixup_cpu_id(c, node);
423
424 if (!node_online(node)) {
425 /*
426 * Two possibilities here:
427 *
428 * - The CPU is missing memory and no node was created. In
429 * that case try picking one from a nearby CPU.
430 *
431 * - The APIC IDs differ from the HyperTransport node IDs
432 * which the K8 northbridge parsing fills in. Assume
433 * they are all increased by a constant offset, but in
434 * the same order as the HT nodeids. If that doesn't
435 * result in a usable node fall back to the path for the
436 * previous case.
437 *
438 * This workaround operates directly on the mapping between
439 * APIC ID and NUMA node, assuming certain relationship
440 * between APIC ID, HT node ID and NUMA topology. As going
441 * through CPU mapping may alter the outcome, directly
442 * access __apicid_to_node[].
443 */
444 int ht_nodeid = c->initial_apicid;
445
446 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
447 node = __apicid_to_node[ht_nodeid];
448 /* Pick a nearby node */
449 if (!node_online(node))
450 node = nearby_node(apicid);
451 }
452 numa_set_node(cpu, node);
453#endif
454}
455
456static void early_init_amd_mc(struct cpuinfo_x86 *c)
457{
458#ifdef CONFIG_SMP
459 unsigned bits, ecx;
460
461 /* Multi core CPU? */
462 if (c->extended_cpuid_level < 0x80000008)
463 return;
464
465 ecx = cpuid_ecx(0x80000008);
466
467 c->x86_max_cores = (ecx & 0xff) + 1;
468
469 /* CPU telling us the core id bits shift? */
470 bits = (ecx >> 12) & 0xF;
471
472 /* Otherwise recompute */
473 if (bits == 0) {
474 while ((1 << bits) < c->x86_max_cores)
475 bits++;
476 }
477
478 c->x86_coreid_bits = bits;
479#endif
480}
481
482static void bsp_init_amd(struct cpuinfo_x86 *c)
483{
484
485#ifdef CONFIG_X86_64
486 if (c->x86 >= 0xf) {
487 unsigned long long tseg;
488
489 /*
490 * Split up direct mapping around the TSEG SMM area.
491 * Don't do it for gbpages because there seems very little
492 * benefit in doing so.
493 */
494 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
495 unsigned long pfn = tseg >> PAGE_SHIFT;
496
497 pr_debug("tseg: %010llx\n", tseg);
498 if (pfn_range_is_mapped(pfn, pfn + 1))
499 set_memory_4k((unsigned long)__va(tseg), 1);
500 }
501 }
502#endif
503
504 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
505
506 if (c->x86 > 0x10 ||
507 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
508 u64 val;
509
510 rdmsrl(MSR_K7_HWCR, val);
511 if (!(val & BIT(24)))
512 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
513 }
514 }
515
516 if (c->x86 == 0x15) {
517 unsigned long upperbit;
518 u32 cpuid, assoc;
519
520 cpuid = cpuid_edx(0x80000005);
521 assoc = cpuid >> 16 & 0xff;
522 upperbit = ((cpuid >> 24) << 10) / assoc;
523
524 va_align.mask = (upperbit - 1) & PAGE_MASK;
525 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
526
527 /* A random value per boot for bit slice [12:upper_bit) */
528 va_align.bits = get_random_int() & va_align.mask;
529 }
530
531 if (cpu_has(c, X86_FEATURE_MWAITX))
532 use_mwaitx_delay();
533
534 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
535 u32 ecx;
536
537 ecx = cpuid_ecx(0x8000001e);
538 nodes_per_socket = ((ecx >> 8) & 7) + 1;
539 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
540 u64 value;
541
542 rdmsrl(MSR_FAM10H_NODE_ID, value);
543 nodes_per_socket = ((value >> 3) & 7) + 1;
544 }
545}
546
547static void early_init_amd(struct cpuinfo_x86 *c)
548{
549 early_init_amd_mc(c);
550
551 /*
552 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
553 * with P/T states and does not stop in deep C-states
554 */
555 if (c->x86_power & (1 << 8)) {
556 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
557 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
558 if (!check_tsc_unstable())
559 set_sched_clock_stable();
560 }
561
562 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
563 if (c->x86_power & BIT(12))
564 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
565
566#ifdef CONFIG_X86_64
567 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
568#else
569 /* Set MTRR capability flag if appropriate */
570 if (c->x86 == 5)
571 if (c->x86_model == 13 || c->x86_model == 9 ||
572 (c->x86_model == 8 && c->x86_mask >= 8))
573 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
574#endif
575#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
576 /*
577 * ApicID can always be treated as an 8-bit value for AMD APIC versions
578 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
579 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
580 * after 16h.
581 */
582 if (boot_cpu_has(X86_FEATURE_APIC)) {
583 if (c->x86 > 0x16)
584 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
585 else if (c->x86 >= 0xf) {
586 /* check CPU config space for extended APIC ID */
587 unsigned int val;
588
589 val = read_pci_config(0, 24, 0, 0x68);
590 if ((val >> 17 & 0x3) == 0x3)
591 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
592 }
593 }
594#endif
595
596 /*
597 * This is only needed to tell the kernel whether to use VMCALL
598 * and VMMCALL. VMMCALL is never executed except under virt, so
599 * we can set it unconditionally.
600 */
601 set_cpu_cap(c, X86_FEATURE_VMMCALL);
602
603 /* F16h erratum 793, CVE-2013-6885 */
604 if (c->x86 == 0x16 && c->x86_model <= 0xf)
605 msr_set_bit(MSR_AMD64_LS_CFG, 15);
606
607 /*
608 * Check whether the machine is affected by erratum 400. This is
609 * used to select the proper idle routine and to enable the check
610 * whether the machine is affected in arch_post_acpi_init(), which
611 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
612 */
613 if (cpu_has_amd_erratum(c, amd_erratum_400))
614 set_cpu_bug(c, X86_BUG_AMD_E400);
615}
616
617static void init_amd_k8(struct cpuinfo_x86 *c)
618{
619 u32 level;
620 u64 value;
621
622 /* On C+ stepping K8 rep microcode works well for copy/memset */
623 level = cpuid_eax(1);
624 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
625 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
626
627 /*
628 * Some BIOSes incorrectly force this feature, but only K8 revision D
629 * (model = 0x14) and later actually support it.
630 * (AMD Erratum #110, docId: 25759).
631 */
632 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
633 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
634 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
635 value &= ~BIT_64(32);
636 wrmsrl_amd_safe(0xc001100d, value);
637 }
638 }
639
640 if (!c->x86_model_id[0])
641 strcpy(c->x86_model_id, "Hammer");
642
643#ifdef CONFIG_SMP
644 /*
645 * Disable TLB flush filter by setting HWCR.FFDIS on K8
646 * bit 6 of msr C001_0015
647 *
648 * Errata 63 for SH-B3 steppings
649 * Errata 122 for all steppings (F+ have it disabled by default)
650 */
651 msr_set_bit(MSR_K7_HWCR, 6);
652#endif
653 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
654}
655
656static void init_amd_gh(struct cpuinfo_x86 *c)
657{
658#ifdef CONFIG_X86_64
659 /* do this for boot cpu */
660 if (c == &boot_cpu_data)
661 check_enable_amd_mmconf_dmi();
662
663 fam10h_check_enable_mmcfg();
664#endif
665
666 /*
667 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
668 * is always needed when GART is enabled, even in a kernel which has no
669 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
670 * If it doesn't, we do it here as suggested by the BKDG.
671 *
672 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
673 */
674 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
675
676 /*
677 * On family 10h BIOS may not have properly enabled WC+ support, causing
678 * it to be converted to CD memtype. This may result in performance
679 * degradation for certain nested-paging guests. Prevent this conversion
680 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
681 *
682 * NOTE: we want to use the _safe accessors so as not to #GP kvm
683 * guests on older kvm hosts.
684 */
685 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
686
687 if (cpu_has_amd_erratum(c, amd_erratum_383))
688 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
689}
690
691#define MSR_AMD64_DE_CFG 0xC0011029
692
693static void init_amd_ln(struct cpuinfo_x86 *c)
694{
695 /*
696 * Apply erratum 665 fix unconditionally so machines without a BIOS
697 * fix work.
698 */
699 msr_set_bit(MSR_AMD64_DE_CFG, 31);
700}
701
702static void init_amd_bd(struct cpuinfo_x86 *c)
703{
704 u64 value;
705
706 /* re-enable TopologyExtensions if switched off by BIOS */
707 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) &&
708 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
709
710 if (msr_set_bit(0xc0011005, 54) > 0) {
711 rdmsrl(0xc0011005, value);
712 if (value & BIT_64(54)) {
713 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
714 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
715 }
716 }
717 }
718
719 /*
720 * The way access filter has a performance penalty on some workloads.
721 * Disable it on the affected CPUs.
722 */
723 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
724 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
725 value |= 0x1E;
726 wrmsrl_safe(MSR_F15H_IC_CFG, value);
727 }
728 }
729}
730
731static void init_amd(struct cpuinfo_x86 *c)
732{
733 u32 dummy;
734
735 early_init_amd(c);
736
737 /*
738 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
739 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
740 */
741 clear_cpu_cap(c, 0*32+31);
742
743 if (c->x86 >= 0x10)
744 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
745
746 /* get apicid instead of initial apic id from cpuid */
747 c->apicid = hard_smp_processor_id();
748
749 /* K6s reports MCEs but don't actually have all the MSRs */
750 if (c->x86 < 6)
751 clear_cpu_cap(c, X86_FEATURE_MCE);
752
753 switch (c->x86) {
754 case 4: init_amd_k5(c); break;
755 case 5: init_amd_k6(c); break;
756 case 6: init_amd_k7(c); break;
757 case 0xf: init_amd_k8(c); break;
758 case 0x10: init_amd_gh(c); break;
759 case 0x12: init_amd_ln(c); break;
760 case 0x15: init_amd_bd(c); break;
761 }
762
763 /* Enable workaround for FXSAVE leak */
764 if (c->x86 >= 6)
765 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
766
767 cpu_detect_cache_sizes(c);
768
769 /* Multi core CPU? */
770 if (c->extended_cpuid_level >= 0x80000008) {
771 amd_detect_cmp(c);
772 srat_detect_node(c);
773 }
774
775#ifdef CONFIG_X86_32
776 detect_ht(c);
777#endif
778
779 init_amd_cacheinfo(c);
780
781 if (c->x86 >= 0xf)
782 set_cpu_cap(c, X86_FEATURE_K8);
783
784 if (cpu_has(c, X86_FEATURE_XMM2)) {
785 /* MFENCE stops RDTSC speculation */
786 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
787 }
788
789 /*
790 * Family 0x12 and above processors have APIC timer
791 * running in deep C states.
792 */
793 if (c->x86 > 0x11)
794 set_cpu_cap(c, X86_FEATURE_ARAT);
795
796 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
797
798 /* 3DNow or LM implies PREFETCHW */
799 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
800 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
801 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
802
803 /* AMD CPUs don't reset SS attributes on SYSRET */
804 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
805}
806
807#ifdef CONFIG_X86_32
808static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
809{
810 /* AMD errata T13 (order #21922) */
811 if ((c->x86 == 6)) {
812 /* Duron Rev A0 */
813 if (c->x86_model == 3 && c->x86_mask == 0)
814 size = 64;
815 /* Tbird rev A1/A2 */
816 if (c->x86_model == 4 &&
817 (c->x86_mask == 0 || c->x86_mask == 1))
818 size = 256;
819 }
820 return size;
821}
822#endif
823
824static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
825{
826 u32 ebx, eax, ecx, edx;
827 u16 mask = 0xfff;
828
829 if (c->x86 < 0xf)
830 return;
831
832 if (c->extended_cpuid_level < 0x80000006)
833 return;
834
835 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
836
837 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
838 tlb_lli_4k[ENTRIES] = ebx & mask;
839
840 /*
841 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
842 * characteristics from the CPUID function 0x80000005 instead.
843 */
844 if (c->x86 == 0xf) {
845 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
846 mask = 0xff;
847 }
848
849 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
850 if (!((eax >> 16) & mask))
851 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
852 else
853 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
854
855 /* a 4M entry uses two 2M entries */
856 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
857
858 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
859 if (!(eax & mask)) {
860 /* Erratum 658 */
861 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
862 tlb_lli_2m[ENTRIES] = 1024;
863 } else {
864 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
865 tlb_lli_2m[ENTRIES] = eax & 0xff;
866 }
867 } else
868 tlb_lli_2m[ENTRIES] = eax & mask;
869
870 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
871}
872
873static const struct cpu_dev amd_cpu_dev = {
874 .c_vendor = "AMD",
875 .c_ident = { "AuthenticAMD" },
876#ifdef CONFIG_X86_32
877 .legacy_models = {
878 { .family = 4, .model_names =
879 {
880 [3] = "486 DX/2",
881 [7] = "486 DX/2-WB",
882 [8] = "486 DX/4",
883 [9] = "486 DX/4-WB",
884 [14] = "Am5x86-WT",
885 [15] = "Am5x86-WB"
886 }
887 },
888 },
889 .legacy_cache_size = amd_size_cache,
890#endif
891 .c_early_init = early_init_amd,
892 .c_detect_tlb = cpu_detect_tlb_amd,
893 .c_bsp_init = bsp_init_amd,
894 .c_init = init_amd,
895 .c_x86_vendor = X86_VENDOR_AMD,
896};
897
898cpu_dev_register(amd_cpu_dev);
899
900/*
901 * AMD errata checking
902 *
903 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
904 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
905 * have an OSVW id assigned, which it takes as first argument. Both take a
906 * variable number of family-specific model-stepping ranges created by
907 * AMD_MODEL_RANGE().
908 *
909 * Example:
910 *
911 * const int amd_erratum_319[] =
912 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
913 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
914 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
915 */
916
917#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
918#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
919#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
920 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
921#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
922#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
923#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
924
925static const int amd_erratum_400[] =
926 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
927 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
928
929static const int amd_erratum_383[] =
930 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
931
932
933static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
934{
935 int osvw_id = *erratum++;
936 u32 range;
937 u32 ms;
938
939 if (osvw_id >= 0 && osvw_id < 65536 &&
940 cpu_has(cpu, X86_FEATURE_OSVW)) {
941 u64 osvw_len;
942
943 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
944 if (osvw_id < osvw_len) {
945 u64 osvw_bits;
946
947 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
948 osvw_bits);
949 return osvw_bits & (1ULL << (osvw_id & 0x3f));
950 }
951 }
952
953 /* OSVW unavailable or ID unknown, match family-model-stepping range */
954 ms = (cpu->x86_model << 4) | cpu->x86_mask;
955 while ((range = *erratum++))
956 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
957 (ms >= AMD_MODEL_RANGE_START(range)) &&
958 (ms <= AMD_MODEL_RANGE_END(range)))
959 return true;
960
961 return false;
962}
963
964void set_dr_addr_mask(unsigned long mask, int dr)
965{
966 if (!boot_cpu_has(X86_FEATURE_BPEXT))
967 return;
968
969 switch (dr) {
970 case 0:
971 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
972 break;
973 case 1:
974 case 2:
975 case 3:
976 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
977 break;
978 default:
979 break;
980 }
981}