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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier Pro4 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/uniphier-gpio.h>
9
10/ {
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 enable-method = "psci";
24 next-level-cache = <&l2>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <1>;
31 enable-method = "psci";
32 next-level-cache = <&l2>;
33 };
34 };
35
36 psci {
37 compatible = "arm,psci-0.2";
38 method = "smc";
39 };
40
41 clocks {
42 refclk: ref {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
46 };
47
48 arm_timer_clk: arm-timer {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
52 };
53 };
54
55 soc {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60 interrupt-parent = <&intc>;
61
62 l2: l2-cache@500c0000 {
63 compatible = "socionext,uniphier-system-cache";
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
67 cache-unified;
68 cache-size = <(768 * 1024)>;
69 cache-sets = <256>;
70 cache-line-size = <128>;
71 cache-level = <2>;
72 };
73
74 serial0: serial@54006800 {
75 compatible = "socionext,uniphier-uart";
76 status = "disabled";
77 reg = <0x54006800 0x40>;
78 interrupts = <0 33 4>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_uart0>;
81 clocks = <&peri_clk 0>;
82 resets = <&peri_rst 0>;
83 };
84
85 serial1: serial@54006900 {
86 compatible = "socionext,uniphier-uart";
87 status = "disabled";
88 reg = <0x54006900 0x40>;
89 interrupts = <0 35 4>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_uart1>;
92 clocks = <&peri_clk 1>;
93 resets = <&peri_rst 1>;
94 };
95
96 serial2: serial@54006a00 {
97 compatible = "socionext,uniphier-uart";
98 status = "disabled";
99 reg = <0x54006a00 0x40>;
100 interrupts = <0 37 4>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart2>;
103 clocks = <&peri_clk 2>;
104 resets = <&peri_rst 2>;
105 };
106
107 serial3: serial@54006b00 {
108 compatible = "socionext,uniphier-uart";
109 status = "disabled";
110 reg = <0x54006b00 0x40>;
111 interrupts = <0 177 4>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_uart3>;
114 clocks = <&peri_clk 3>;
115 resets = <&peri_rst 3>;
116 };
117
118 gpio: gpio@55000000 {
119 compatible = "socionext,uniphier-gpio";
120 reg = <0x55000000 0x200>;
121 interrupt-parent = <&aidet>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 gpio-ranges = <&pinctrl 0 0 0>;
127 gpio-ranges-group-names = "gpio_range";
128 ngpios = <248>;
129 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
130 };
131
132 i2c0: i2c@58780000 {
133 compatible = "socionext,uniphier-fi2c";
134 status = "disabled";
135 reg = <0x58780000 0x80>;
136 #address-cells = <1>;
137 #size-cells = <0>;
138 interrupts = <0 41 4>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c0>;
141 clocks = <&peri_clk 4>;
142 resets = <&peri_rst 4>;
143 clock-frequency = <100000>;
144 };
145
146 i2c1: i2c@58781000 {
147 compatible = "socionext,uniphier-fi2c";
148 status = "disabled";
149 reg = <0x58781000 0x80>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupts = <0 42 4>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 clocks = <&peri_clk 5>;
156 resets = <&peri_rst 5>;
157 clock-frequency = <100000>;
158 };
159
160 i2c2: i2c@58782000 {
161 compatible = "socionext,uniphier-fi2c";
162 status = "disabled";
163 reg = <0x58782000 0x80>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 interrupts = <0 43 4>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_i2c2>;
169 clocks = <&peri_clk 6>;
170 resets = <&peri_rst 6>;
171 clock-frequency = <100000>;
172 };
173
174 i2c3: i2c@58783000 {
175 compatible = "socionext,uniphier-fi2c";
176 status = "disabled";
177 reg = <0x58783000 0x80>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 interrupts = <0 44 4>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_i2c3>;
183 clocks = <&peri_clk 7>;
184 resets = <&peri_rst 7>;
185 clock-frequency = <100000>;
186 };
187
188 /* i2c4 does not exist */
189
190 /* chip-internal connection for DMD */
191 i2c5: i2c@58785000 {
192 compatible = "socionext,uniphier-fi2c";
193 reg = <0x58785000 0x80>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 interrupts = <0 25 4>;
197 clocks = <&peri_clk 9>;
198 resets = <&peri_rst 9>;
199 clock-frequency = <400000>;
200 };
201
202 /* chip-internal connection for HDMI */
203 i2c6: i2c@58786000 {
204 compatible = "socionext,uniphier-fi2c";
205 reg = <0x58786000 0x80>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 interrupts = <0 26 4>;
209 clocks = <&peri_clk 10>;
210 resets = <&peri_rst 10>;
211 clock-frequency = <400000>;
212 };
213
214 system_bus: system-bus@58c00000 {
215 compatible = "socionext,uniphier-system-bus";
216 status = "disabled";
217 reg = <0x58c00000 0x400>;
218 #address-cells = <2>;
219 #size-cells = <1>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_system_bus>;
222 };
223
224 smpctrl@59801000 {
225 compatible = "socionext,uniphier-smpctrl";
226 reg = <0x59801000 0x400>;
227 };
228
229 mioctrl@59810000 {
230 compatible = "socionext,uniphier-pro4-mioctrl",
231 "simple-mfd", "syscon";
232 reg = <0x59810000 0x800>;
233
234 mio_clk: clock {
235 compatible = "socionext,uniphier-pro4-mio-clock";
236 #clock-cells = <1>;
237 };
238
239 mio_rst: reset {
240 compatible = "socionext,uniphier-pro4-mio-reset";
241 #reset-cells = <1>;
242 };
243 };
244
245 perictrl@59820000 {
246 compatible = "socionext,uniphier-pro4-perictrl",
247 "simple-mfd", "syscon";
248 reg = <0x59820000 0x200>;
249
250 peri_clk: clock {
251 compatible = "socionext,uniphier-pro4-peri-clock";
252 #clock-cells = <1>;
253 };
254
255 peri_rst: reset {
256 compatible = "socionext,uniphier-pro4-peri-reset";
257 #reset-cells = <1>;
258 };
259 };
260
261 usb2: usb@5a800100 {
262 compatible = "socionext,uniphier-ehci", "generic-ehci";
263 status = "disabled";
264 reg = <0x5a800100 0x100>;
265 interrupts = <0 80 4>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_usb2>;
268 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
269 <&mio_clk 12>;
270 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
271 <&mio_rst 12>;
272 has-transaction-translator;
273 };
274
275 usb3: usb@5a810100 {
276 compatible = "socionext,uniphier-ehci", "generic-ehci";
277 status = "disabled";
278 reg = <0x5a810100 0x100>;
279 interrupts = <0 81 4>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_usb3>;
282 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
283 <&mio_clk 13>;
284 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
285 <&mio_rst 13>;
286 has-transaction-translator;
287 };
288
289 soc-glue@5f800000 {
290 compatible = "socionext,uniphier-pro4-soc-glue",
291 "simple-mfd", "syscon";
292 reg = <0x5f800000 0x2000>;
293
294 pinctrl: pinctrl {
295 compatible = "socionext,uniphier-pro4-pinctrl";
296 };
297 };
298
299 soc-glue@5f900000 {
300 compatible = "socionext,uniphier-pro4-soc-glue-debug",
301 "simple-mfd";
302 #address-cells = <1>;
303 #size-cells = <1>;
304 ranges = <0 0x5f900000 0x2000>;
305
306 efuse@100 {
307 compatible = "socionext,uniphier-efuse";
308 reg = <0x100 0x28>;
309 };
310
311 efuse@130 {
312 compatible = "socionext,uniphier-efuse";
313 reg = <0x130 0x8>;
314 };
315
316 efuse@200 {
317 compatible = "socionext,uniphier-efuse";
318 reg = <0x200 0x14>;
319 };
320 };
321
322 aidet: aidet@5fc20000 {
323 compatible = "socionext,uniphier-pro4-aidet";
324 reg = <0x5fc20000 0x200>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 timer@60000200 {
330 compatible = "arm,cortex-a9-global-timer";
331 reg = <0x60000200 0x20>;
332 interrupts = <1 11 0x304>;
333 clocks = <&arm_timer_clk>;
334 };
335
336 timer@60000600 {
337 compatible = "arm,cortex-a9-twd-timer";
338 reg = <0x60000600 0x20>;
339 interrupts = <1 13 0x304>;
340 clocks = <&arm_timer_clk>;
341 };
342
343 intc: interrupt-controller@60001000 {
344 compatible = "arm,cortex-a9-gic";
345 reg = <0x60001000 0x1000>,
346 <0x60000100 0x100>;
347 #interrupt-cells = <3>;
348 interrupt-controller;
349 };
350
351 sysctrl@61840000 {
352 compatible = "socionext,uniphier-pro4-sysctrl",
353 "simple-mfd", "syscon";
354 reg = <0x61840000 0x10000>;
355
356 sys_clk: clock {
357 compatible = "socionext,uniphier-pro4-clock";
358 #clock-cells = <1>;
359 };
360
361 sys_rst: reset {
362 compatible = "socionext,uniphier-pro4-reset";
363 #reset-cells = <1>;
364 };
365 };
366
367 eth: ethernet@65000000 {
368 compatible = "socionext,uniphier-pro4-ave4";
369 status = "disabled";
370 reg = <0x65000000 0x8500>;
371 interrupts = <0 66 4>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_ether_rgmii>;
374 clocks = <&sys_clk 6>;
375 resets = <&sys_rst 6>;
376 phy-mode = "rgmii";
377 local-mac-address = [00 00 00 00 00 00];
378
379 mdio: mdio {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 };
383 };
384
385 nand: nand@68000000 {
386 compatible = "socionext,uniphier-denali-nand-v5a";
387 status = "disabled";
388 reg-names = "nand_data", "denali_reg";
389 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
390 interrupts = <0 65 4>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_nand>;
393 clocks = <&sys_clk 2>;
394 resets = <&sys_rst 2>;
395 };
396 };
397};
398
399#include "uniphier-pinctrl.dtsi"
1/*
2 * Device Tree Source for UniPhier Pro4 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/include/ "skeleton.dtsi"
47
48/ {
49 compatible = "socionext,uniphier-pro4";
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu@0 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a9";
58 reg = <0>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 };
62
63 cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a9";
66 reg = <1>;
67 enable-method = "psci";
68 next-level-cache = <&l2>;
69 };
70 };
71
72 psci {
73 compatible = "arm,psci-0.2";
74 method = "smc";
75 };
76
77 clocks {
78 refclk: ref {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <25000000>;
82 };
83
84 arm_timer_clk: arm_timer_clk {
85 #clock-cells = <0>;
86 compatible = "fixed-clock";
87 clock-frequency = <50000000>;
88 };
89 };
90
91 soc {
92 compatible = "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 interrupt-parent = <&intc>;
97
98 l2: l2-cache@500c0000 {
99 compatible = "socionext,uniphier-system-cache";
100 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
101 <0x506c0000 0x400>;
102 interrupts = <0 174 4>, <0 175 4>;
103 cache-unified;
104 cache-size = <(768 * 1024)>;
105 cache-sets = <256>;
106 cache-line-size = <128>;
107 cache-level = <2>;
108 };
109
110 serial0: serial@54006800 {
111 compatible = "socionext,uniphier-uart";
112 status = "disabled";
113 reg = <0x54006800 0x40>;
114 interrupts = <0 33 4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_uart0>;
117 clocks = <&peri_clk 0>;
118 };
119
120 serial1: serial@54006900 {
121 compatible = "socionext,uniphier-uart";
122 status = "disabled";
123 reg = <0x54006900 0x40>;
124 interrupts = <0 35 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_uart1>;
127 clocks = <&peri_clk 1>;
128 };
129
130 serial2: serial@54006a00 {
131 compatible = "socionext,uniphier-uart";
132 status = "disabled";
133 reg = <0x54006a00 0x40>;
134 interrupts = <0 37 4>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_uart2>;
137 clocks = <&peri_clk 2>;
138 };
139
140 serial3: serial@54006b00 {
141 compatible = "socionext,uniphier-uart";
142 status = "disabled";
143 reg = <0x54006b00 0x40>;
144 interrupts = <0 177 4>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_uart3>;
147 clocks = <&peri_clk 3>;
148 };
149
150 i2c0: i2c@58780000 {
151 compatible = "socionext,uniphier-fi2c";
152 status = "disabled";
153 reg = <0x58780000 0x80>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 interrupts = <0 41 4>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c0>;
159 clocks = <&peri_clk 4>;
160 clock-frequency = <100000>;
161 };
162
163 i2c1: i2c@58781000 {
164 compatible = "socionext,uniphier-fi2c";
165 status = "disabled";
166 reg = <0x58781000 0x80>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 interrupts = <0 42 4>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_i2c1>;
172 clocks = <&peri_clk 5>;
173 clock-frequency = <100000>;
174 };
175
176 i2c2: i2c@58782000 {
177 compatible = "socionext,uniphier-fi2c";
178 status = "disabled";
179 reg = <0x58782000 0x80>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 interrupts = <0 43 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c2>;
185 clocks = <&peri_clk 6>;
186 clock-frequency = <100000>;
187 };
188
189 i2c3: i2c@58783000 {
190 compatible = "socionext,uniphier-fi2c";
191 status = "disabled";
192 reg = <0x58783000 0x80>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 interrupts = <0 44 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
198 clocks = <&peri_clk 7>;
199 clock-frequency = <100000>;
200 };
201
202 /* i2c4 does not exist */
203
204 /* chip-internal connection for DMD */
205 i2c5: i2c@58785000 {
206 compatible = "socionext,uniphier-fi2c";
207 reg = <0x58785000 0x80>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 interrupts = <0 25 4>;
211 clocks = <&peri_clk 9>;
212 clock-frequency = <400000>;
213 };
214
215 /* chip-internal connection for HDMI */
216 i2c6: i2c@58786000 {
217 compatible = "socionext,uniphier-fi2c";
218 reg = <0x58786000 0x80>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 interrupts = <0 26 4>;
222 clocks = <&peri_clk 10>;
223 clock-frequency = <400000>;
224 };
225
226 system_bus: system-bus@58c00000 {
227 compatible = "socionext,uniphier-system-bus";
228 status = "disabled";
229 reg = <0x58c00000 0x400>;
230 #address-cells = <2>;
231 #size-cells = <1>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_system_bus>;
234 };
235
236 smpctrl@59800000 {
237 compatible = "socionext,uniphier-smpctrl";
238 reg = <0x59801000 0x400>;
239 };
240
241 mioctrl@59810000 {
242 compatible = "socionext,uniphier-pro4-mioctrl",
243 "simple-mfd", "syscon";
244 reg = <0x59810000 0x800>;
245
246 mio_clk: clock {
247 compatible = "socionext,uniphier-pro4-mio-clock";
248 #clock-cells = <1>;
249 };
250
251 mio_rst: reset {
252 compatible = "socionext,uniphier-pro4-mio-reset";
253 #reset-cells = <1>;
254 };
255 };
256
257 perictrl@59820000 {
258 compatible = "socionext,uniphier-pro4-perictrl",
259 "simple-mfd", "syscon";
260 reg = <0x59820000 0x200>;
261
262 peri_clk: clock {
263 compatible = "socionext,uniphier-pro4-peri-clock";
264 #clock-cells = <1>;
265 };
266
267 peri_rst: reset {
268 compatible = "socionext,uniphier-pro4-peri-reset";
269 #reset-cells = <1>;
270 };
271 };
272
273 usb2: usb@5a800100 {
274 compatible = "socionext,uniphier-ehci", "generic-ehci";
275 status = "disabled";
276 reg = <0x5a800100 0x100>;
277 interrupts = <0 80 4>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_usb2>;
280 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
281 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
282 <&mio_rst 12>;
283 };
284
285 usb3: usb@5a810100 {
286 compatible = "socionext,uniphier-ehci", "generic-ehci";
287 status = "disabled";
288 reg = <0x5a810100 0x100>;
289 interrupts = <0 81 4>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_usb3>;
292 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
293 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
294 <&mio_rst 13>;
295 };
296
297 soc-glue@5f800000 {
298 compatible = "socionext,uniphier-pro4-soc-glue",
299 "simple-mfd", "syscon";
300 reg = <0x5f800000 0x2000>;
301
302 pinctrl: pinctrl {
303 compatible = "socionext,uniphier-pro4-pinctrl";
304 };
305 };
306
307 timer@60000200 {
308 compatible = "arm,cortex-a9-global-timer";
309 reg = <0x60000200 0x20>;
310 interrupts = <1 11 0x304>;
311 clocks = <&arm_timer_clk>;
312 };
313
314 timer@60000600 {
315 compatible = "arm,cortex-a9-twd-timer";
316 reg = <0x60000600 0x20>;
317 interrupts = <1 13 0x304>;
318 clocks = <&arm_timer_clk>;
319 };
320
321 intc: interrupt-controller@60001000 {
322 compatible = "arm,cortex-a9-gic";
323 reg = <0x60001000 0x1000>,
324 <0x60000100 0x100>;
325 #interrupt-cells = <3>;
326 interrupt-controller;
327 };
328
329 sysctrl@61840000 {
330 compatible = "socionext,uniphier-pro4-sysctrl",
331 "simple-mfd", "syscon";
332 reg = <0x61840000 0x10000>;
333
334 sys_clk: clock {
335 compatible = "socionext,uniphier-pro4-clock";
336 #clock-cells = <1>;
337 };
338
339 sys_rst: reset {
340 compatible = "socionext,uniphier-pro4-reset";
341 #reset-cells = <1>;
342 };
343 };
344 };
345};
346
347/include/ "uniphier-pinctrl.dtsi"