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1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "sun8i-a23-a33.dtsi"
46#include <dt-bindings/thermal/thermal.h>
47
48/ {
49 cpu0_opp_table: opp_table0 {
50 compatible = "operating-points-v2";
51 opp-shared;
52
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
55 opp-microvolt = <1040000>;
56 clock-latency-ns = <244144>; /* 8 32k periods */
57 };
58
59 opp-240000000 {
60 opp-hz = /bits/ 64 <240000000>;
61 opp-microvolt = <1040000>;
62 clock-latency-ns = <244144>; /* 8 32k periods */
63 };
64
65 opp-312000000 {
66 opp-hz = /bits/ 64 <312000000>;
67 opp-microvolt = <1040000>;
68 clock-latency-ns = <244144>; /* 8 32k periods */
69 };
70
71 opp-408000000 {
72 opp-hz = /bits/ 64 <408000000>;
73 opp-microvolt = <1040000>;
74 clock-latency-ns = <244144>; /* 8 32k periods */
75 };
76
77 opp-480000000 {
78 opp-hz = /bits/ 64 <480000000>;
79 opp-microvolt = <1040000>;
80 clock-latency-ns = <244144>; /* 8 32k periods */
81 };
82
83 opp-504000000 {
84 opp-hz = /bits/ 64 <504000000>;
85 opp-microvolt = <1040000>;
86 clock-latency-ns = <244144>; /* 8 32k periods */
87 };
88
89 opp-600000000 {
90 opp-hz = /bits/ 64 <600000000>;
91 opp-microvolt = <1040000>;
92 clock-latency-ns = <244144>; /* 8 32k periods */
93 };
94
95 opp-648000000 {
96 opp-hz = /bits/ 64 <648000000>;
97 opp-microvolt = <1040000>;
98 clock-latency-ns = <244144>; /* 8 32k periods */
99 };
100
101 opp-720000000 {
102 opp-hz = /bits/ 64 <720000000>;
103 opp-microvolt = <1100000>;
104 clock-latency-ns = <244144>; /* 8 32k periods */
105 };
106
107 opp-816000000 {
108 opp-hz = /bits/ 64 <816000000>;
109 opp-microvolt = <1100000>;
110 clock-latency-ns = <244144>; /* 8 32k periods */
111 };
112
113 opp-912000000 {
114 opp-hz = /bits/ 64 <912000000>;
115 opp-microvolt = <1200000>;
116 clock-latency-ns = <244144>; /* 8 32k periods */
117 };
118
119 opp-1008000000 {
120 opp-hz = /bits/ 64 <1008000000>;
121 opp-microvolt = <1200000>;
122 clock-latency-ns = <244144>; /* 8 32k periods */
123 };
124 };
125
126 cpus {
127 cpu@0 {
128 clocks = <&ccu CLK_CPUX>;
129 clock-names = "cpu";
130 operating-points-v2 = <&cpu0_opp_table>;
131 #cooling-cells = <2>;
132 };
133
134 cpu@1 {
135 operating-points-v2 = <&cpu0_opp_table>;
136 };
137
138 cpu@2 {
139 compatible = "arm,cortex-a7";
140 device_type = "cpu";
141 reg = <2>;
142 operating-points-v2 = <&cpu0_opp_table>;
143 };
144
145 cpu@3 {
146 compatible = "arm,cortex-a7";
147 device_type = "cpu";
148 reg = <3>;
149 operating-points-v2 = <&cpu0_opp_table>;
150 };
151 };
152
153 de: display-engine {
154 compatible = "allwinner,sun8i-a33-display-engine";
155 allwinner,pipelines = <&fe0>;
156 status = "disabled";
157 };
158
159 iio-hwmon {
160 compatible = "iio-hwmon";
161 io-channels = <&ths>;
162 };
163
164 mali_opp_table: gpu-opp-table {
165 compatible = "operating-points-v2";
166
167 opp-144000000 {
168 opp-hz = /bits/ 64 <144000000>;
169 };
170
171 opp-240000000 {
172 opp-hz = /bits/ 64 <240000000>;
173 };
174
175 opp-384000000 {
176 opp-hz = /bits/ 64 <384000000>;
177 };
178 };
179
180 memory {
181 reg = <0x40000000 0x80000000>;
182 };
183
184 sound: sound {
185 compatible = "simple-audio-card";
186 simple-audio-card,name = "sun8i-a33-audio";
187 simple-audio-card,format = "i2s";
188 simple-audio-card,frame-master = <&link_codec>;
189 simple-audio-card,bitclock-master = <&link_codec>;
190 simple-audio-card,mclk-fs = <512>;
191 simple-audio-card,aux-devs = <&codec_analog>;
192 simple-audio-card,routing =
193 "Left DAC", "AIF1 Slot 0 Left",
194 "Right DAC", "AIF1 Slot 0 Right";
195 status = "disabled";
196
197 simple-audio-card,cpu {
198 sound-dai = <&dai>;
199 };
200
201 link_codec: simple-audio-card,codec {
202 sound-dai = <&codec>;
203 };
204 };
205
206 soc@1c00000 {
207 tcon0: lcd-controller@1c0c000 {
208 compatible = "allwinner,sun8i-a33-tcon";
209 reg = <0x01c0c000 0x1000>;
210 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&ccu CLK_BUS_LCD>,
212 <&ccu CLK_LCD_CH0>;
213 clock-names = "ahb",
214 "tcon-ch0";
215 clock-output-names = "tcon-pixel-clock";
216 resets = <&ccu RST_BUS_LCD>;
217 reset-names = "lcd";
218 status = "disabled";
219
220 ports {
221 #address-cells = <1>;
222 #size-cells = <0>;
223
224 tcon0_in: port@0 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 reg = <0>;
228
229 tcon0_in_drc0: endpoint@0 {
230 reg = <0>;
231 remote-endpoint = <&drc0_out_tcon0>;
232 };
233 };
234
235 tcon0_out: port@1 {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 reg = <1>;
239 };
240 };
241 };
242
243 crypto: crypto-engine@1c15000 {
244 compatible = "allwinner,sun4i-a10-crypto";
245 reg = <0x01c15000 0x1000>;
246 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
248 clock-names = "ahb", "mod";
249 resets = <&ccu RST_BUS_SS>;
250 reset-names = "ahb";
251 };
252
253 dai: dai@1c22c00 {
254 #sound-dai-cells = <0>;
255 compatible = "allwinner,sun6i-a31-i2s";
256 reg = <0x01c22c00 0x200>;
257 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
259 clock-names = "apb", "mod";
260 resets = <&ccu RST_BUS_CODEC>;
261 dmas = <&dma 15>, <&dma 15>;
262 dma-names = "rx", "tx";
263 status = "disabled";
264 };
265
266 codec: codec@1c22e00 {
267 #sound-dai-cells = <0>;
268 compatible = "allwinner,sun8i-a33-codec";
269 reg = <0x01c22e00 0x400>;
270 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
272 clock-names = "bus", "mod";
273 status = "disabled";
274 };
275
276 ths: ths@1c25000 {
277 compatible = "allwinner,sun8i-a33-ths";
278 reg = <0x01c25000 0x100>;
279 #thermal-sensor-cells = <0>;
280 #io-channel-cells = <0>;
281 };
282
283 fe0: display-frontend@1e00000 {
284 compatible = "allwinner,sun8i-a33-display-frontend";
285 reg = <0x01e00000 0x20000>;
286 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
288 <&ccu CLK_DRAM_DE_FE>;
289 clock-names = "ahb", "mod",
290 "ram";
291 resets = <&ccu RST_BUS_DE_FE>;
292
293 ports {
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 fe0_out: port@1 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 reg = <1>;
301
302 fe0_out_be0: endpoint@0 {
303 reg = <0>;
304 remote-endpoint = <&be0_in_fe0>;
305 };
306 };
307 };
308 };
309
310 be0: display-backend@1e60000 {
311 compatible = "allwinner,sun8i-a33-display-backend";
312 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
313 reg-names = "be", "sat";
314 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
316 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
317 clock-names = "ahb", "mod",
318 "ram", "sat";
319 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
320 reset-names = "be", "sat";
321 assigned-clocks = <&ccu CLK_DE_BE>;
322 assigned-clock-rates = <300000000>;
323
324 ports {
325 #address-cells = <1>;
326 #size-cells = <0>;
327
328 be0_in: port@0 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 reg = <0>;
332
333 be0_in_fe0: endpoint@0 {
334 reg = <0>;
335 remote-endpoint = <&fe0_out_be0>;
336 };
337 };
338
339 be0_out: port@1 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <1>;
343
344 be0_out_drc0: endpoint@0 {
345 reg = <0>;
346 remote-endpoint = <&drc0_in_be0>;
347 };
348 };
349 };
350 };
351
352 drc0: drc@1e70000 {
353 compatible = "allwinner,sun8i-a33-drc";
354 reg = <0x01e70000 0x10000>;
355 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
357 <&ccu CLK_DRAM_DRC>;
358 clock-names = "ahb", "mod", "ram";
359 resets = <&ccu RST_BUS_DRC>;
360
361 assigned-clocks = <&ccu CLK_DRC>;
362 assigned-clock-rates = <300000000>;
363
364 ports {
365 #address-cells = <1>;
366 #size-cells = <0>;
367
368 drc0_in: port@0 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <0>;
372
373 drc0_in_be0: endpoint@0 {
374 reg = <0>;
375 remote-endpoint = <&be0_out_drc0>;
376 };
377 };
378
379 drc0_out: port@1 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 reg = <1>;
383
384 drc0_out_tcon0: endpoint@0 {
385 reg = <0>;
386 remote-endpoint = <&tcon0_in_drc0>;
387 };
388 };
389 };
390 };
391 };
392
393 thermal-zones {
394 cpu_thermal {
395 /* milliseconds */
396 polling-delay-passive = <250>;
397 polling-delay = <1000>;
398 thermal-sensors = <&ths>;
399
400 cooling-maps {
401 map0 {
402 trip = <&cpu_alert0>;
403 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
404 };
405 map1 {
406 trip = <&cpu_alert1>;
407 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
408 };
409
410 map2 {
411 trip = <&gpu_alert0>;
412 cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
413 };
414
415 map3 {
416 trip = <&gpu_alert1>;
417 cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
418 };
419 };
420
421 trips {
422 cpu_alert0: cpu_alert0 {
423 /* milliCelsius */
424 temperature = <75000>;
425 hysteresis = <2000>;
426 type = "passive";
427 };
428
429 gpu_alert0: gpu_alert0 {
430 /* milliCelsius */
431 temperature = <85000>;
432 hysteresis = <2000>;
433 type = "passive";
434 };
435
436 cpu_alert1: cpu_alert1 {
437 /* milliCelsius */
438 temperature = <90000>;
439 hysteresis = <2000>;
440 type = "hot";
441 };
442
443 gpu_alert1: gpu_alert1 {
444 /* milliCelsius */
445 temperature = <95000>;
446 hysteresis = <2000>;
447 type = "hot";
448 };
449
450 cpu_crit: cpu_crit {
451 /* milliCelsius */
452 temperature = <110000>;
453 hysteresis = <2000>;
454 type = "critical";
455 };
456 };
457 };
458 };
459};
460
461&ccu {
462 compatible = "allwinner,sun8i-a33-ccu";
463};
464
465&mali {
466 operating-points-v2 = <&mali_opp_table>;
467};
468
469&pio {
470 compatible = "allwinner,sun8i-a33-pinctrl";
471 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
473
474 uart0_pins_b: uart0@1 {
475 pins = "PB0", "PB1";
476 function = "uart0";
477 };
478
479};
480
481&usb_otg {
482 compatible = "allwinner,sun8i-a33-musb";
483};
484
485&usbphy {
486 compatible = "allwinner,sun8i-a33-usb-phy";
487 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
488 reg-names = "phy_ctrl", "pmu1";
489};
1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "sun8i-a23-a33.dtsi"
46
47/ {
48 cpus {
49 cpu@2 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <2>;
53 };
54
55 cpu@3 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <3>;
59 };
60 };
61
62 de: display-engine {
63 compatible = "allwinner,sun8i-a33-display-engine";
64 allwinner,pipelines = <&fe0>;
65 status = "disabled";
66 };
67
68 memory {
69 reg = <0x40000000 0x80000000>;
70 };
71
72 soc@01c00000 {
73 tcon0: lcd-controller@01c0c000 {
74 compatible = "allwinner,sun8i-a33-tcon";
75 reg = <0x01c0c000 0x1000>;
76 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&ccu CLK_BUS_LCD>,
78 <&ccu CLK_LCD_CH0>;
79 clock-names = "ahb",
80 "tcon-ch0";
81 clock-output-names = "tcon-pixel-clock";
82 resets = <&ccu RST_BUS_LCD>;
83 reset-names = "lcd";
84 status = "disabled";
85
86 ports {
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 tcon0_in: port@0 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 reg = <0>;
94
95 tcon0_in_drc0: endpoint@0 {
96 reg = <0>;
97 remote-endpoint = <&drc0_out_tcon0>;
98 };
99 };
100
101 tcon0_out: port@1 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 reg = <1>;
105 };
106 };
107 };
108
109 crypto: crypto-engine@01c15000 {
110 compatible = "allwinner,sun4i-a10-crypto";
111 reg = <0x01c15000 0x1000>;
112 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
114 clock-names = "ahb", "mod";
115 resets = <&ccu RST_BUS_SS>;
116 reset-names = "ahb";
117 };
118
119 fe0: display-frontend@01e00000 {
120 compatible = "allwinner,sun8i-a33-display-frontend";
121 reg = <0x01e00000 0x20000>;
122 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
124 <&ccu CLK_DRAM_DE_FE>;
125 clock-names = "ahb", "mod",
126 "ram";
127 resets = <&ccu RST_BUS_DE_FE>;
128 status = "disabled";
129
130 ports {
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 fe0_out: port@1 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 reg = <1>;
138
139 fe0_out_be0: endpoint@0 {
140 reg = <0>;
141 remote-endpoint = <&be0_in_fe0>;
142 };
143 };
144 };
145 };
146
147 be0: display-backend@01e60000 {
148 compatible = "allwinner,sun8i-a33-display-backend";
149 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
150 reg-names = "be", "sat";
151 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
153 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
154 clock-names = "ahb", "mod",
155 "ram", "sat";
156 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
157 reset-names = "be", "sat";
158 assigned-clocks = <&ccu CLK_DE_BE>;
159 assigned-clock-rates = <300000000>;
160
161 ports {
162 #address-cells = <1>;
163 #size-cells = <0>;
164
165 be0_in: port@0 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 reg = <0>;
169
170 be0_in_fe0: endpoint@0 {
171 reg = <0>;
172 remote-endpoint = <&fe0_out_be0>;
173 };
174 };
175
176 be0_out: port@1 {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 reg = <1>;
180
181 be0_out_drc0: endpoint@0 {
182 reg = <0>;
183 remote-endpoint = <&drc0_in_be0>;
184 };
185 };
186 };
187 };
188
189 drc0: drc@01e70000 {
190 compatible = "allwinner,sun8i-a33-drc";
191 reg = <0x01e70000 0x10000>;
192 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
194 <&ccu CLK_DRAM_DRC>;
195 clock-names = "ahb", "mod", "ram";
196 resets = <&ccu RST_BUS_DRC>;
197
198 assigned-clocks = <&ccu CLK_DRC>;
199 assigned-clock-rates = <300000000>;
200
201 ports {
202 #address-cells = <1>;
203 #size-cells = <0>;
204
205 drc0_in: port@0 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 reg = <0>;
209
210 drc0_in_be0: endpoint@0 {
211 reg = <0>;
212 remote-endpoint = <&be0_out_drc0>;
213 };
214 };
215
216 drc0_out: port@1 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 reg = <1>;
220
221 drc0_out_tcon0: endpoint@0 {
222 reg = <0>;
223 remote-endpoint = <&tcon0_in_drc0>;
224 };
225 };
226 };
227 };
228 };
229};
230
231&ccu {
232 compatible = "allwinner,sun8i-a33-ccu";
233};
234
235&pio {
236 compatible = "allwinner,sun8i-a33-pinctrl";
237 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
239
240 uart0_pins_b: uart0@1 {
241 allwinner,pins = "PB0", "PB1";
242 allwinner,function = "uart0";
243 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
244 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
245 };
246
247};
248
249&usb_otg {
250 compatible = "allwinner,sun8i-a33-musb";
251};
252
253&usbphy {
254 compatible = "allwinner,sun8i-a33-usb-phy";
255 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
256 reg-names = "phy_ctrl", "pmu1";
257};