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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell Armada XP development board
4 * (DB-MV784MP-GP)
5 *
6 * Copyright (C) 2013-2014 Marvell
7 *
8 * Lior Amsalem <alior@marvell.com>
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 *
12 * Note: this Device Tree assumes that the bootloader has remapped the
13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
16 * boards were delivered with an older version of the bootloader that
17 * left internal registers mapped at 0xd0000000. If you are in this
18 * situation, you should either update your bootloader (preferred
19 * solution) or the below Device Tree should be adjusted.
20 */
21
22/dts-v1/;
23#include <dt-bindings/gpio/gpio.h>
24#include "armada-xp-mv78460.dtsi"
25
26/ {
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
28 compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
29
30 chosen {
31 stdout-path = "serial0:115200n8";
32 };
33
34 memory@0 {
35 device_type = "memory";
36 /*
37 * 8 GB of plug-in RAM modules by default.The amount
38 * of memory available can be changed by the
39 * bootloader according the size of the module
40 * actually plugged. However, memory between
41 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
42 * the address range used for I/O (internal registers,
43 * MBus windows).
44 */
45 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
46 <0x00000001 0x00000000 0x00000001 0x00000000>;
47 };
48
49 cpus {
50 pm_pic {
51 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
52 <&gpio0 17 GPIO_ACTIVE_LOW>,
53 <&gpio0 18 GPIO_ACTIVE_LOW>;
54 };
55 };
56
57 soc {
58 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
59 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
60 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
61 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
62 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
63 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64
65 devbus-bootcs {
66 status = "okay";
67
68 /* Device Bus parameters are required */
69
70 /* Read parameters */
71 devbus,bus-width = <16>;
72 devbus,turn-off-ps = <60000>;
73 devbus,badr-skew-ps = <0>;
74 devbus,acc-first-ps = <124000>;
75 devbus,acc-next-ps = <248000>;
76 devbus,rd-setup-ps = <0>;
77 devbus,rd-hold-ps = <0>;
78
79 /* Write parameters */
80 devbus,sync-enable = <0>;
81 devbus,wr-high-ps = <60000>;
82 devbus,wr-low-ps = <60000>;
83 devbus,ale-wr-ps = <60000>;
84
85 /* NOR 16 MiB */
86 nor@0 {
87 compatible = "cfi-flash";
88 reg = <0 0x1000000>;
89 bank-width = <2>;
90 };
91 };
92
93 internal-regs {
94 serial@12000 {
95 status = "okay";
96 };
97 serial@12100 {
98 status = "okay";
99 };
100 serial@12200 {
101 status = "okay";
102 };
103 serial@12300 {
104 status = "okay";
105 };
106 pinctrl {
107 pinctrl-0 = <&pic_pins>;
108 pinctrl-names = "default";
109 pic_pins: pic-pins-0 {
110 marvell,pins = "mpp16", "mpp17",
111 "mpp18";
112 marvell,function = "gpio";
113 };
114 };
115 sata@a0000 {
116 nr-ports = <2>;
117 status = "okay";
118 };
119
120 ethernet@70000 {
121 status = "okay";
122 phy = <&phy0>;
123 phy-mode = "qsgmii";
124 buffer-manager = <&bm>;
125 bm,pool-long = <0>;
126 };
127 ethernet@74000 {
128 status = "okay";
129 phy = <&phy1>;
130 phy-mode = "qsgmii";
131 buffer-manager = <&bm>;
132 bm,pool-long = <1>;
133 };
134 ethernet@30000 {
135 status = "okay";
136 phy = <&phy2>;
137 phy-mode = "qsgmii";
138 buffer-manager = <&bm>;
139 bm,pool-long = <2>;
140 };
141 ethernet@34000 {
142 status = "okay";
143 phy = <&phy3>;
144 phy-mode = "qsgmii";
145 buffer-manager = <&bm>;
146 bm,pool-long = <3>;
147 };
148
149 /* Front-side USB slot */
150 usb@50000 {
151 status = "okay";
152 };
153
154 /* Back-side USB slot */
155 usb@51000 {
156 status = "okay";
157 };
158
159 bm@c0000 {
160 status = "okay";
161 };
162
163 nand@d0000 {
164 status = "okay";
165 num-cs = <1>;
166 marvell,nand-keep-config;
167 marvell,nand-enable-arbiter;
168 nand-on-flash-bbt;
169 };
170 };
171
172 bm-bppi {
173 status = "okay";
174 };
175 };
176};
177
178&pciec {
179 status = "okay";
180
181 /*
182 * The 3 slots are physically present as
183 * standard PCIe slots on the board.
184 */
185 pcie@1,0 {
186 /* Port 0, Lane 0 */
187 status = "okay";
188 };
189 pcie@9,0 {
190 /* Port 2, Lane 0 */
191 status = "okay";
192 };
193 pcie@a,0 {
194 /* Port 3, Lane 0 */
195 status = "okay";
196 };
197};
198
199&mdio {
200 phy0: ethernet-phy@0 {
201 reg = <16>;
202 };
203
204 phy1: ethernet-phy@1 {
205 reg = <17>;
206 };
207
208 phy2: ethernet-phy@2 {
209 reg = <18>;
210 };
211
212 phy3: ethernet-phy@3 {
213 reg = <19>;
214 };
215};
216
217&spi0 {
218 status = "okay";
219
220 spi-flash@0 {
221 #address-cells = <1>;
222 #size-cells = <1>;
223 compatible = "n25q128a13", "jedec,spi-nor";
224 reg = <0>; /* Chip select 0 */
225 spi-max-frequency = <108000000>;
226 };
227};
1/*
2 * Device Tree file for Marvell Armada XP development board
3 * (DB-MV784MP-GP)
4 *
5 * Copyright (C) 2013-2014 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of the
19 * License, or (at your option) any later version.
20 *
21 * This file is distributed in the hope that it will be useful
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * Or, alternatively
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * Note: this Device Tree assumes that the bootloader has remapped the
50 * internal registers to 0xf1000000 (instead of the default
51 * 0xd0000000). The 0xf1000000 is the default used by the recent,
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
53 * boards were delivered with an older version of the bootloader that
54 * left internal registers mapped at 0xd0000000. If you are in this
55 * situation, you should either update your bootloader (preferred
56 * solution) or the below Device Tree should be adjusted.
57 */
58
59/dts-v1/;
60#include <dt-bindings/gpio/gpio.h>
61#include "armada-xp-mv78460.dtsi"
62
63/ {
64 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
65 compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
66
67 chosen {
68 stdout-path = "serial0:115200n8";
69 };
70
71 memory@0 {
72 device_type = "memory";
73 /*
74 * 8 GB of plug-in RAM modules by default.The amount
75 * of memory available can be changed by the
76 * bootloader according the size of the module
77 * actually plugged. However, memory between
78 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
79 * the address range used for I/O (internal registers,
80 * MBus windows).
81 */
82 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
83 <0x00000001 0x00000000 0x00000001 0x00000000>;
84 };
85
86 cpus {
87 pm_pic {
88 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
89 <&gpio0 17 GPIO_ACTIVE_LOW>,
90 <&gpio0 18 GPIO_ACTIVE_LOW>;
91 };
92 };
93
94 soc {
95 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
96 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
97 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
98 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
99 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
100 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
101
102 devbus-bootcs {
103 status = "okay";
104
105 /* Device Bus parameters are required */
106
107 /* Read parameters */
108 devbus,bus-width = <16>;
109 devbus,turn-off-ps = <60000>;
110 devbus,badr-skew-ps = <0>;
111 devbus,acc-first-ps = <124000>;
112 devbus,acc-next-ps = <248000>;
113 devbus,rd-setup-ps = <0>;
114 devbus,rd-hold-ps = <0>;
115
116 /* Write parameters */
117 devbus,sync-enable = <0>;
118 devbus,wr-high-ps = <60000>;
119 devbus,wr-low-ps = <60000>;
120 devbus,ale-wr-ps = <60000>;
121
122 /* NOR 16 MiB */
123 nor@0 {
124 compatible = "cfi-flash";
125 reg = <0 0x1000000>;
126 bank-width = <2>;
127 };
128 };
129
130 internal-regs {
131 serial@12000 {
132 status = "okay";
133 };
134 serial@12100 {
135 status = "okay";
136 };
137 serial@12200 {
138 status = "okay";
139 };
140 serial@12300 {
141 status = "okay";
142 };
143 pinctrl {
144 pinctrl-0 = <&pic_pins>;
145 pinctrl-names = "default";
146 pic_pins: pic-pins-0 {
147 marvell,pins = "mpp16", "mpp17",
148 "mpp18";
149 marvell,function = "gpio";
150 };
151 };
152 sata@a0000 {
153 nr-ports = <2>;
154 status = "okay";
155 };
156
157 ethernet@70000 {
158 status = "okay";
159 phy = <&phy0>;
160 phy-mode = "qsgmii";
161 buffer-manager = <&bm>;
162 bm,pool-long = <0>;
163 };
164 ethernet@74000 {
165 status = "okay";
166 phy = <&phy1>;
167 phy-mode = "qsgmii";
168 buffer-manager = <&bm>;
169 bm,pool-long = <1>;
170 };
171 ethernet@30000 {
172 status = "okay";
173 phy = <&phy2>;
174 phy-mode = "qsgmii";
175 buffer-manager = <&bm>;
176 bm,pool-long = <2>;
177 };
178 ethernet@34000 {
179 status = "okay";
180 phy = <&phy3>;
181 phy-mode = "qsgmii";
182 buffer-manager = <&bm>;
183 bm,pool-long = <3>;
184 };
185
186 /* Front-side USB slot */
187 usb@50000 {
188 status = "okay";
189 };
190
191 /* Back-side USB slot */
192 usb@51000 {
193 status = "okay";
194 };
195
196 bm@c0000 {
197 status = "okay";
198 };
199
200 nand@d0000 {
201 status = "okay";
202 num-cs = <1>;
203 marvell,nand-keep-config;
204 marvell,nand-enable-arbiter;
205 nand-on-flash-bbt;
206 };
207 };
208
209 bm-bppi {
210 status = "okay";
211 };
212 };
213};
214
215&pciec {
216 status = "okay";
217
218 /*
219 * The 3 slots are physically present as
220 * standard PCIe slots on the board.
221 */
222 pcie@1,0 {
223 /* Port 0, Lane 0 */
224 status = "okay";
225 };
226 pcie@9,0 {
227 /* Port 2, Lane 0 */
228 status = "okay";
229 };
230 pcie@10,0 {
231 /* Port 3, Lane 0 */
232 status = "okay";
233 };
234};
235
236&mdio {
237 phy0: ethernet-phy@0 {
238 reg = <16>;
239 };
240
241 phy1: ethernet-phy@1 {
242 reg = <17>;
243 };
244
245 phy2: ethernet-phy@2 {
246 reg = <18>;
247 };
248
249 phy3: ethernet-phy@3 {
250 reg = <19>;
251 };
252};
253
254&spi0 {
255 status = "okay";
256
257 spi-flash@0 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 compatible = "n25q128a13", "jedec,spi-nor";
261 reg = <0>; /* Chip select 0 */
262 spi-max-frequency = <108000000>;
263 };
264};