Loading...
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * dwc3-omap.c - OMAP Specific Glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/irq.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/platform_data/dwc3-omap.h>
18#include <linux/pm_runtime.h>
19#include <linux/dma-mapping.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/of_platform.h>
24#include <linux/extcon.h>
25#include <linux/regulator/consumer.h>
26
27#include <linux/usb/otg.h>
28
29/*
30 * All these registers belong to OMAP's Wrapper around the
31 * DesignWare USB3 Core.
32 */
33
34#define USBOTGSS_REVISION 0x0000
35#define USBOTGSS_SYSCONFIG 0x0010
36#define USBOTGSS_IRQ_EOI 0x0020
37#define USBOTGSS_EOI_OFFSET 0x0008
38#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
39#define USBOTGSS_IRQSTATUS_0 0x0028
40#define USBOTGSS_IRQENABLE_SET_0 0x002c
41#define USBOTGSS_IRQENABLE_CLR_0 0x0030
42#define USBOTGSS_IRQ0_OFFSET 0x0004
43#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
44#define USBOTGSS_IRQSTATUS_1 0x0034
45#define USBOTGSS_IRQENABLE_SET_1 0x0038
46#define USBOTGSS_IRQENABLE_CLR_1 0x003c
47#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
48#define USBOTGSS_IRQSTATUS_2 0x0044
49#define USBOTGSS_IRQENABLE_SET_2 0x0048
50#define USBOTGSS_IRQENABLE_CLR_2 0x004c
51#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
52#define USBOTGSS_IRQSTATUS_3 0x0054
53#define USBOTGSS_IRQENABLE_SET_3 0x0058
54#define USBOTGSS_IRQENABLE_CLR_3 0x005c
55#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
56#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
57#define USBOTGSS_IRQSTATUS_MISC 0x0038
58#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
59#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
60#define USBOTGSS_IRQMISC_OFFSET 0x03fc
61#define USBOTGSS_UTMI_OTG_STATUS 0x0080
62#define USBOTGSS_UTMI_OTG_CTRL 0x0084
63#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
64#define USBOTGSS_TXFIFO_DEPTH 0x0508
65#define USBOTGSS_RXFIFO_DEPTH 0x050c
66#define USBOTGSS_MMRAM_OFFSET 0x0100
67#define USBOTGSS_FLADJ 0x0104
68#define USBOTGSS_DEBUG_CFG 0x0108
69#define USBOTGSS_DEBUG_DATA 0x010c
70#define USBOTGSS_DEV_EBC_EN 0x0110
71#define USBOTGSS_DEBUG_OFFSET 0x0600
72
73/* SYSCONFIG REGISTER */
74#define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16)
75
76/* IRQ_EOI REGISTER */
77#define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0)
78
79/* IRQS0 BITS */
80#define USBOTGSS_IRQO_COREIRQ_ST BIT(0)
81
82/* IRQMISC BITS */
83#define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17)
84#define USBOTGSS_IRQMISC_OEVT BIT(16)
85#define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13)
86#define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12)
87#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11)
88#define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8)
89#define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5)
90#define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4)
91#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3)
92#define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0)
93
94/* UTMI_OTG_STATUS REGISTER */
95#define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5)
96#define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4)
97#define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3)
98#define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0)
99
100/* UTMI_OTG_CTRL REGISTER */
101#define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31)
102#define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9)
103#define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8)
104#define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4)
105#define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3)
106#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2)
107#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1)
108
109struct dwc3_omap {
110 struct device *dev;
111
112 int irq;
113 void __iomem *base;
114
115 u32 utmi_otg_ctrl;
116 u32 utmi_otg_offset;
117 u32 irqmisc_offset;
118 u32 irq_eoi_offset;
119 u32 debug_offset;
120 u32 irq0_offset;
121
122 struct extcon_dev *edev;
123 struct notifier_block vbus_nb;
124 struct notifier_block id_nb;
125
126 struct regulator *vbus_reg;
127};
128
129enum omap_dwc3_vbus_id_status {
130 OMAP_DWC3_ID_FLOAT,
131 OMAP_DWC3_ID_GROUND,
132 OMAP_DWC3_VBUS_OFF,
133 OMAP_DWC3_VBUS_VALID,
134};
135
136static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
137{
138 return readl(base + offset);
139}
140
141static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
142{
143 writel(value, base + offset);
144}
145
146static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
147{
148 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
149 omap->utmi_otg_offset);
150}
151
152static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
153{
154 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
155 omap->utmi_otg_offset, value);
156
157}
158
159static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
160{
161 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
162 omap->irq0_offset);
163}
164
165static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
166{
167 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
168 omap->irq0_offset, value);
169
170}
171
172static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
173{
174 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
175 omap->irqmisc_offset);
176}
177
178static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
179{
180 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
181 omap->irqmisc_offset, value);
182
183}
184
185static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
186{
187 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
188 omap->irqmisc_offset, value);
189
190}
191
192static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
193{
194 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
195 omap->irq0_offset, value);
196}
197
198static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
199{
200 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
201 omap->irqmisc_offset, value);
202}
203
204static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
205{
206 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
207 omap->irq0_offset, value);
208}
209
210static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
211 enum omap_dwc3_vbus_id_status status)
212{
213 int ret;
214 u32 val;
215
216 switch (status) {
217 case OMAP_DWC3_ID_GROUND:
218 if (omap->vbus_reg) {
219 ret = regulator_enable(omap->vbus_reg);
220 if (ret) {
221 dev_err(omap->dev, "regulator enable failed\n");
222 return;
223 }
224 }
225
226 val = dwc3_omap_read_utmi_ctrl(omap);
227 val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
228 dwc3_omap_write_utmi_ctrl(omap, val);
229 break;
230
231 case OMAP_DWC3_VBUS_VALID:
232 val = dwc3_omap_read_utmi_ctrl(omap);
233 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
234 val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
235 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
236 dwc3_omap_write_utmi_ctrl(omap, val);
237 break;
238
239 case OMAP_DWC3_ID_FLOAT:
240 if (omap->vbus_reg)
241 regulator_disable(omap->vbus_reg);
242 val = dwc3_omap_read_utmi_ctrl(omap);
243 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
244 dwc3_omap_write_utmi_ctrl(omap, val);
245 break;
246
247 case OMAP_DWC3_VBUS_OFF:
248 val = dwc3_omap_read_utmi_ctrl(omap);
249 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
250 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
251 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
252 dwc3_omap_write_utmi_ctrl(omap, val);
253 break;
254
255 default:
256 dev_WARN(omap->dev, "invalid state\n");
257 }
258}
259
260static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
261static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
262
263static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
264{
265 struct dwc3_omap *omap = _omap;
266
267 if (dwc3_omap_read_irqmisc_status(omap) ||
268 dwc3_omap_read_irq0_status(omap)) {
269 /* mask irqs */
270 dwc3_omap_disable_irqs(omap);
271 return IRQ_WAKE_THREAD;
272 }
273
274 return IRQ_NONE;
275}
276
277static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
278{
279 struct dwc3_omap *omap = _omap;
280 u32 reg;
281
282 /* clear irq status flags */
283 reg = dwc3_omap_read_irqmisc_status(omap);
284 dwc3_omap_write_irqmisc_status(omap, reg);
285
286 reg = dwc3_omap_read_irq0_status(omap);
287 dwc3_omap_write_irq0_status(omap, reg);
288
289 /* unmask irqs */
290 dwc3_omap_enable_irqs(omap);
291
292 return IRQ_HANDLED;
293}
294
295static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
296{
297 u32 reg;
298
299 /* enable all IRQs */
300 reg = USBOTGSS_IRQO_COREIRQ_ST;
301 dwc3_omap_write_irq0_set(omap, reg);
302
303 reg = (USBOTGSS_IRQMISC_OEVT |
304 USBOTGSS_IRQMISC_DRVVBUS_RISE |
305 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
306 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
307 USBOTGSS_IRQMISC_IDPULLUP_RISE |
308 USBOTGSS_IRQMISC_DRVVBUS_FALL |
309 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
310 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
311 USBOTGSS_IRQMISC_IDPULLUP_FALL);
312
313 dwc3_omap_write_irqmisc_set(omap, reg);
314}
315
316static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
317{
318 u32 reg;
319
320 /* disable all IRQs */
321 reg = USBOTGSS_IRQO_COREIRQ_ST;
322 dwc3_omap_write_irq0_clr(omap, reg);
323
324 reg = (USBOTGSS_IRQMISC_OEVT |
325 USBOTGSS_IRQMISC_DRVVBUS_RISE |
326 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
327 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
328 USBOTGSS_IRQMISC_IDPULLUP_RISE |
329 USBOTGSS_IRQMISC_DRVVBUS_FALL |
330 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
331 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
332 USBOTGSS_IRQMISC_IDPULLUP_FALL);
333
334 dwc3_omap_write_irqmisc_clr(omap, reg);
335}
336
337static int dwc3_omap_id_notifier(struct notifier_block *nb,
338 unsigned long event, void *ptr)
339{
340 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
341
342 if (event)
343 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
344 else
345 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
346
347 return NOTIFY_DONE;
348}
349
350static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
351 unsigned long event, void *ptr)
352{
353 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
354
355 if (event)
356 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
357 else
358 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
359
360 return NOTIFY_DONE;
361}
362
363static void dwc3_omap_map_offset(struct dwc3_omap *omap)
364{
365 struct device_node *node = omap->dev->of_node;
366
367 /*
368 * Differentiate between OMAP5 and AM437x.
369 *
370 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
371 * though there are changes in wrapper register offsets.
372 *
373 * Using dt compatible to differentiate AM437x.
374 */
375 if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
376 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
377 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
378 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
379 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
380 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
381 }
382}
383
384static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
385{
386 u32 reg;
387 struct device_node *node = omap->dev->of_node;
388 u32 utmi_mode = 0;
389
390 reg = dwc3_omap_read_utmi_ctrl(omap);
391
392 of_property_read_u32(node, "utmi-mode", &utmi_mode);
393
394 switch (utmi_mode) {
395 case DWC3_OMAP_UTMI_MODE_SW:
396 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
397 break;
398 case DWC3_OMAP_UTMI_MODE_HW:
399 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
400 break;
401 default:
402 dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
403 }
404
405 dwc3_omap_write_utmi_ctrl(omap, reg);
406}
407
408static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
409{
410 int ret;
411 struct device_node *node = omap->dev->of_node;
412 struct extcon_dev *edev;
413
414 if (of_property_read_bool(node, "extcon")) {
415 edev = extcon_get_edev_by_phandle(omap->dev, 0);
416 if (IS_ERR(edev)) {
417 dev_vdbg(omap->dev, "couldn't get extcon device\n");
418 return -EPROBE_DEFER;
419 }
420
421 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
422 ret = devm_extcon_register_notifier(omap->dev, edev,
423 EXTCON_USB, &omap->vbus_nb);
424 if (ret < 0)
425 dev_vdbg(omap->dev, "failed to register notifier for USB\n");
426
427 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
428 ret = devm_extcon_register_notifier(omap->dev, edev,
429 EXTCON_USB_HOST, &omap->id_nb);
430 if (ret < 0)
431 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
432
433 if (extcon_get_state(edev, EXTCON_USB) == true)
434 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
435 if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
436 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
437
438 omap->edev = edev;
439 }
440
441 return 0;
442}
443
444static int dwc3_omap_probe(struct platform_device *pdev)
445{
446 struct device_node *node = pdev->dev.of_node;
447
448 struct dwc3_omap *omap;
449 struct resource *res;
450 struct device *dev = &pdev->dev;
451 struct regulator *vbus_reg = NULL;
452
453 int ret;
454 int irq;
455
456 u32 reg;
457
458 void __iomem *base;
459
460 if (!node) {
461 dev_err(dev, "device node not found\n");
462 return -EINVAL;
463 }
464
465 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
466 if (!omap)
467 return -ENOMEM;
468
469 platform_set_drvdata(pdev, omap);
470
471 irq = platform_get_irq(pdev, 0);
472 if (irq < 0) {
473 dev_err(dev, "missing IRQ resource: %d\n", irq);
474 return irq;
475 }
476
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 base = devm_ioremap_resource(dev, res);
479 if (IS_ERR(base))
480 return PTR_ERR(base);
481
482 if (of_property_read_bool(node, "vbus-supply")) {
483 vbus_reg = devm_regulator_get(dev, "vbus");
484 if (IS_ERR(vbus_reg)) {
485 dev_err(dev, "vbus init failed\n");
486 return PTR_ERR(vbus_reg);
487 }
488 }
489
490 omap->dev = dev;
491 omap->irq = irq;
492 omap->base = base;
493 omap->vbus_reg = vbus_reg;
494
495 pm_runtime_enable(dev);
496 ret = pm_runtime_get_sync(dev);
497 if (ret < 0) {
498 dev_err(dev, "get_sync failed with err %d\n", ret);
499 goto err1;
500 }
501
502 dwc3_omap_map_offset(omap);
503 dwc3_omap_set_utmi_mode(omap);
504
505 /* check the DMA Status */
506 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
507
508 ret = dwc3_omap_extcon_register(omap);
509 if (ret < 0)
510 goto err1;
511
512 ret = of_platform_populate(node, NULL, NULL, dev);
513 if (ret) {
514 dev_err(&pdev->dev, "failed to create dwc3 core\n");
515 goto err1;
516 }
517
518 ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
519 dwc3_omap_interrupt_thread, IRQF_SHARED,
520 "dwc3-omap", omap);
521 if (ret) {
522 dev_err(dev, "failed to request IRQ #%d --> %d\n",
523 omap->irq, ret);
524 goto err1;
525 }
526 dwc3_omap_enable_irqs(omap);
527 return 0;
528
529err1:
530 pm_runtime_put_sync(dev);
531 pm_runtime_disable(dev);
532
533 return ret;
534}
535
536static int dwc3_omap_remove(struct platform_device *pdev)
537{
538 struct dwc3_omap *omap = platform_get_drvdata(pdev);
539
540 dwc3_omap_disable_irqs(omap);
541 disable_irq(omap->irq);
542 of_platform_depopulate(omap->dev);
543 pm_runtime_put_sync(&pdev->dev);
544 pm_runtime_disable(&pdev->dev);
545
546 return 0;
547}
548
549static const struct of_device_id of_dwc3_match[] = {
550 {
551 .compatible = "ti,dwc3"
552 },
553 {
554 .compatible = "ti,am437x-dwc3"
555 },
556 { },
557};
558MODULE_DEVICE_TABLE(of, of_dwc3_match);
559
560#ifdef CONFIG_PM_SLEEP
561static int dwc3_omap_suspend(struct device *dev)
562{
563 struct dwc3_omap *omap = dev_get_drvdata(dev);
564
565 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
566 dwc3_omap_disable_irqs(omap);
567
568 return 0;
569}
570
571static int dwc3_omap_resume(struct device *dev)
572{
573 struct dwc3_omap *omap = dev_get_drvdata(dev);
574
575 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
576 dwc3_omap_enable_irqs(omap);
577
578 pm_runtime_disable(dev);
579 pm_runtime_set_active(dev);
580 pm_runtime_enable(dev);
581
582 return 0;
583}
584
585static void dwc3_omap_complete(struct device *dev)
586{
587 struct dwc3_omap *omap = dev_get_drvdata(dev);
588
589 if (extcon_get_state(omap->edev, EXTCON_USB))
590 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
591 else
592 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
593
594 if (extcon_get_state(omap->edev, EXTCON_USB_HOST))
595 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
596 else
597 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
598}
599
600static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
601
602 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
603 .complete = dwc3_omap_complete,
604};
605
606#define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
607#else
608#define DEV_PM_OPS NULL
609#endif /* CONFIG_PM_SLEEP */
610
611static struct platform_driver dwc3_omap_driver = {
612 .probe = dwc3_omap_probe,
613 .remove = dwc3_omap_remove,
614 .driver = {
615 .name = "omap-dwc3",
616 .of_match_table = of_dwc3_match,
617 .pm = DEV_PM_OPS,
618 },
619};
620
621module_platform_driver(dwc3_omap_driver);
622
623MODULE_ALIAS("platform:omap-dwc3");
624MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
625MODULE_LICENSE("GPL v2");
626MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
1/**
2 * dwc3-omap.c - OMAP Specific Glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/interrupt.h>
43#include <linux/spinlock.h>
44#include <linux/platform_device.h>
45#include <linux/platform_data/dwc3-omap.h>
46#include <linux/dma-mapping.h>
47#include <linux/ioport.h>
48#include <linux/io.h>
49#include <linux/of.h>
50
51#include "core.h"
52
53/*
54 * All these registers belong to OMAP's Wrapper around the
55 * DesignWare USB3 Core.
56 */
57
58#define USBOTGSS_REVISION 0x0000
59#define USBOTGSS_SYSCONFIG 0x0010
60#define USBOTGSS_IRQ_EOI 0x0020
61#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
62#define USBOTGSS_IRQSTATUS_0 0x0028
63#define USBOTGSS_IRQENABLE_SET_0 0x002c
64#define USBOTGSS_IRQENABLE_CLR_0 0x0030
65#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
66#define USBOTGSS_IRQSTATUS_1 0x0038
67#define USBOTGSS_IRQENABLE_SET_1 0x003c
68#define USBOTGSS_IRQENABLE_CLR_1 0x0040
69#define USBOTGSS_UTMI_OTG_CTRL 0x0080
70#define USBOTGSS_UTMI_OTG_STATUS 0x0084
71#define USBOTGSS_MMRAM_OFFSET 0x0100
72#define USBOTGSS_FLADJ 0x0104
73#define USBOTGSS_DEBUG_CFG 0x0108
74#define USBOTGSS_DEBUG_DATA 0x010c
75
76/* SYSCONFIG REGISTER */
77#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
78#define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
79
80#define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0
81#define USBOTGSS_STANDBYMODE_NO_STANDBY 1
82#define USBOTGSS_STANDBYMODE_SMART_STANDBY 2
83#define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3
84
85#define USBOTGSS_STANDBYMODE_MASK (0x03 << 4)
86
87#define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
88
89#define USBOTGSS_IDLEMODE_FORCE_IDLE 0
90#define USBOTGSS_IDLEMODE_NO_IDLE 1
91#define USBOTGSS_IDLEMODE_SMART_IDLE 2
92#define USBOTGSS_IDLEMODE_SMART_WAKEUP 3
93
94#define USBOTGSS_IDLEMODE_MASK (0x03 << 2)
95
96/* IRQ_EOI REGISTER */
97#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
98
99/* IRQS0 BITS */
100#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
101
102/* IRQ1 BITS */
103#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
104#define USBOTGSS_IRQ1_OEVT (1 << 16)
105#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
106#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
107#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
108#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
109#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
110#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
111#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
112#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
113
114/* UTMI_OTG_CTRL REGISTER */
115#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
116#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
117#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
118#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
119
120/* UTMI_OTG_STATUS REGISTER */
121#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
122#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
123#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
124#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
125#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
126#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
127#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
128
129struct dwc3_omap {
130 /* device lock */
131 spinlock_t lock;
132
133 struct platform_device *dwc3;
134 struct device *dev;
135
136 int irq;
137 void __iomem *base;
138
139 void *context;
140 u32 resource_size;
141
142 u32 dma_status:1;
143};
144
145static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
146{
147 return readl(base + offset);
148}
149
150static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
151{
152 writel(value, base + offset);
153}
154
155
156static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
157{
158 struct dwc3_omap *omap = _omap;
159 u32 reg;
160
161 spin_lock(&omap->lock);
162
163 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
164
165 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
166 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
167 omap->dma_status = false;
168 }
169
170 if (reg & USBOTGSS_IRQ1_OEVT)
171 dev_dbg(omap->dev, "OTG Event\n");
172
173 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
174 dev_dbg(omap->dev, "DRVVBUS Rise\n");
175
176 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
177 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
178
179 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
180 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
181
182 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
183 dev_dbg(omap->dev, "IDPULLUP Rise\n");
184
185 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
186 dev_dbg(omap->dev, "DRVVBUS Fall\n");
187
188 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
189 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
190
191 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
192 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
193
194 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
195 dev_dbg(omap->dev, "IDPULLUP Fall\n");
196
197 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
198
199 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
200 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
201
202 spin_unlock(&omap->lock);
203
204 return IRQ_HANDLED;
205}
206
207static int __devinit dwc3_omap_probe(struct platform_device *pdev)
208{
209 struct dwc3_omap_data *pdata = pdev->dev.platform_data;
210 struct device_node *node = pdev->dev.of_node;
211
212 struct platform_device *dwc3;
213 struct dwc3_omap *omap;
214 struct resource *res;
215 struct device *dev = &pdev->dev;
216
217 int devid;
218 int size;
219 int ret = -ENOMEM;
220 int irq;
221
222 const u32 *utmi_mode;
223 u32 reg;
224
225 void __iomem *base;
226 void *context;
227
228 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
229 if (!omap) {
230 dev_err(dev, "not enough memory\n");
231 return -ENOMEM;
232 }
233
234 platform_set_drvdata(pdev, omap);
235
236 irq = platform_get_irq(pdev, 1);
237 if (irq < 0) {
238 dev_err(dev, "missing IRQ resource\n");
239 return -EINVAL;
240 }
241
242 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
243 if (!res) {
244 dev_err(dev, "missing memory base resource\n");
245 return -EINVAL;
246 }
247
248 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
249 if (!base) {
250 dev_err(dev, "ioremap failed\n");
251 return -ENOMEM;
252 }
253
254 devid = dwc3_get_device_id();
255 if (devid < 0)
256 return -ENODEV;
257
258 dwc3 = platform_device_alloc("dwc3", devid);
259 if (!dwc3) {
260 dev_err(dev, "couldn't allocate dwc3 device\n");
261 goto err1;
262 }
263
264 context = devm_kzalloc(dev, resource_size(res), GFP_KERNEL);
265 if (!context) {
266 dev_err(dev, "couldn't allocate dwc3 context memory\n");
267 goto err2;
268 }
269
270 spin_lock_init(&omap->lock);
271 dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
272
273 dwc3->dev.parent = dev;
274 dwc3->dev.dma_mask = dev->dma_mask;
275 dwc3->dev.dma_parms = dev->dma_parms;
276 omap->resource_size = resource_size(res);
277 omap->context = context;
278 omap->dev = dev;
279 omap->irq = irq;
280 omap->base = base;
281 omap->dwc3 = dwc3;
282
283 reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
284
285 utmi_mode = of_get_property(node, "utmi-mode", &size);
286 if (utmi_mode && size == sizeof(*utmi_mode)) {
287 reg |= *utmi_mode;
288 } else {
289 if (!pdata) {
290 dev_dbg(dev, "missing platform data\n");
291 } else {
292 switch (pdata->utmi_mode) {
293 case DWC3_OMAP_UTMI_MODE_SW:
294 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
295 break;
296 case DWC3_OMAP_UTMI_MODE_HW:
297 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
298 break;
299 default:
300 dev_dbg(dev, "UNKNOWN utmi mode %d\n",
301 pdata->utmi_mode);
302 }
303 }
304 }
305
306 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
307
308 /* check the DMA Status */
309 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
310 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
311
312 /* Set No-Idle and No-Standby */
313 reg &= ~(USBOTGSS_STANDBYMODE_MASK
314 | USBOTGSS_IDLEMODE_MASK);
315
316 reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
317 | USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
318
319 dwc3_omap_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
320
321 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
322 "dwc3-omap", omap);
323 if (ret) {
324 dev_err(dev, "failed to request IRQ #%d --> %d\n",
325 omap->irq, ret);
326 goto err2;
327 }
328
329 /* enable all IRQs */
330 reg = USBOTGSS_IRQO_COREIRQ_ST;
331 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
332
333 reg = (USBOTGSS_IRQ1_OEVT |
334 USBOTGSS_IRQ1_DRVVBUS_RISE |
335 USBOTGSS_IRQ1_CHRGVBUS_RISE |
336 USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
337 USBOTGSS_IRQ1_IDPULLUP_RISE |
338 USBOTGSS_IRQ1_DRVVBUS_FALL |
339 USBOTGSS_IRQ1_CHRGVBUS_FALL |
340 USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
341 USBOTGSS_IRQ1_IDPULLUP_FALL);
342
343 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
344
345 ret = platform_device_add_resources(dwc3, pdev->resource,
346 pdev->num_resources);
347 if (ret) {
348 dev_err(dev, "couldn't add resources to dwc3 device\n");
349 goto err2;
350 }
351
352 ret = platform_device_add(dwc3);
353 if (ret) {
354 dev_err(dev, "failed to register dwc3 device\n");
355 goto err2;
356 }
357
358 return 0;
359
360err2:
361 platform_device_put(dwc3);
362
363err1:
364 dwc3_put_device_id(devid);
365
366 return ret;
367}
368
369static int __devexit dwc3_omap_remove(struct platform_device *pdev)
370{
371 struct dwc3_omap *omap = platform_get_drvdata(pdev);
372
373 platform_device_unregister(omap->dwc3);
374
375 dwc3_put_device_id(omap->dwc3->id);
376
377 return 0;
378}
379
380static const struct of_device_id of_dwc3_matach[] = {
381 {
382 "ti,dwc3",
383 },
384 { },
385};
386MODULE_DEVICE_TABLE(of, of_dwc3_matach);
387
388static struct platform_driver dwc3_omap_driver = {
389 .probe = dwc3_omap_probe,
390 .remove = __devexit_p(dwc3_omap_remove),
391 .driver = {
392 .name = "omap-dwc3",
393 .of_match_table = of_dwc3_matach,
394 },
395};
396
397module_platform_driver(dwc3_omap_driver);
398
399MODULE_ALIAS("platform:omap-dwc3");
400MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
401MODULE_LICENSE("Dual BSD/GPL");
402MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");