1/*******************************************************************************
   2
   3  Intel 10 Gigabit PCI Express Linux driver
   4  Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  Linux NICS <linux.nics@intel.com>
  24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27*******************************************************************************/
  28
  29#include <linux/pci.h>
  30#include <linux/delay.h>
  31#include <linux/sched.h>
  32
  33#include "ixgbe.h"
  34#include "ixgbe_phy.h"
  35
  36static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  37static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  38static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  39static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  40static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  41static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  42static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  43static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  45static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  46static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  47static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  48static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  49static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  50static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
  51
  52/**
  53 *  ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54 *  @hw: pointer to the hardware structure
  55 *  @byte: byte to send
  56 *
  57 *  Returns an error code on error.
  58 **/
  59static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60{
  61	s32 status;
  62
  63	status = ixgbe_clock_out_i2c_byte(hw, byte);
  64	if (status)
  65		return status;
  66	return ixgbe_get_i2c_ack(hw);
  67}
  68
  69/**
  70 *  ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71 *  @hw: pointer to the hardware structure
  72 *  @byte: pointer to a u8 to receive the byte
  73 *
  74 *  Returns an error code on error.
  75 **/
  76static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77{
  78	s32 status;
  79
  80	status = ixgbe_clock_in_i2c_byte(hw, byte);
  81	if (status)
  82		return status;
  83	/* ACK */
  84	return ixgbe_clock_out_i2c_bit(hw, false);
  85}
  86
  87/**
  88 *  ixgbe_ones_comp_byte_add - Perform one's complement addition
  89 *  @add1: addend 1
  90 *  @add2: addend 2
  91 *
  92 *  Returns one's complement 8-bit sum.
  93 **/
  94static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95{
  96	u16 sum = add1 + add2;
  97
  98	sum = (sum & 0xFF) + (sum >> 8);
  99	return sum & 0xFF;
 100}
 101
 102/**
 103 *  ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104 *  @hw: pointer to the hardware structure
 105 *  @addr: I2C bus address to read from
 106 *  @reg: I2C device register to read from
 107 *  @val: pointer to location to receive read value
 108 *  @lock: true if to take and release semaphore
 109 *
 110 *  Returns an error code on error.
 111 */
 112s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 113					u16 reg, u16 *val, bool lock)
 114{
 115	u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116	int max_retry = 3;
 117	int retry = 0;
 118	u8 csum_byte;
 119	u8 high_bits;
 120	u8 low_bits;
 121	u8 reg_high;
 122	u8 csum;
 123
 124	reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 125	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 126	csum = ~csum;
 127	do {
 128		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 129			return IXGBE_ERR_SWFW_SYNC;
 130		ixgbe_i2c_start(hw);
 131		/* Device Address and write indication */
 132		if (ixgbe_out_i2c_byte_ack(hw, addr))
 133			goto fail;
 134		/* Write bits 14:8 */
 135		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 136			goto fail;
 137		/* Write bits 7:0 */
 138		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 139			goto fail;
 140		/* Write csum */
 141		if (ixgbe_out_i2c_byte_ack(hw, csum))
 142			goto fail;
 143		/* Re-start condition */
 144		ixgbe_i2c_start(hw);
 145		/* Device Address and read indication */
 146		if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 147			goto fail;
 148		/* Get upper bits */
 149		if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 150			goto fail;
 151		/* Get low bits */
 152		if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 153			goto fail;
 154		/* Get csum */
 155		if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 156			goto fail;
 157		/* NACK */
 158		if (ixgbe_clock_out_i2c_bit(hw, false))
 159			goto fail;
 160		ixgbe_i2c_stop(hw);
 161		if (lock)
 162			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 163		*val = (high_bits << 8) | low_bits;
 164		return 0;
 165
 166fail:
 167		ixgbe_i2c_bus_clear(hw);
 168		if (lock)
 169			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 170		retry++;
 171		if (retry < max_retry)
 172			hw_dbg(hw, "I2C byte read combined error - Retry.\n");
 173		else
 174			hw_dbg(hw, "I2C byte read combined error.\n");
 175	} while (retry < max_retry);
 176
 177	return IXGBE_ERR_I2C;
 178}
 179
 180/**
 181 *  ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 182 *  @hw: pointer to the hardware structure
 183 *  @addr: I2C bus address to write to
 184 *  @reg: I2C device register to write to
 185 *  @val: value to write
 186 *  @lock: true if to take and release semaphore
 187 *
 188 *  Returns an error code on error.
 189 */
 190s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
 191					 u16 reg, u16 val, bool lock)
 192{
 193	u32 swfw_mask = hw->phy.phy_semaphore_mask;
 194	int max_retry = 1;
 195	int retry = 0;
 196	u8 reg_high;
 197	u8 csum;
 198
 199	reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 200	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 201	csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 202	csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 203	csum = ~csum;
 204	do {
 205		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 206			return IXGBE_ERR_SWFW_SYNC;
 207		ixgbe_i2c_start(hw);
 208		/* Device Address and write indication */
 209		if (ixgbe_out_i2c_byte_ack(hw, addr))
 210			goto fail;
 211		/* Write bits 14:8 */
 212		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 213			goto fail;
 214		/* Write bits 7:0 */
 215		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 216			goto fail;
 217		/* Write data 15:8 */
 218		if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 219			goto fail;
 220		/* Write data 7:0 */
 221		if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 222			goto fail;
 223		/* Write csum */
 224		if (ixgbe_out_i2c_byte_ack(hw, csum))
 225			goto fail;
 226		ixgbe_i2c_stop(hw);
 227		if (lock)
 228			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 229		return 0;
 230
 231fail:
 232		ixgbe_i2c_bus_clear(hw);
 233		if (lock)
 234			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 235		retry++;
 236		if (retry < max_retry)
 237			hw_dbg(hw, "I2C byte write combined error - Retry.\n");
 238		else
 239			hw_dbg(hw, "I2C byte write combined error.\n");
 240	} while (retry < max_retry);
 241
 242	return IXGBE_ERR_I2C;
 243}
 244
 245/**
 246 *  ixgbe_probe_phy - Probe a single address for a PHY
 247 *  @hw: pointer to hardware structure
 248 *  @phy_addr: PHY address to probe
 249 *
 250 *  Returns true if PHY found
 251 **/
 252static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 253{
 254	u16 ext_ability = 0;
 255
 256	hw->phy.mdio.prtad = phy_addr;
 257	if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
 258		return false;
 259
 260	if (ixgbe_get_phy_id(hw))
 261		return false;
 262
 263	hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 264
 265	if (hw->phy.type == ixgbe_phy_unknown) {
 266		hw->phy.ops.read_reg(hw,
 267				     MDIO_PMA_EXTABLE,
 268				     MDIO_MMD_PMAPMD,
 269				     &ext_ability);
 270		if (ext_ability &
 271		    (MDIO_PMA_EXTABLE_10GBT |
 272		     MDIO_PMA_EXTABLE_1000BT))
 273			hw->phy.type = ixgbe_phy_cu_unknown;
 274		else
 275			hw->phy.type = ixgbe_phy_generic;
 276	}
 277
 278	return true;
 279}
 280
 281/**
 282 *  ixgbe_identify_phy_generic - Get physical layer module
 283 *  @hw: pointer to hardware structure
 284 *
 285 *  Determines the physical layer module found on the current adapter.
 286 **/
 287s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 288{
 
 289	u32 phy_addr;
 290	u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 291
 292	if (!hw->phy.phy_semaphore_mask) {
 293		if (hw->bus.lan_id)
 294			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 295		else
 296			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 297	}
 298
 299	if (hw->phy.type != ixgbe_phy_unknown)
 300		return 0;
 
 
 
 
 
 301
 302	if (hw->phy.nw_mng_if_sel) {
 303		phy_addr = (hw->phy.nw_mng_if_sel &
 304			    IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 305			   IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 306		if (ixgbe_probe_phy(hw, phy_addr))
 307			return 0;
 308		else
 309			return IXGBE_ERR_PHY_ADDR_INVALID;
 310	}
 
 
 
 
 
 311
 312	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 313		if (ixgbe_probe_phy(hw, phy_addr)) {
 314			status = 0;
 315			break;
 316		}
 
 
 
 
 
 317	}
 318
 319	/* Certain media types do not have a phy so an address will not
 320	 * be found and the code will take this path.  Caller has to
 321	 * decide if it is an error or not.
 322	 */
 323	if (status)
 324		hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
 325
 326	return status;
 327}
 328
 329/**
 330 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 331 * @hw: pointer to the hardware structure
 332 *
 333 * This function checks the MMNGC.MNG_VETO bit to see if there are
 334 * any constraints on link from manageability.  For MAC's that don't
 335 * have this bit just return false since the link can not be blocked
 336 * via this method.
 337 **/
 338bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 339{
 340	u32 mmngc;
 341
 342	/* If we don't have this bit, it can't be blocking */
 343	if (hw->mac.type == ixgbe_mac_82598EB)
 344		return false;
 345
 346	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 347	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 348		hw_dbg(hw, "MNG_VETO bit detected.\n");
 349		return true;
 350	}
 351
 352	return false;
 353}
 354
 355/**
 356 *  ixgbe_get_phy_id - Get the phy type
 357 *  @hw: pointer to hardware structure
 358 *
 359 **/
 360static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 361{
 362	s32 status;
 363	u16 phy_id_high = 0;
 364	u16 phy_id_low = 0;
 365
 366	status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 367				      &phy_id_high);
 368
 369	if (!status) {
 370		hw->phy.id = (u32)(phy_id_high << 16);
 371		status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 372					      &phy_id_low);
 373		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 374		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 375	}
 376	return status;
 377}
 378
 379/**
 380 *  ixgbe_get_phy_type_from_id - Get the phy type
 381 *  @phy_id: hardware phy id
 382 *
 383 **/
 384static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 385{
 386	enum ixgbe_phy_type phy_type;
 387
 388	switch (phy_id) {
 389	case TN1010_PHY_ID:
 390		phy_type = ixgbe_phy_tn;
 391		break;
 392	case X550_PHY_ID2:
 393	case X550_PHY_ID3:
 394	case X540_PHY_ID:
 395		phy_type = ixgbe_phy_aq;
 396		break;
 397	case QT2022_PHY_ID:
 398		phy_type = ixgbe_phy_qt;
 399		break;
 400	case ATH_PHY_ID:
 401		phy_type = ixgbe_phy_nl;
 402		break;
 403	case X557_PHY_ID:
 404	case X557_PHY_ID2:
 405		phy_type = ixgbe_phy_x550em_ext_t;
 406		break;
 407	default:
 408		phy_type = ixgbe_phy_unknown;
 409		break;
 410	}
 411
 412	return phy_type;
 413}
 414
 415/**
 416 *  ixgbe_reset_phy_generic - Performs a PHY reset
 417 *  @hw: pointer to hardware structure
 418 **/
 419s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 420{
 421	u32 i;
 422	u16 ctrl = 0;
 423	s32 status = 0;
 424
 425	if (hw->phy.type == ixgbe_phy_unknown)
 426		status = ixgbe_identify_phy_generic(hw);
 427
 428	if (status != 0 || hw->phy.type == ixgbe_phy_none)
 429		return status;
 430
 431	/* Don't reset PHY if it's shut down due to overtemp. */
 432	if (!hw->phy.reset_if_overtemp &&
 433	    (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 434		return 0;
 435
 436	/* Blocked by MNG FW so bail */
 437	if (ixgbe_check_reset_blocked(hw))
 438		return 0;
 439
 440	/*
 441	 * Perform soft PHY reset to the PHY_XS.
 442	 * This will cause a soft reset to the PHY
 443	 */
 444	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 445			      MDIO_MMD_PHYXS,
 446			      MDIO_CTRL1_RESET);
 447
 448	/*
 449	 * Poll for reset bit to self-clear indicating reset is complete.
 450	 * Some PHYs could take up to 3 seconds to complete and need about
 451	 * 1.7 usec delay after the reset is complete.
 452	 */
 453	for (i = 0; i < 30; i++) {
 454		msleep(100);
 455		if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 456			status = hw->phy.ops.read_reg(hw,
 457						  IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 458						  MDIO_MMD_PMAPMD, &ctrl);
 459			if (status)
 460				return status;
 461
 462			if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 463				udelay(2);
 464				break;
 465			}
 466		} else {
 467			status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 468						      MDIO_MMD_PHYXS, &ctrl);
 469			if (status)
 470				return status;
 471
 472			if (!(ctrl & MDIO_CTRL1_RESET)) {
 473				udelay(2);
 474				break;
 475			}
 476		}
 477	}
 478
 479	if (ctrl & MDIO_CTRL1_RESET) {
 
 480		hw_dbg(hw, "PHY reset polling failed to complete.\n");
 481		return IXGBE_ERR_RESET_FAILED;
 482	}
 483
 484	return 0;
 
 485}
 486
 487/**
 488 *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 489 *  the SWFW lock
 490 *  @hw: pointer to hardware structure
 491 *  @reg_addr: 32 bit address of PHY register to read
 492 *  @device_type: 5 bit device type
 493 *  @phy_data: Pointer to read data from PHY register
 494 **/
 495s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 496		       u16 *phy_data)
 497{
 498	u32 i, data, command;
 
 
 
 
 499
 500	/* Setup and write the address cycle command */
 501	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 502		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 503		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 504		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 505
 506	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 507
 508	/* Check every 10 usec to see if the address cycle completed.
 509	 * The MDI Command bit will clear when the operation is
 510	 * complete
 511	 */
 512	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 513		udelay(10);
 514
 515		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 516		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 517				break;
 518	}
 519
 
 
 
 
 
 
 520
 521	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 522		hw_dbg(hw, "PHY address command did not complete.\n");
 523		return IXGBE_ERR_PHY;
 524	}
 525
 526	/* Address cycle complete, setup and write the read
 527	 * command
 528	 */
 529	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 530		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 531		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 532		   (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 533
 534	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 535
 536	/* Check every 10 usec to see if the address cycle
 537	 * completed. The MDI Command bit will clear when the
 538	 * operation is complete
 539	 */
 540	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 541		udelay(10);
 542
 543		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 544		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 545			break;
 546	}
 547
 548	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 549		hw_dbg(hw, "PHY read command didn't complete\n");
 550		return IXGBE_ERR_PHY;
 551	}
 552
 553	/* Read operation is complete.  Get the data
 554	 * from MSRWD
 555	 */
 556	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 557	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 558	*phy_data = (u16)(data);
 559
 560	return 0;
 561}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 562
 563/**
 564 *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 565 *  using the SWFW lock - this function is needed in most cases
 566 *  @hw: pointer to hardware structure
 567 *  @reg_addr: 32 bit address of PHY register to read
 568 *  @device_type: 5 bit device type
 569 *  @phy_data: Pointer to read data from PHY register
 570 **/
 571s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 572			       u32 device_type, u16 *phy_data)
 573{
 574	s32 status;
 575	u32 gssr = hw->phy.phy_semaphore_mask;
 
 
 
 
 
 
 576
 577	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 578		status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 579						phy_data);
 580		hw->mac.ops.release_swfw_sync(hw, gssr);
 581	} else {
 582		return IXGBE_ERR_SWFW_SYNC;
 583	}
 584
 585	return status;
 586}
 587
 588/**
 589 *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 590 *  without SWFW lock
 591 *  @hw: pointer to hardware structure
 592 *  @reg_addr: 32 bit PHY register to write
 593 *  @device_type: 5 bit device type
 594 *  @phy_data: Data to write to the PHY register
 595 **/
 596s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 597				u32 device_type, u16 phy_data)
 598{
 599	u32 i, command;
 
 
 
 600
 601	/* Put the data in the MDI single read and write data register*/
 602	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 
 
 603
 604	/* Setup and write the address cycle command */
 605	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 606		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 607		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 608		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 609
 610	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 
 
 611
 612	/*
 613	 * Check every 10 usec to see if the address cycle completed.
 614	 * The MDI Command bit will clear when the operation is
 615	 * complete
 616	 */
 617	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 618		udelay(10);
 619
 620		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 621		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 622			break;
 623	}
 624
 625	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 626		hw_dbg(hw, "PHY address cmd didn't complete\n");
 627		return IXGBE_ERR_PHY;
 628	}
 
 
 
 629
 630	/*
 631	 * Address cycle complete, setup and write the write
 632	 * command
 633	 */
 634	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 635		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 636		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 637		   (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 638
 639	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 640
 641	/* Check every 10 usec to see if the address cycle
 642	 * completed. The MDI Command bit will clear when the
 643	 * operation is complete
 644	 */
 645	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 646		udelay(10);
 647
 648		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 649		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 650			break;
 651	}
 652
 653	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 654		hw_dbg(hw, "PHY write cmd didn't complete\n");
 655		return IXGBE_ERR_PHY;
 656	}
 657
 658	return 0;
 659}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 660
 661/**
 662 *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 663 *  using SWFW lock- this function is needed in most cases
 664 *  @hw: pointer to hardware structure
 665 *  @reg_addr: 32 bit PHY register to write
 666 *  @device_type: 5 bit device type
 667 *  @phy_data: Data to write to the PHY register
 668 **/
 669s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 670				u32 device_type, u16 phy_data)
 671{
 672	s32 status;
 673	u32 gssr = hw->phy.phy_semaphore_mask;
 674
 675	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 676		status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 677						 phy_data);
 678		hw->mac.ops.release_swfw_sync(hw, gssr);
 679	} else {
 680		return IXGBE_ERR_SWFW_SYNC;
 681	}
 682
 683	return status;
 684}
 685
 686/**
 687 *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 688 *  @hw: pointer to hardware structure
 689 *
 690 *  Restart autonegotiation and PHY and waits for completion.
 691 **/
 692s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 693{
 694	s32 status = 0;
 
 
 695	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 696	bool autoneg = false;
 697	ixgbe_link_speed speed;
 698
 699	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 700
 701	/* Set or unset auto-negotiation 10G advertisement */
 702	hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
 
 
 
 703
 704	autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 705	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 706	    (speed & IXGBE_LINK_SPEED_10GB_FULL))
 707		autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 708
 709	hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
 
 
 
 710
 711	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 712			     MDIO_MMD_AN, &autoneg_reg);
 
 
 
 
 713
 714	if (hw->mac.type == ixgbe_mac_X550) {
 715		/* Set or unset auto-negotiation 5G advertisement */
 716		autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 717		if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 718		    (speed & IXGBE_LINK_SPEED_5GB_FULL))
 719			autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 720
 721		/* Set or unset auto-negotiation 2.5G advertisement */
 722		autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 723		if ((hw->phy.autoneg_advertised &
 724		     IXGBE_LINK_SPEED_2_5GB_FULL) &&
 725		    (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 726			autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 727	}
 728
 729	/* Set or unset auto-negotiation 1G advertisement */
 730	autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 731	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 732	    (speed & IXGBE_LINK_SPEED_1GB_FULL))
 733		autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 734
 735	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 736			      MDIO_MMD_AN, autoneg_reg);
 
 
 
 737
 738	/* Set or unset auto-negotiation 100M advertisement */
 739	hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
 
 
 
 740
 741	autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
 742	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 743	    (speed & IXGBE_LINK_SPEED_100_FULL))
 744		autoneg_reg |= ADVERTISE_100FULL;
 745
 746	hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
 747
 748	/* Blocked by MNG FW so don't reset PHY */
 749	if (ixgbe_check_reset_blocked(hw))
 750		return 0;
 751
 752	/* Restart PHY autonegotiation and wait for completion */
 753	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 754			     MDIO_MMD_AN, &autoneg_reg);
 755
 756	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 757
 758	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 759			      MDIO_MMD_AN, autoneg_reg);
 760
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 761	return status;
 762}
 763
 764/**
 765 *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 766 *  @hw: pointer to hardware structure
 767 *  @speed: new link speed
 768 *  @autoneg_wait_to_complete: unused
 769 **/
 770s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 771				       ixgbe_link_speed speed,
 772				       bool autoneg_wait_to_complete)
 
 773{
 774	/* Clear autoneg_advertised and set new values based on input link
 
 
 775	 * speed.
 776	 */
 777	hw->phy.autoneg_advertised = 0;
 778
 779	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 780		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 781
 782	if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 783		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 784
 785	if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 786		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 787
 788	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 789		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 790
 791	if (speed & IXGBE_LINK_SPEED_100_FULL)
 792		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 793
 794	if (speed & IXGBE_LINK_SPEED_10_FULL)
 795		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 796
 797	/* Setup link based on the new speed settings */
 798	if (hw->phy.ops.setup_link)
 799		hw->phy.ops.setup_link(hw);
 800
 801	return 0;
 802}
 803
 804/**
 805 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
 806 * @hw: pointer to hardware structure
 807 *
 808 * Determines the supported link capabilities by reading the PHY auto
 809 * negotiation register.
 810 */
 811static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 812{
 813	u16 speed_ability;
 814	s32 status;
 815
 816	status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 817				      &speed_ability);
 818	if (status)
 819		return status;
 820
 821	if (speed_ability & MDIO_SPEED_10G)
 822		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 823	if (speed_ability & MDIO_PMA_SPEED_1000)
 824		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 825	if (speed_ability & MDIO_PMA_SPEED_100)
 826		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 827
 828	switch (hw->mac.type) {
 829	case ixgbe_mac_X550:
 830		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 831		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 832		break;
 833	case ixgbe_mac_X550EM_x:
 834	case ixgbe_mac_x550em_a:
 835		hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 836		break;
 837	default:
 838		break;
 839	}
 840
 841	return 0;
 842}
 843
 844/**
 845 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 846 * @hw: pointer to hardware structure
 847 * @speed: pointer to link speed
 848 * @autoneg: boolean auto-negotiation value
 
 
 849 */
 850s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 851					       ixgbe_link_speed *speed,
 852					       bool *autoneg)
 853{
 854	s32 status = 0;
 
 855
 
 856	*autoneg = true;
 857	if (!hw->phy.speeds_supported)
 858		status = ixgbe_get_copper_speeds_supported(hw);
 859
 860	*speed = hw->phy.speeds_supported;
 
 
 
 
 
 
 
 
 
 
 
 861	return status;
 862}
 863
 864/**
 865 *  ixgbe_check_phy_link_tnx - Determine link and speed status
 866 *  @hw: pointer to hardware structure
 867 *  @speed: link speed
 868 *  @link_up: status of link
 869 *
 870 *  Reads the VS1 register to determine if link is up and the current speed for
 871 *  the PHY.
 872 **/
 873s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 874			     bool *link_up)
 875{
 876	s32 status;
 877	u32 time_out;
 878	u32 max_time_out = 10;
 879	u16 phy_link = 0;
 880	u16 phy_speed = 0;
 881	u16 phy_data = 0;
 882
 883	/* Initialize speed and link to default case */
 884	*link_up = false;
 885	*speed = IXGBE_LINK_SPEED_10GB_FULL;
 886
 887	/*
 888	 * Check current speed and link status of the PHY register.
 889	 * This is a vendor specific register and may have to
 890	 * be changed for other copper PHYs.
 891	 */
 892	for (time_out = 0; time_out < max_time_out; time_out++) {
 893		udelay(10);
 894		status = hw->phy.ops.read_reg(hw,
 895					      MDIO_STAT1,
 896					      MDIO_MMD_VEND1,
 897					      &phy_data);
 898		phy_link = phy_data &
 899			    IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 900		phy_speed = phy_data &
 901			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 902		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 903			*link_up = true;
 904			if (phy_speed ==
 905			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 906				*speed = IXGBE_LINK_SPEED_1GB_FULL;
 907			break;
 908		}
 909	}
 910
 911	return status;
 912}
 913
 914/**
 915 *	ixgbe_setup_phy_link_tnx - Set and restart autoneg
 916 *	@hw: pointer to hardware structure
 917 *
 918 *	Restart autonegotiation and PHY and waits for completion.
 919 *      This function always returns success, this is nessary since
 920 *	it is called via a function pointer that could call other
 921 *	functions that could return an error.
 922 **/
 923s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 924{
 
 
 
 925	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 926	bool autoneg = false;
 927	ixgbe_link_speed speed;
 928
 929	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 930
 931	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 932		/* Set or unset auto-negotiation 10G advertisement */
 933		hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 934				     MDIO_MMD_AN,
 935				     &autoneg_reg);
 936
 937		autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 938		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 939			autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 940
 941		hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 942				      MDIO_MMD_AN,
 943				      autoneg_reg);
 944	}
 945
 946	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 947		/* Set or unset auto-negotiation 1G advertisement */
 948		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 949				     MDIO_MMD_AN,
 950				     &autoneg_reg);
 951
 952		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 953		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 954			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 955
 956		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 957				      MDIO_MMD_AN,
 958				      autoneg_reg);
 959	}
 960
 961	if (speed & IXGBE_LINK_SPEED_100_FULL) {
 962		/* Set or unset auto-negotiation 100M advertisement */
 963		hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 964				     MDIO_MMD_AN,
 965				     &autoneg_reg);
 966
 967		autoneg_reg &= ~(ADVERTISE_100FULL |
 968				 ADVERTISE_100HALF);
 969		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 970			autoneg_reg |= ADVERTISE_100FULL;
 971
 972		hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 973				      MDIO_MMD_AN,
 974				      autoneg_reg);
 975	}
 976
 977	/* Blocked by MNG FW so don't reset PHY */
 978	if (ixgbe_check_reset_blocked(hw))
 979		return 0;
 980
 981	/* Restart PHY autonegotiation and wait for completion */
 982	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 983			     MDIO_MMD_AN, &autoneg_reg);
 984
 985	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 986
 987	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 988			      MDIO_MMD_AN, autoneg_reg);
 989	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 990}
 991
 992/**
 993 *  ixgbe_reset_phy_nl - Performs a PHY reset
 994 *  @hw: pointer to hardware structure
 995 **/
 996s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 997{
 998	u16 phy_offset, control, eword, edata, block_crc;
 999	bool end_data = false;
1000	u16 list_offset, data_offset;
1001	u16 phy_data = 0;
1002	s32 ret_val;
1003	u32 i;
1004
1005	/* Blocked by MNG FW so bail */
1006	if (ixgbe_check_reset_blocked(hw))
1007		return 0;
1008
1009	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1010
1011	/* reset the PHY and poll for completion */
1012	hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1013			      (phy_data | MDIO_CTRL1_RESET));
1014
1015	for (i = 0; i < 100; i++) {
1016		hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1017				     &phy_data);
1018		if ((phy_data & MDIO_CTRL1_RESET) == 0)
1019			break;
1020		usleep_range(10000, 20000);
1021	}
1022
1023	if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1024		hw_dbg(hw, "PHY reset did not complete.\n");
1025		return IXGBE_ERR_PHY;
 
1026	}
1027
1028	/* Get init offsets */
1029	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1030						      &data_offset);
1031	if (ret_val)
1032		return ret_val;
1033
1034	ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1035	data_offset++;
1036	while (!end_data) {
1037		/*
1038		 * Read control word from PHY init contents offset
1039		 */
1040		ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1041		if (ret_val)
1042			goto err_eeprom;
1043		control = (eword & IXGBE_CONTROL_MASK_NL) >>
1044			   IXGBE_CONTROL_SHIFT_NL;
1045		edata = eword & IXGBE_DATA_MASK_NL;
1046		switch (control) {
1047		case IXGBE_DELAY_NL:
1048			data_offset++;
1049			hw_dbg(hw, "DELAY: %d MS\n", edata);
1050			usleep_range(edata * 1000, edata * 2000);
1051			break;
1052		case IXGBE_DATA_NL:
1053			hw_dbg(hw, "DATA:\n");
1054			data_offset++;
1055			ret_val = hw->eeprom.ops.read(hw, data_offset++,
1056						      &phy_offset);
1057			if (ret_val)
1058				goto err_eeprom;
1059			for (i = 0; i < edata; i++) {
1060				ret_val = hw->eeprom.ops.read(hw, data_offset,
1061							      &eword);
1062				if (ret_val)
1063					goto err_eeprom;
1064				hw->phy.ops.write_reg(hw, phy_offset,
1065						      MDIO_MMD_PMAPMD, eword);
1066				hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1067				       phy_offset);
1068				data_offset++;
1069				phy_offset++;
1070			}
1071			break;
1072		case IXGBE_CONTROL_NL:
1073			data_offset++;
1074			hw_dbg(hw, "CONTROL:\n");
1075			if (edata == IXGBE_CONTROL_EOL_NL) {
1076				hw_dbg(hw, "EOL\n");
1077				end_data = true;
1078			} else if (edata == IXGBE_CONTROL_SOL_NL) {
1079				hw_dbg(hw, "SOL\n");
1080			} else {
1081				hw_dbg(hw, "Bad control value\n");
1082				return IXGBE_ERR_PHY;
 
1083			}
1084			break;
1085		default:
1086			hw_dbg(hw, "Bad control type\n");
1087			return IXGBE_ERR_PHY;
 
1088		}
1089	}
1090
 
1091	return ret_val;
1092
1093err_eeprom:
1094	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1095	return IXGBE_ERR_PHY;
1096}
1097
1098/**
1099 *  ixgbe_identify_module_generic - Identifies module type
1100 *  @hw: pointer to hardware structure
1101 *
1102 *  Determines HW type and calls appropriate function.
1103 **/
1104s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1105{
1106	switch (hw->mac.ops.get_media_type(hw)) {
1107	case ixgbe_media_type_fiber:
1108		return ixgbe_identify_sfp_module_generic(hw);
1109	case ixgbe_media_type_fiber_qsfp:
1110		return ixgbe_identify_qsfp_module_generic(hw);
1111	default:
1112		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1113		return IXGBE_ERR_SFP_NOT_PRESENT;
1114	}
1115
1116	return IXGBE_ERR_SFP_NOT_PRESENT;
1117}
1118
1119/**
1120 *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1121 *  @hw: pointer to hardware structure
1122 *
1123 *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1124 **/
1125s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1126{
1127	struct ixgbe_adapter *adapter = hw->back;
1128	s32 status;
1129	u32 vendor_oui = 0;
1130	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1131	u8 identifier = 0;
1132	u8 comp_codes_1g = 0;
1133	u8 comp_codes_10g = 0;
1134	u8 oui_bytes[3] = {0, 0, 0};
1135	u8 cable_tech = 0;
1136	u8 cable_spec = 0;
1137	u16 enforce_sfp = 0;
1138
1139	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1140		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1141		return IXGBE_ERR_SFP_NOT_PRESENT;
 
1142	}
1143
1144	/* LAN ID is needed for sfp_type determination */
1145	hw->mac.ops.set_lan_id(hw);
1146
1147	status = hw->phy.ops.read_i2c_eeprom(hw,
1148					     IXGBE_SFF_IDENTIFIER,
1149					     &identifier);
1150
1151	if (status)
 
 
1152		goto err_read_i2c_eeprom;
1153
 
 
 
1154	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1155		hw->phy.type = ixgbe_phy_sfp_unsupported;
1156		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1157	}
1158	status = hw->phy.ops.read_i2c_eeprom(hw,
1159					     IXGBE_SFF_1GBE_COMP_CODES,
1160					     &comp_codes_1g);
1161
1162	if (status)
1163		goto err_read_i2c_eeprom;
1164
1165	status = hw->phy.ops.read_i2c_eeprom(hw,
1166					     IXGBE_SFF_10GBE_COMP_CODES,
1167					     &comp_codes_10g);
1168
1169	if (status)
1170		goto err_read_i2c_eeprom;
1171	status = hw->phy.ops.read_i2c_eeprom(hw,
1172					     IXGBE_SFF_CABLE_TECHNOLOGY,
1173					     &cable_tech);
1174
1175	if (status)
1176		goto err_read_i2c_eeprom;
1177
1178	 /* ID Module
1179	  * =========
1180	  * 0   SFP_DA_CU
1181	  * 1   SFP_SR
1182	  * 2   SFP_LR
1183	  * 3   SFP_DA_CORE0 - 82599-specific
1184	  * 4   SFP_DA_CORE1 - 82599-specific
1185	  * 5   SFP_SR/LR_CORE0 - 82599-specific
1186	  * 6   SFP_SR/LR_CORE1 - 82599-specific
1187	  * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1188	  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1189	  * 9   SFP_1g_cu_CORE0 - 82599-specific
1190	  * 10  SFP_1g_cu_CORE1 - 82599-specific
1191	  * 11  SFP_1g_sx_CORE0 - 82599-specific
1192	  * 12  SFP_1g_sx_CORE1 - 82599-specific
1193	  */
1194	if (hw->mac.type == ixgbe_mac_82598EB) {
1195		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1196			hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1197		else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1198			hw->phy.sfp_type = ixgbe_sfp_type_sr;
1199		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1200			hw->phy.sfp_type = ixgbe_sfp_type_lr;
1201		else
1202			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1203	} else {
1204		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1205			if (hw->bus.lan_id == 0)
1206				hw->phy.sfp_type =
1207					     ixgbe_sfp_type_da_cu_core0;
1208			else
1209				hw->phy.sfp_type =
1210					     ixgbe_sfp_type_da_cu_core1;
1211		} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1212			hw->phy.ops.read_i2c_eeprom(
1213					hw, IXGBE_SFF_CABLE_SPEC_COMP,
1214					&cable_spec);
1215			if (cable_spec &
1216			    IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1217				if (hw->bus.lan_id == 0)
1218					hw->phy.sfp_type =
1219					ixgbe_sfp_type_da_act_lmt_core0;
1220				else
1221					hw->phy.sfp_type =
1222					ixgbe_sfp_type_da_act_lmt_core1;
1223			} else {
1224				hw->phy.sfp_type =
1225						ixgbe_sfp_type_unknown;
1226			}
1227		} else if (comp_codes_10g &
1228			   (IXGBE_SFF_10GBASESR_CAPABLE |
1229			    IXGBE_SFF_10GBASELR_CAPABLE)) {
1230			if (hw->bus.lan_id == 0)
1231				hw->phy.sfp_type =
1232					      ixgbe_sfp_type_srlr_core0;
1233			else
1234				hw->phy.sfp_type =
1235					      ixgbe_sfp_type_srlr_core1;
1236		} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1237			if (hw->bus.lan_id == 0)
1238				hw->phy.sfp_type =
1239					ixgbe_sfp_type_1g_cu_core0;
1240			else
1241				hw->phy.sfp_type =
1242					ixgbe_sfp_type_1g_cu_core1;
1243		} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1244			if (hw->bus.lan_id == 0)
1245				hw->phy.sfp_type =
1246					ixgbe_sfp_type_1g_sx_core0;
1247			else
1248				hw->phy.sfp_type =
1249					ixgbe_sfp_type_1g_sx_core1;
1250		} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1251			if (hw->bus.lan_id == 0)
1252				hw->phy.sfp_type =
1253					ixgbe_sfp_type_1g_lx_core0;
1254			else
1255				hw->phy.sfp_type =
1256					ixgbe_sfp_type_1g_lx_core1;
1257		} else {
1258			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1259		}
1260	}
1261
1262	if (hw->phy.sfp_type != stored_sfp_type)
1263		hw->phy.sfp_setup_needed = true;
1264
1265	/* Determine if the SFP+ PHY is dual speed or not. */
1266	hw->phy.multispeed_fiber = false;
1267	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1268	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1269	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1270	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1271		hw->phy.multispeed_fiber = true;
1272
1273	/* Determine PHY vendor */
1274	if (hw->phy.type != ixgbe_phy_nl) {
1275		hw->phy.id = identifier;
1276		status = hw->phy.ops.read_i2c_eeprom(hw,
1277					    IXGBE_SFF_VENDOR_OUI_BYTE0,
1278					    &oui_bytes[0]);
1279
1280		if (status != 0)
 
 
1281			goto err_read_i2c_eeprom;
1282
1283		status = hw->phy.ops.read_i2c_eeprom(hw,
1284					    IXGBE_SFF_VENDOR_OUI_BYTE1,
1285					    &oui_bytes[1]);
1286
1287		if (status != 0)
 
 
1288			goto err_read_i2c_eeprom;
1289
1290		status = hw->phy.ops.read_i2c_eeprom(hw,
1291					    IXGBE_SFF_VENDOR_OUI_BYTE2,
1292					    &oui_bytes[2]);
1293
1294		if (status != 0)
 
 
1295			goto err_read_i2c_eeprom;
1296
1297		vendor_oui =
1298		  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1299		   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1300		   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1301
1302		switch (vendor_oui) {
1303		case IXGBE_SFF_VENDOR_OUI_TYCO:
 
 
 
 
 
 
 
 
1304			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1305				hw->phy.type =
1306					    ixgbe_phy_sfp_passive_tyco;
1307			break;
1308		case IXGBE_SFF_VENDOR_OUI_FTL:
1309			if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1310				hw->phy.type = ixgbe_phy_sfp_ftl_active;
1311			else
1312				hw->phy.type = ixgbe_phy_sfp_ftl;
1313			break;
1314		case IXGBE_SFF_VENDOR_OUI_AVAGO:
1315			hw->phy.type = ixgbe_phy_sfp_avago;
1316			break;
1317		case IXGBE_SFF_VENDOR_OUI_INTEL:
1318			hw->phy.type = ixgbe_phy_sfp_intel;
1319			break;
1320		default:
1321			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1322				hw->phy.type =
1323					 ixgbe_phy_sfp_passive_unknown;
1324			else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1325				hw->phy.type =
1326					ixgbe_phy_sfp_active_unknown;
1327			else
1328				hw->phy.type = ixgbe_phy_sfp_unknown;
1329			break;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1330		}
1331	}
1332
1333	/* Allow any DA cable vendor */
1334	if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1335	    IXGBE_SFF_DA_ACTIVE_CABLE))
1336		return 0;
1337
1338	/* Verify supported 1G SFP modules */
1339	if (comp_codes_10g == 0 &&
1340	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1341	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1342	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1343	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1344	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1345	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1346		hw->phy.type = ixgbe_phy_sfp_unsupported;
1347		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1348	}
1349
1350	/* Anything else 82598-based is supported */
1351	if (hw->mac.type == ixgbe_mac_82598EB)
1352		return 0;
1353
1354	hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1355	if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1356	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1357	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1358	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1359	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1360	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1361	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1362		/* Make sure we're a supported PHY type */
1363		if (hw->phy.type == ixgbe_phy_sfp_intel)
1364			return 0;
1365		if (hw->allow_unsupported_sfp) {
1366			e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1367			return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1368		}
1369		hw_dbg(hw, "SFP+ module not supported\n");
1370		hw->phy.type = ixgbe_phy_sfp_unsupported;
1371		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1372	}
1373	return 0;
1374
1375err_read_i2c_eeprom:
1376	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1377	if (hw->phy.type != ixgbe_phy_nl) {
1378		hw->phy.id = 0;
1379		hw->phy.type = ixgbe_phy_unknown;
1380	}
1381	return IXGBE_ERR_SFP_NOT_PRESENT;
1382}
1383
1384/**
1385 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1386 * @hw: pointer to hardware structure
1387 *
1388 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1389 **/
1390static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1391{
1392	struct ixgbe_adapter *adapter = hw->back;
1393	s32 status;
1394	u32 vendor_oui = 0;
1395	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1396	u8 identifier = 0;
1397	u8 comp_codes_1g = 0;
1398	u8 comp_codes_10g = 0;
1399	u8 oui_bytes[3] = {0, 0, 0};
1400	u16 enforce_sfp = 0;
1401	u8 connector = 0;
1402	u8 cable_length = 0;
1403	u8 device_tech = 0;
1404	bool active_cable = false;
1405
1406	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1407		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1408		return IXGBE_ERR_SFP_NOT_PRESENT;
1409	}
1410
1411	/* LAN ID is needed for sfp_type determination */
1412	hw->mac.ops.set_lan_id(hw);
1413
1414	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1415					     &identifier);
1416
1417	if (status != 0)
1418		goto err_read_i2c_eeprom;
1419
1420	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1421		hw->phy.type = ixgbe_phy_sfp_unsupported;
1422		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1423	}
1424
1425	hw->phy.id = identifier;
1426
1427	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1428					     &comp_codes_10g);
1429
1430	if (status != 0)
1431		goto err_read_i2c_eeprom;
1432
1433	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1434					     &comp_codes_1g);
1435
1436	if (status != 0)
1437		goto err_read_i2c_eeprom;
1438
1439	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1440		hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1441		if (hw->bus.lan_id == 0)
1442			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1443		else
1444			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1445	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1446				     IXGBE_SFF_10GBASELR_CAPABLE)) {
1447		if (hw->bus.lan_id == 0)
1448			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1449		else
1450			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1451	} else {
1452		if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1453			active_cable = true;
1454
1455		if (!active_cable) {
1456			/* check for active DA cables that pre-date
1457			 * SFF-8436 v3.6
1458			 */
1459			hw->phy.ops.read_i2c_eeprom(hw,
1460					IXGBE_SFF_QSFP_CONNECTOR,
1461					&connector);
1462
1463			hw->phy.ops.read_i2c_eeprom(hw,
1464					IXGBE_SFF_QSFP_CABLE_LENGTH,
1465					&cable_length);
1466
1467			hw->phy.ops.read_i2c_eeprom(hw,
1468					IXGBE_SFF_QSFP_DEVICE_TECH,
1469					&device_tech);
1470
1471			if ((connector ==
1472				     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1473			    (cable_length > 0) &&
1474			    ((device_tech >> 4) ==
1475				     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1476				active_cable = true;
1477		}
1478
1479		if (active_cable) {
1480			hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1481			if (hw->bus.lan_id == 0)
1482				hw->phy.sfp_type =
1483						ixgbe_sfp_type_da_act_lmt_core0;
1484			else
1485				hw->phy.sfp_type =
1486						ixgbe_sfp_type_da_act_lmt_core1;
1487		} else {
1488			/* unsupported module type */
1489			hw->phy.type = ixgbe_phy_sfp_unsupported;
1490			return IXGBE_ERR_SFP_NOT_SUPPORTED;
 
1491		}
1492	}
1493
1494	if (hw->phy.sfp_type != stored_sfp_type)
1495		hw->phy.sfp_setup_needed = true;
1496
1497	/* Determine if the QSFP+ PHY is dual speed or not. */
1498	hw->phy.multispeed_fiber = false;
1499	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1500	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1501	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1502	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1503		hw->phy.multispeed_fiber = true;
1504
1505	/* Determine PHY vendor for optical modules */
1506	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1507			      IXGBE_SFF_10GBASELR_CAPABLE)) {
1508		status = hw->phy.ops.read_i2c_eeprom(hw,
1509					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1510					&oui_bytes[0]);
1511
1512		if (status != 0)
1513			goto err_read_i2c_eeprom;
1514
1515		status = hw->phy.ops.read_i2c_eeprom(hw,
1516					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1517					&oui_bytes[1]);
1518
1519		if (status != 0)
1520			goto err_read_i2c_eeprom;
1521
1522		status = hw->phy.ops.read_i2c_eeprom(hw,
1523					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1524					&oui_bytes[2]);
1525
1526		if (status != 0)
1527			goto err_read_i2c_eeprom;
1528
1529		vendor_oui =
1530			((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1531			 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1532			 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1533
1534		if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1535			hw->phy.type = ixgbe_phy_qsfp_intel;
1536		else
1537			hw->phy.type = ixgbe_phy_qsfp_unknown;
1538
1539		hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1540		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
 
 
1541			/* Make sure we're a supported PHY type */
1542			if (hw->phy.type == ixgbe_phy_qsfp_intel)
1543				return 0;
1544			if (hw->allow_unsupported_sfp) {
1545				e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1546				return 0;
 
 
 
 
 
 
 
 
1547			}
1548			hw_dbg(hw, "QSFP module not supported\n");
1549			hw->phy.type = ixgbe_phy_sfp_unsupported;
1550			return IXGBE_ERR_SFP_NOT_SUPPORTED;
1551		}
1552		return 0;
1553	}
1554	return 0;
 
 
1555
1556err_read_i2c_eeprom:
1557	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1558	hw->phy.id = 0;
1559	hw->phy.type = ixgbe_phy_unknown;
1560
 
1561	return IXGBE_ERR_SFP_NOT_PRESENT;
1562}
1563
1564/**
1565 *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1566 *  @hw: pointer to hardware structure
1567 *  @list_offset: offset to the SFP ID list
1568 *  @data_offset: offset to the SFP data block
1569 *
1570 *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1571 *  so it returns the offsets to the phy init sequence block.
1572 **/
1573s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1574					u16 *list_offset,
1575					u16 *data_offset)
1576{
1577	u16 sfp_id;
1578	u16 sfp_type = hw->phy.sfp_type;
1579
1580	if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1581		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1582
1583	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1584		return IXGBE_ERR_SFP_NOT_PRESENT;
1585
1586	if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1587	    (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1588		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1589
1590	/*
1591	 * Limiting active cables and 1G Phys must be initialized as
1592	 * SR modules
1593	 */
1594	if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1595	    sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1596	    sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1597	    sfp_type == ixgbe_sfp_type_1g_sx_core0)
1598		sfp_type = ixgbe_sfp_type_srlr_core0;
1599	else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1600		 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1601		 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1602		 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1603		sfp_type = ixgbe_sfp_type_srlr_core1;
1604
1605	/* Read offset to PHY init contents */
1606	if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1607		hw_err(hw, "eeprom read at %d failed\n",
1608		       IXGBE_PHY_INIT_OFFSET_NL);
1609		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1610	}
1611
1612	if ((!*list_offset) || (*list_offset == 0xFFFF))
1613		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1614
1615	/* Shift offset to first ID word */
1616	(*list_offset)++;
1617
1618	/*
1619	 * Find the matching SFP ID in the EEPROM
1620	 * and program the init sequence
1621	 */
1622	if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1623		goto err_phy;
1624
1625	while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1626		if (sfp_id == sfp_type) {
1627			(*list_offset)++;
1628			if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1629				goto err_phy;
1630			if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1631				hw_dbg(hw, "SFP+ module not supported\n");
1632				return IXGBE_ERR_SFP_NOT_SUPPORTED;
1633			} else {
1634				break;
1635			}
1636		} else {
1637			(*list_offset) += 2;
1638			if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1639				goto err_phy;
1640		}
1641	}
1642
1643	if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1644		hw_dbg(hw, "No matching SFP+ module found\n");
1645		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1646	}
1647
1648	return 0;
1649
1650err_phy:
1651	hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1652	return IXGBE_ERR_PHY;
1653}
1654
1655/**
1656 *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1657 *  @hw: pointer to hardware structure
1658 *  @byte_offset: EEPROM byte offset to read
1659 *  @eeprom_data: value read
1660 *
1661 *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1662 **/
1663s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1664				  u8 *eeprom_data)
1665{
1666	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1667					 IXGBE_I2C_EEPROM_DEV_ADDR,
1668					 eeprom_data);
1669}
1670
1671/**
1672 *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1673 *  @hw: pointer to hardware structure
1674 *  @byte_offset: byte offset at address 0xA2
1675 *  @sff8472_data: value read
1676 *
1677 *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1678 **/
1679s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1680				   u8 *sff8472_data)
1681{
1682	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1683					 IXGBE_I2C_EEPROM_DEV_ADDR2,
1684					 sff8472_data);
1685}
1686
1687/**
1688 *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1689 *  @hw: pointer to hardware structure
1690 *  @byte_offset: EEPROM byte offset to write
1691 *  @eeprom_data: value to write
1692 *
1693 *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1694 **/
1695s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1696				   u8 eeprom_data)
1697{
1698	return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1699					  IXGBE_I2C_EEPROM_DEV_ADDR,
1700					  eeprom_data);
1701}
1702
1703/**
1704 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1705 * @hw: pointer to hardware structure
1706 * @offset: eeprom offset to be read
1707 * @addr: I2C address to be read
1708 */
1709static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1710{
1711	if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1712	    offset == IXGBE_SFF_IDENTIFIER &&
1713	    hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1714		return true;
1715	return false;
1716}
1717
1718/**
1719 *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1720 *  @hw: pointer to hardware structure
1721 *  @byte_offset: byte offset to read
1722 *  @dev_addr: device address
1723 *  @data: value read
1724 *  @lock: true if to take and release semaphore
1725 *
1726 *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1727 *  a specified device address.
1728 */
1729static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1730					   u8 dev_addr, u8 *data, bool lock)
1731{
1732	s32 status;
1733	u32 max_retry = 10;
1734	u32 retry = 0;
1735	u32 swfw_mask = hw->phy.phy_semaphore_mask;
1736	bool nack = true;
1737
1738	if (hw->mac.type >= ixgbe_mac_X550)
1739		max_retry = 3;
1740	if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1741		max_retry = IXGBE_SFP_DETECT_RETRIES;
1742
1743	*data = 0;
1744
 
 
 
 
 
1745	do {
1746		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1747			return IXGBE_ERR_SWFW_SYNC;
 
 
1748
1749		ixgbe_i2c_start(hw);
1750
1751		/* Device Address and write indication */
1752		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1753		if (status != 0)
1754			goto fail;
1755
1756		status = ixgbe_get_i2c_ack(hw);
1757		if (status != 0)
1758			goto fail;
1759
1760		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1761		if (status != 0)
1762			goto fail;
1763
1764		status = ixgbe_get_i2c_ack(hw);
1765		if (status != 0)
1766			goto fail;
1767
1768		ixgbe_i2c_start(hw);
1769
1770		/* Device Address and read indication */
1771		status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1772		if (status != 0)
1773			goto fail;
1774
1775		status = ixgbe_get_i2c_ack(hw);
1776		if (status != 0)
1777			goto fail;
1778
1779		status = ixgbe_clock_in_i2c_byte(hw, data);
1780		if (status != 0)
1781			goto fail;
1782
1783		status = ixgbe_clock_out_i2c_bit(hw, nack);
1784		if (status != 0)
1785			goto fail;
1786
1787		ixgbe_i2c_stop(hw);
1788		if (lock)
1789			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1790		return 0;
1791
1792fail:
 
 
1793		ixgbe_i2c_bus_clear(hw);
1794		if (lock) {
1795			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1796			msleep(100);
1797		}
1798		retry++;
1799		if (retry < max_retry)
1800			hw_dbg(hw, "I2C byte read error - Retrying.\n");
1801		else
1802			hw_dbg(hw, "I2C byte read error.\n");
1803
1804	} while (retry < max_retry);
1805
1806	return status;
1807}
1808
1809/**
1810 *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1811 *  @hw: pointer to hardware structure
1812 *  @byte_offset: byte offset to read
1813 *  @dev_addr: device address
1814 *  @data: value read
1815 *
1816 *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1817 *  a specified device address.
1818 */
1819s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1820				u8 dev_addr, u8 *data)
1821{
1822	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1823					       data, true);
1824}
1825
1826/**
1827 *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
1828 *  @hw: pointer to hardware structure
1829 *  @byte_offset: byte offset to read
1830 *  @dev_addr: device address
1831 *  @data: value read
1832 *
1833 *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1834 *  a specified device address.
1835 */
1836s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1837					 u8 dev_addr, u8 *data)
1838{
1839	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1840					       data, false);
1841}
1842
1843/**
1844 *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
1845 *  @hw: pointer to hardware structure
1846 *  @byte_offset: byte offset to write
1847 *  @dev_addr: device address
1848 *  @data: value to write
1849 *  @lock: true if to take and release semaphore
1850 *
1851 *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1852 *  a specified device address.
1853 */
1854static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1855					    u8 dev_addr, u8 data, bool lock)
1856{
1857	s32 status;
1858	u32 max_retry = 1;
1859	u32 retry = 0;
1860	u32 swfw_mask = hw->phy.phy_semaphore_mask;
1861
1862	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1863		return IXGBE_ERR_SWFW_SYNC;
 
 
 
 
 
 
 
1864
1865	do {
1866		ixgbe_i2c_start(hw);
1867
1868		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1869		if (status != 0)
1870			goto fail;
1871
1872		status = ixgbe_get_i2c_ack(hw);
1873		if (status != 0)
1874			goto fail;
1875
1876		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1877		if (status != 0)
1878			goto fail;
1879
1880		status = ixgbe_get_i2c_ack(hw);
1881		if (status != 0)
1882			goto fail;
1883
1884		status = ixgbe_clock_out_i2c_byte(hw, data);
1885		if (status != 0)
1886			goto fail;
1887
1888		status = ixgbe_get_i2c_ack(hw);
1889		if (status != 0)
1890			goto fail;
1891
1892		ixgbe_i2c_stop(hw);
1893		if (lock)
1894			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1895		return 0;
1896
1897fail:
1898		ixgbe_i2c_bus_clear(hw);
1899		retry++;
1900		if (retry < max_retry)
1901			hw_dbg(hw, "I2C byte write error - Retrying.\n");
1902		else
1903			hw_dbg(hw, "I2C byte write error.\n");
1904	} while (retry < max_retry);
1905
1906	if (lock)
1907		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1908
 
1909	return status;
1910}
1911
1912/**
1913 *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1914 *  @hw: pointer to hardware structure
1915 *  @byte_offset: byte offset to write
1916 *  @dev_addr: device address
1917 *  @data: value to write
1918 *
1919 *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1920 *  a specified device address.
1921 */
1922s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1923				 u8 dev_addr, u8 data)
1924{
1925	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1926						data, true);
1927}
1928
1929/**
1930 *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
1931 *  @hw: pointer to hardware structure
1932 *  @byte_offset: byte offset to write
1933 *  @dev_addr: device address
1934 *  @data: value to write
1935 *
1936 *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1937 *  a specified device address.
1938 */
1939s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1940					  u8 dev_addr, u8 data)
1941{
1942	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1943						data, false);
1944}
1945
1946/**
1947 *  ixgbe_i2c_start - Sets I2C start condition
1948 *  @hw: pointer to hardware structure
1949 *
1950 *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1951 *  Set bit-bang mode on X550 hardware.
1952 **/
1953static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1954{
1955	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1956
1957	i2cctl |= IXGBE_I2C_BB_EN(hw);
1958
1959	/* Start condition must begin with data and clock high */
1960	ixgbe_set_i2c_data(hw, &i2cctl, 1);
1961	ixgbe_raise_i2c_clk(hw, &i2cctl);
1962
1963	/* Setup time for start condition (4.7us) */
1964	udelay(IXGBE_I2C_T_SU_STA);
1965
1966	ixgbe_set_i2c_data(hw, &i2cctl, 0);
1967
1968	/* Hold time for start condition (4us) */
1969	udelay(IXGBE_I2C_T_HD_STA);
1970
1971	ixgbe_lower_i2c_clk(hw, &i2cctl);
1972
1973	/* Minimum low period of clock is 4.7 us */
1974	udelay(IXGBE_I2C_T_LOW);
1975
1976}
1977
1978/**
1979 *  ixgbe_i2c_stop - Sets I2C stop condition
1980 *  @hw: pointer to hardware structure
1981 *
1982 *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1983 *  Disables bit-bang mode and negates data output enable on X550
1984 *  hardware.
1985 **/
1986static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1987{
1988	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1989	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
1990	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
1991	u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
1992
1993	/* Stop condition must begin with data low and clock high */
1994	ixgbe_set_i2c_data(hw, &i2cctl, 0);
1995	ixgbe_raise_i2c_clk(hw, &i2cctl);
1996
1997	/* Setup time for stop condition (4us) */
1998	udelay(IXGBE_I2C_T_SU_STO);
1999
2000	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2001
2002	/* bus free time between stop and start (4.7us)*/
2003	udelay(IXGBE_I2C_T_BUF);
2004
2005	if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2006		i2cctl &= ~bb_en_bit;
2007		i2cctl |= data_oe_bit | clk_oe_bit;
2008		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2009		IXGBE_WRITE_FLUSH(hw);
2010	}
2011}
2012
2013/**
2014 *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2015 *  @hw: pointer to hardware structure
2016 *  @data: data byte to clock in
2017 *
2018 *  Clocks in one byte data via I2C data/clock
2019 **/
2020static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2021{
2022	s32 i;
2023	bool bit = false;
2024
2025	*data = 0;
2026	for (i = 7; i >= 0; i--) {
2027		ixgbe_clock_in_i2c_bit(hw, &bit);
2028		*data |= bit << i;
2029	}
2030
2031	return 0;
2032}
2033
2034/**
2035 *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2036 *  @hw: pointer to hardware structure
2037 *  @data: data byte clocked out
2038 *
2039 *  Clocks out one byte data via I2C data/clock
2040 **/
2041static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2042{
2043	s32 status;
2044	s32 i;
2045	u32 i2cctl;
2046	bool bit = false;
2047
2048	for (i = 7; i >= 0; i--) {
2049		bit = (data >> i) & 0x1;
2050		status = ixgbe_clock_out_i2c_bit(hw, bit);
2051
2052		if (status != 0)
2053			break;
2054	}
2055
2056	/* Release SDA line (set high) */
2057	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2058	i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2059	i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2060	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2061	IXGBE_WRITE_FLUSH(hw);
2062
2063	return status;
2064}
2065
2066/**
2067 *  ixgbe_get_i2c_ack - Polls for I2C ACK
2068 *  @hw: pointer to hardware structure
2069 *
2070 *  Clocks in/out one bit via I2C data/clock
2071 **/
2072static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2073{
2074	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2075	s32 status = 0;
2076	u32 i = 0;
2077	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2078	u32 timeout = 10;
2079	bool ack = true;
2080
2081	if (data_oe_bit) {
2082		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2083		i2cctl |= data_oe_bit;
2084		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2085		IXGBE_WRITE_FLUSH(hw);
2086	}
2087	ixgbe_raise_i2c_clk(hw, &i2cctl);
2088
 
2089	/* Minimum high period of clock is 4us */
2090	udelay(IXGBE_I2C_T_HIGH);
2091
2092	/* Poll for ACK.  Note that ACK in I2C spec is
2093	 * transition from 1 to 0 */
2094	for (i = 0; i < timeout; i++) {
2095		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2096		ack = ixgbe_get_i2c_data(hw, &i2cctl);
2097
2098		udelay(1);
2099		if (ack == 0)
2100			break;
2101	}
2102
2103	if (ack == 1) {
2104		hw_dbg(hw, "I2C ack was not received.\n");
2105		status = IXGBE_ERR_I2C;
2106	}
2107
2108	ixgbe_lower_i2c_clk(hw, &i2cctl);
2109
2110	/* Minimum low period of clock is 4.7 us */
2111	udelay(IXGBE_I2C_T_LOW);
2112
2113	return status;
2114}
2115
2116/**
2117 *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2118 *  @hw: pointer to hardware structure
2119 *  @data: read data value
2120 *
2121 *  Clocks in one bit via I2C data/clock
2122 **/
2123static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2124{
2125	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2126	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2127
2128	if (data_oe_bit) {
2129		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2130		i2cctl |= data_oe_bit;
2131		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2132		IXGBE_WRITE_FLUSH(hw);
2133	}
2134	ixgbe_raise_i2c_clk(hw, &i2cctl);
2135
2136	/* Minimum high period of clock is 4us */
2137	udelay(IXGBE_I2C_T_HIGH);
2138
2139	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2140	*data = ixgbe_get_i2c_data(hw, &i2cctl);
2141
2142	ixgbe_lower_i2c_clk(hw, &i2cctl);
2143
2144	/* Minimum low period of clock is 4.7 us */
2145	udelay(IXGBE_I2C_T_LOW);
2146
2147	return 0;
2148}
2149
2150/**
2151 *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2152 *  @hw: pointer to hardware structure
2153 *  @data: data value to write
2154 *
2155 *  Clocks out one bit via I2C data/clock
2156 **/
2157static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2158{
2159	s32 status;
2160	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2161
2162	status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2163	if (status == 0) {
2164		ixgbe_raise_i2c_clk(hw, &i2cctl);
2165
2166		/* Minimum high period of clock is 4us */
2167		udelay(IXGBE_I2C_T_HIGH);
2168
2169		ixgbe_lower_i2c_clk(hw, &i2cctl);
2170
2171		/* Minimum low period of clock is 4.7 us.
2172		 * This also takes care of the data hold time.
2173		 */
2174		udelay(IXGBE_I2C_T_LOW);
2175	} else {
 
2176		hw_dbg(hw, "I2C data was not set to %X\n", data);
2177		return IXGBE_ERR_I2C;
2178	}
2179
2180	return 0;
2181}
2182/**
2183 *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2184 *  @hw: pointer to hardware structure
2185 *  @i2cctl: Current value of I2CCTL register
2186 *
2187 *  Raises the I2C clock line '0'->'1'
2188 *  Negates the I2C clock output enable on X550 hardware.
2189 **/
2190static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2191{
2192	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2193	u32 i = 0;
2194	u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2195	u32 i2cctl_r = 0;
2196
2197	if (clk_oe_bit) {
2198		*i2cctl |= clk_oe_bit;
2199		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2200	}
2201
2202	for (i = 0; i < timeout; i++) {
2203		*i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2204		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2205		IXGBE_WRITE_FLUSH(hw);
2206		/* SCL rise time (1000ns) */
2207		udelay(IXGBE_I2C_T_RISE);
2208
2209		i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2210		if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2211			break;
2212	}
2213}
2214
2215/**
2216 *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2217 *  @hw: pointer to hardware structure
2218 *  @i2cctl: Current value of I2CCTL register
2219 *
2220 *  Lowers the I2C clock line '1'->'0'
2221 *  Asserts the I2C clock output enable on X550 hardware.
2222 **/
2223static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2224{
2225
2226	*i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2227	*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2228
2229	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2230	IXGBE_WRITE_FLUSH(hw);
2231
2232	/* SCL fall time (300ns) */
2233	udelay(IXGBE_I2C_T_FALL);
2234}
2235
2236/**
2237 *  ixgbe_set_i2c_data - Sets the I2C data bit
2238 *  @hw: pointer to hardware structure
2239 *  @i2cctl: Current value of I2CCTL register
2240 *  @data: I2C data value (0 or 1) to set
2241 *
2242 *  Sets the I2C data bit
2243 *  Asserts the I2C data output enable on X550 hardware.
2244 **/
2245static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2246{
2247	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2248
2249	if (data)
2250		*i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2251	else
2252		*i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2253	*i2cctl &= ~data_oe_bit;
2254
2255	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2256	IXGBE_WRITE_FLUSH(hw);
2257
2258	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2259	udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2260
2261	if (!data)	/* Can't verify data in this case */
2262		return 0;
2263	if (data_oe_bit) {
2264		*i2cctl |= data_oe_bit;
2265		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2266		IXGBE_WRITE_FLUSH(hw);
2267	}
2268
2269	/* Verify data was set correctly */
2270	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2271	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
 
2272		hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2273		return IXGBE_ERR_I2C;
2274	}
2275
2276	return 0;
2277}
2278
2279/**
2280 *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2281 *  @hw: pointer to hardware structure
2282 *  @i2cctl: Current value of I2CCTL register
2283 *
2284 *  Returns the I2C data bit value
2285 *  Negates the I2C data output enable on X550 hardware.
2286 **/
2287static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2288{
2289	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2290
2291	if (data_oe_bit) {
2292		*i2cctl |= data_oe_bit;
2293		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2294		IXGBE_WRITE_FLUSH(hw);
2295		udelay(IXGBE_I2C_T_FALL);
2296	}
2297
2298	if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2299		return true;
2300	return false;
2301}
2302
2303/**
2304 *  ixgbe_i2c_bus_clear - Clears the I2C bus
2305 *  @hw: pointer to hardware structure
2306 *
2307 *  Clears the I2C bus by sending nine clock pulses.
2308 *  Used when data line is stuck low.
2309 **/
2310static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2311{
2312	u32 i2cctl;
2313	u32 i;
2314
2315	ixgbe_i2c_start(hw);
2316	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2317
2318	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2319
2320	for (i = 0; i < 9; i++) {
2321		ixgbe_raise_i2c_clk(hw, &i2cctl);
2322
2323		/* Min high period of clock is 4us */
2324		udelay(IXGBE_I2C_T_HIGH);
2325
2326		ixgbe_lower_i2c_clk(hw, &i2cctl);
2327
2328		/* Min low period of clock is 4.7us*/
2329		udelay(IXGBE_I2C_T_LOW);
2330	}
2331
2332	ixgbe_i2c_start(hw);
2333
2334	/* Put the i2c bus back to default state */
2335	ixgbe_i2c_stop(hw);
2336}
2337
2338/**
2339 *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2340 *  @hw: pointer to hardware structure
2341 *
2342 *  Checks if the LASI temp alarm status was triggered due to overtemp
2343 **/
2344s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2345{
 
2346	u16 phy_data = 0;
2347
2348	if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2349		return 0;
2350
2351	/* Check that the LASI temp alarm status was triggered */
2352	hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2353			     MDIO_MMD_PMAPMD, &phy_data);
2354
2355	if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2356		return 0;
2357
2358	return IXGBE_ERR_OVERTEMP;
2359}
2360
2361/** ixgbe_set_copper_phy_power - Control power for copper phy
2362 *  @hw: pointer to hardware structure
2363 *  @on: true for on, false for off
2364 **/
2365s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2366{
2367	u32 status;
2368	u16 reg;
2369
2370	/* Bail if we don't have copper phy */
2371	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2372		return 0;
2373
2374	if (!on && ixgbe_mng_present(hw))
2375		return 0;
2376
2377	status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
2378	if (status)
2379		return status;
2380
2381	if (on) {
2382		reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2383	} else {
2384		if (ixgbe_check_reset_blocked(hw))
2385			return 0;
2386		reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2387	}
2388
2389	status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
 
2390	return status;
2391}