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1/*
2 * Performance events - AMD IBS
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
5 *
6 * For licencing details see kernel-base/COPYING
7 */
8
9#include <linux/perf_event.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/ptrace.h>
13
14#include <asm/apic.h>
15
16static u32 ibs_caps;
17
18#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
19
20#include <linux/kprobes.h>
21#include <linux/hardirq.h>
22
23#include <asm/nmi.h>
24
25#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
26#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
27
28enum ibs_states {
29 IBS_ENABLED = 0,
30 IBS_STARTED = 1,
31 IBS_STOPPING = 2,
32
33 IBS_MAX_STATES,
34};
35
36struct cpu_perf_ibs {
37 struct perf_event *event;
38 unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
39};
40
41struct perf_ibs {
42 struct pmu pmu;
43 unsigned int msr;
44 u64 config_mask;
45 u64 cnt_mask;
46 u64 enable_mask;
47 u64 valid_mask;
48 u64 max_period;
49 unsigned long offset_mask[1];
50 int offset_max;
51 struct cpu_perf_ibs __percpu *pcpu;
52 u64 (*get_count)(u64 config);
53};
54
55struct perf_ibs_data {
56 u32 size;
57 union {
58 u32 data[0]; /* data buffer starts here */
59 u32 caps;
60 };
61 u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
62};
63
64static int
65perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
66{
67 s64 left = local64_read(&hwc->period_left);
68 s64 period = hwc->sample_period;
69 int overflow = 0;
70
71 /*
72 * If we are way outside a reasonable range then just skip forward:
73 */
74 if (unlikely(left <= -period)) {
75 left = period;
76 local64_set(&hwc->period_left, left);
77 hwc->last_period = period;
78 overflow = 1;
79 }
80
81 if (unlikely(left < (s64)min)) {
82 left += period;
83 local64_set(&hwc->period_left, left);
84 hwc->last_period = period;
85 overflow = 1;
86 }
87
88 /*
89 * If the hw period that triggers the sw overflow is too short
90 * we might hit the irq handler. This biases the results.
91 * Thus we shorten the next-to-last period and set the last
92 * period to the max period.
93 */
94 if (left > max) {
95 left -= max;
96 if (left > max)
97 left = max;
98 else if (left < min)
99 left = min;
100 }
101
102 *hw_period = (u64)left;
103
104 return overflow;
105}
106
107static int
108perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
109{
110 struct hw_perf_event *hwc = &event->hw;
111 int shift = 64 - width;
112 u64 prev_raw_count;
113 u64 delta;
114
115 /*
116 * Careful: an NMI might modify the previous event value.
117 *
118 * Our tactic to handle this is to first atomically read and
119 * exchange a new raw count - then add that new-prev delta
120 * count to the generic event atomically:
121 */
122 prev_raw_count = local64_read(&hwc->prev_count);
123 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
124 new_raw_count) != prev_raw_count)
125 return 0;
126
127 /*
128 * Now we have the new raw value and have updated the prev
129 * timestamp already. We can now calculate the elapsed delta
130 * (event-)time and add that to the generic event.
131 *
132 * Careful, not all hw sign-extends above the physical width
133 * of the count.
134 */
135 delta = (new_raw_count << shift) - (prev_raw_count << shift);
136 delta >>= shift;
137
138 local64_add(delta, &event->count);
139 local64_sub(delta, &hwc->period_left);
140
141 return 1;
142}
143
144static struct perf_ibs perf_ibs_fetch;
145static struct perf_ibs perf_ibs_op;
146
147static struct perf_ibs *get_ibs_pmu(int type)
148{
149 if (perf_ibs_fetch.pmu.type == type)
150 return &perf_ibs_fetch;
151 if (perf_ibs_op.pmu.type == type)
152 return &perf_ibs_op;
153 return NULL;
154}
155
156/*
157 * Use IBS for precise event sampling:
158 *
159 * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count
160 * perf record -a -e r076:p ... # same as -e cpu-cycles:p
161 * perf record -a -e r0C1:p ... # use ibs op counting micro-ops
162 *
163 * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
164 * MSRC001_1033) is used to select either cycle or micro-ops counting
165 * mode.
166 *
167 * The rip of IBS samples has skid 0. Thus, IBS supports precise
168 * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
169 * rip is invalid when IBS was not able to record the rip correctly.
170 * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
171 *
172 */
173static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
174{
175 switch (event->attr.precise_ip) {
176 case 0:
177 return -ENOENT;
178 case 1:
179 case 2:
180 break;
181 default:
182 return -EOPNOTSUPP;
183 }
184
185 switch (event->attr.type) {
186 case PERF_TYPE_HARDWARE:
187 switch (event->attr.config) {
188 case PERF_COUNT_HW_CPU_CYCLES:
189 *config = 0;
190 return 0;
191 }
192 break;
193 case PERF_TYPE_RAW:
194 switch (event->attr.config) {
195 case 0x0076:
196 *config = 0;
197 return 0;
198 case 0x00C1:
199 *config = IBS_OP_CNT_CTL;
200 return 0;
201 }
202 break;
203 default:
204 return -ENOENT;
205 }
206
207 return -EOPNOTSUPP;
208}
209
210static const struct perf_event_attr ibs_notsupp = {
211 .exclude_user = 1,
212 .exclude_kernel = 1,
213 .exclude_hv = 1,
214 .exclude_idle = 1,
215 .exclude_host = 1,
216 .exclude_guest = 1,
217};
218
219static int perf_ibs_init(struct perf_event *event)
220{
221 struct hw_perf_event *hwc = &event->hw;
222 struct perf_ibs *perf_ibs;
223 u64 max_cnt, config;
224 int ret;
225
226 perf_ibs = get_ibs_pmu(event->attr.type);
227 if (perf_ibs) {
228 config = event->attr.config;
229 } else {
230 perf_ibs = &perf_ibs_op;
231 ret = perf_ibs_precise_event(event, &config);
232 if (ret)
233 return ret;
234 }
235
236 if (event->pmu != &perf_ibs->pmu)
237 return -ENOENT;
238
239 if (perf_flags(&event->attr) & perf_flags(&ibs_notsupp))
240 return -EINVAL;
241
242 if (config & ~perf_ibs->config_mask)
243 return -EINVAL;
244
245 if (hwc->sample_period) {
246 if (config & perf_ibs->cnt_mask)
247 /* raw max_cnt may not be set */
248 return -EINVAL;
249 if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
250 /*
251 * lower 4 bits can not be set in ibs max cnt,
252 * but allowing it in case we adjust the
253 * sample period to set a frequency.
254 */
255 return -EINVAL;
256 hwc->sample_period &= ~0x0FULL;
257 if (!hwc->sample_period)
258 hwc->sample_period = 0x10;
259 } else {
260 max_cnt = config & perf_ibs->cnt_mask;
261 config &= ~perf_ibs->cnt_mask;
262 event->attr.sample_period = max_cnt << 4;
263 hwc->sample_period = event->attr.sample_period;
264 }
265
266 if (!hwc->sample_period)
267 return -EINVAL;
268
269 /*
270 * If we modify hwc->sample_period, we also need to update
271 * hwc->last_period and hwc->period_left.
272 */
273 hwc->last_period = hwc->sample_period;
274 local64_set(&hwc->period_left, hwc->sample_period);
275
276 hwc->config_base = perf_ibs->msr;
277 hwc->config = config;
278
279 return 0;
280}
281
282static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
283 struct hw_perf_event *hwc, u64 *period)
284{
285 int overflow;
286
287 /* ignore lower 4 bits in min count: */
288 overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
289 local64_set(&hwc->prev_count, 0);
290
291 return overflow;
292}
293
294static u64 get_ibs_fetch_count(u64 config)
295{
296 return (config & IBS_FETCH_CNT) >> 12;
297}
298
299static u64 get_ibs_op_count(u64 config)
300{
301 u64 count = 0;
302
303 if (config & IBS_OP_VAL)
304 count += (config & IBS_OP_MAX_CNT) << 4; /* cnt rolled over */
305
306 if (ibs_caps & IBS_CAPS_RDWROPCNT)
307 count += (config & IBS_OP_CUR_CNT) >> 32;
308
309 return count;
310}
311
312static void
313perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
314 u64 *config)
315{
316 u64 count = perf_ibs->get_count(*config);
317
318 /*
319 * Set width to 64 since we do not overflow on max width but
320 * instead on max count. In perf_ibs_set_period() we clear
321 * prev count manually on overflow.
322 */
323 while (!perf_event_try_update(event, count, 64)) {
324 rdmsrl(event->hw.config_base, *config);
325 count = perf_ibs->get_count(*config);
326 }
327}
328
329static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
330 struct hw_perf_event *hwc, u64 config)
331{
332 wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);
333}
334
335/*
336 * Erratum #420 Instruction-Based Sampling Engine May Generate
337 * Interrupt that Cannot Be Cleared:
338 *
339 * Must clear counter mask first, then clear the enable bit. See
340 * Revision Guide for AMD Family 10h Processors, Publication #41322.
341 */
342static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
343 struct hw_perf_event *hwc, u64 config)
344{
345 config &= ~perf_ibs->cnt_mask;
346 wrmsrl(hwc->config_base, config);
347 config &= ~perf_ibs->enable_mask;
348 wrmsrl(hwc->config_base, config);
349}
350
351/*
352 * We cannot restore the ibs pmu state, so we always needs to update
353 * the event while stopping it and then reset the state when starting
354 * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
355 * perf_ibs_start()/perf_ibs_stop() and instead always do it.
356 */
357static void perf_ibs_start(struct perf_event *event, int flags)
358{
359 struct hw_perf_event *hwc = &event->hw;
360 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
361 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
362 u64 period;
363
364 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
365 return;
366
367 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
368 hwc->state = 0;
369
370 perf_ibs_set_period(perf_ibs, hwc, &period);
371 set_bit(IBS_STARTED, pcpu->state);
372 perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
373
374 perf_event_update_userpage(event);
375}
376
377static void perf_ibs_stop(struct perf_event *event, int flags)
378{
379 struct hw_perf_event *hwc = &event->hw;
380 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
381 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
382 u64 config;
383 int stopping;
384
385 stopping = test_and_clear_bit(IBS_STARTED, pcpu->state);
386
387 if (!stopping && (hwc->state & PERF_HES_UPTODATE))
388 return;
389
390 rdmsrl(hwc->config_base, config);
391
392 if (stopping) {
393 set_bit(IBS_STOPPING, pcpu->state);
394 perf_ibs_disable_event(perf_ibs, hwc, config);
395 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
396 hwc->state |= PERF_HES_STOPPED;
397 }
398
399 if (hwc->state & PERF_HES_UPTODATE)
400 return;
401
402 /*
403 * Clear valid bit to not count rollovers on update, rollovers
404 * are only updated in the irq handler.
405 */
406 config &= ~perf_ibs->valid_mask;
407
408 perf_ibs_event_update(perf_ibs, event, &config);
409 hwc->state |= PERF_HES_UPTODATE;
410}
411
412static int perf_ibs_add(struct perf_event *event, int flags)
413{
414 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
415 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
416
417 if (test_and_set_bit(IBS_ENABLED, pcpu->state))
418 return -ENOSPC;
419
420 event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
421
422 pcpu->event = event;
423
424 if (flags & PERF_EF_START)
425 perf_ibs_start(event, PERF_EF_RELOAD);
426
427 return 0;
428}
429
430static void perf_ibs_del(struct perf_event *event, int flags)
431{
432 struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
433 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
434
435 if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
436 return;
437
438 perf_ibs_stop(event, PERF_EF_UPDATE);
439
440 pcpu->event = NULL;
441
442 perf_event_update_userpage(event);
443}
444
445static void perf_ibs_read(struct perf_event *event) { }
446
447static struct perf_ibs perf_ibs_fetch = {
448 .pmu = {
449 .task_ctx_nr = perf_invalid_context,
450
451 .event_init = perf_ibs_init,
452 .add = perf_ibs_add,
453 .del = perf_ibs_del,
454 .start = perf_ibs_start,
455 .stop = perf_ibs_stop,
456 .read = perf_ibs_read,
457 },
458 .msr = MSR_AMD64_IBSFETCHCTL,
459 .config_mask = IBS_FETCH_CONFIG_MASK,
460 .cnt_mask = IBS_FETCH_MAX_CNT,
461 .enable_mask = IBS_FETCH_ENABLE,
462 .valid_mask = IBS_FETCH_VAL,
463 .max_period = IBS_FETCH_MAX_CNT << 4,
464 .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
465 .offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
466
467 .get_count = get_ibs_fetch_count,
468};
469
470static struct perf_ibs perf_ibs_op = {
471 .pmu = {
472 .task_ctx_nr = perf_invalid_context,
473
474 .event_init = perf_ibs_init,
475 .add = perf_ibs_add,
476 .del = perf_ibs_del,
477 .start = perf_ibs_start,
478 .stop = perf_ibs_stop,
479 .read = perf_ibs_read,
480 },
481 .msr = MSR_AMD64_IBSOPCTL,
482 .config_mask = IBS_OP_CONFIG_MASK,
483 .cnt_mask = IBS_OP_MAX_CNT,
484 .enable_mask = IBS_OP_ENABLE,
485 .valid_mask = IBS_OP_VAL,
486 .max_period = IBS_OP_MAX_CNT << 4,
487 .offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
488 .offset_max = MSR_AMD64_IBSOP_REG_COUNT,
489
490 .get_count = get_ibs_op_count,
491};
492
493static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
494{
495 struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
496 struct perf_event *event = pcpu->event;
497 struct hw_perf_event *hwc = &event->hw;
498 struct perf_sample_data data;
499 struct perf_raw_record raw;
500 struct pt_regs regs;
501 struct perf_ibs_data ibs_data;
502 int offset, size, check_rip, offset_max, throttle = 0;
503 unsigned int msr;
504 u64 *buf, *config, period;
505
506 if (!test_bit(IBS_STARTED, pcpu->state)) {
507 /*
508 * Catch spurious interrupts after stopping IBS: After
509 * disabling IBS there could be still incomming NMIs
510 * with samples that even have the valid bit cleared.
511 * Mark all this NMIs as handled.
512 */
513 return test_and_clear_bit(IBS_STOPPING, pcpu->state) ? 1 : 0;
514 }
515
516 msr = hwc->config_base;
517 buf = ibs_data.regs;
518 rdmsrl(msr, *buf);
519 if (!(*buf++ & perf_ibs->valid_mask))
520 return 0;
521
522 config = &ibs_data.regs[0];
523 perf_ibs_event_update(perf_ibs, event, config);
524 perf_sample_data_init(&data, 0, hwc->last_period);
525 if (!perf_ibs_set_period(perf_ibs, hwc, &period))
526 goto out; /* no sw counter overflow */
527
528 ibs_data.caps = ibs_caps;
529 size = 1;
530 offset = 1;
531 check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
532 if (event->attr.sample_type & PERF_SAMPLE_RAW)
533 offset_max = perf_ibs->offset_max;
534 else if (check_rip)
535 offset_max = 2;
536 else
537 offset_max = 1;
538 do {
539 rdmsrl(msr + offset, *buf++);
540 size++;
541 offset = find_next_bit(perf_ibs->offset_mask,
542 perf_ibs->offset_max,
543 offset + 1);
544 } while (offset < offset_max);
545 ibs_data.size = sizeof(u64) * size;
546
547 regs = *iregs;
548 if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
549 regs.flags &= ~PERF_EFLAGS_EXACT;
550 } else {
551 instruction_pointer_set(®s, ibs_data.regs[1]);
552 regs.flags |= PERF_EFLAGS_EXACT;
553 }
554
555 if (event->attr.sample_type & PERF_SAMPLE_RAW) {
556 raw.size = sizeof(u32) + ibs_data.size;
557 raw.data = ibs_data.data;
558 data.raw = &raw;
559 }
560
561 throttle = perf_event_overflow(event, &data, ®s);
562out:
563 if (throttle)
564 perf_ibs_disable_event(perf_ibs, hwc, *config);
565 else
566 perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
567
568 perf_event_update_userpage(event);
569
570 return 1;
571}
572
573static int __kprobes
574perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
575{
576 int handled = 0;
577
578 handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
579 handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
580
581 if (handled)
582 inc_irq_stat(apic_perf_irqs);
583
584 return handled;
585}
586
587static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
588{
589 struct cpu_perf_ibs __percpu *pcpu;
590 int ret;
591
592 pcpu = alloc_percpu(struct cpu_perf_ibs);
593 if (!pcpu)
594 return -ENOMEM;
595
596 perf_ibs->pcpu = pcpu;
597
598 ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
599 if (ret) {
600 perf_ibs->pcpu = NULL;
601 free_percpu(pcpu);
602 }
603
604 return ret;
605}
606
607static __init int perf_event_ibs_init(void)
608{
609 if (!ibs_caps)
610 return -ENODEV; /* ibs not supported by the cpu */
611
612 perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
613 if (ibs_caps & IBS_CAPS_OPCNT)
614 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
615 perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
616 register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
617 printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
618
619 return 0;
620}
621
622#else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
623
624static __init int perf_event_ibs_init(void) { return 0; }
625
626#endif
627
628/* IBS - apic initialization, for perf and oprofile */
629
630static __init u32 __get_ibs_caps(void)
631{
632 u32 caps;
633 unsigned int max_level;
634
635 if (!boot_cpu_has(X86_FEATURE_IBS))
636 return 0;
637
638 /* check IBS cpuid feature flags */
639 max_level = cpuid_eax(0x80000000);
640 if (max_level < IBS_CPUID_FEATURES)
641 return IBS_CAPS_DEFAULT;
642
643 caps = cpuid_eax(IBS_CPUID_FEATURES);
644 if (!(caps & IBS_CAPS_AVAIL))
645 /* cpuid flags not valid */
646 return IBS_CAPS_DEFAULT;
647
648 return caps;
649}
650
651u32 get_ibs_caps(void)
652{
653 return ibs_caps;
654}
655
656EXPORT_SYMBOL(get_ibs_caps);
657
658static inline int get_eilvt(int offset)
659{
660 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
661}
662
663static inline int put_eilvt(int offset)
664{
665 return !setup_APIC_eilvt(offset, 0, 0, 1);
666}
667
668/*
669 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
670 */
671static inline int ibs_eilvt_valid(void)
672{
673 int offset;
674 u64 val;
675 int valid = 0;
676
677 preempt_disable();
678
679 rdmsrl(MSR_AMD64_IBSCTL, val);
680 offset = val & IBSCTL_LVT_OFFSET_MASK;
681
682 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
683 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
684 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
685 goto out;
686 }
687
688 if (!get_eilvt(offset)) {
689 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
690 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
691 goto out;
692 }
693
694 valid = 1;
695out:
696 preempt_enable();
697
698 return valid;
699}
700
701static int setup_ibs_ctl(int ibs_eilvt_off)
702{
703 struct pci_dev *cpu_cfg;
704 int nodes;
705 u32 value = 0;
706
707 nodes = 0;
708 cpu_cfg = NULL;
709 do {
710 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
711 PCI_DEVICE_ID_AMD_10H_NB_MISC,
712 cpu_cfg);
713 if (!cpu_cfg)
714 break;
715 ++nodes;
716 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
717 | IBSCTL_LVT_OFFSET_VALID);
718 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
719 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
720 pci_dev_put(cpu_cfg);
721 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
722 "IBSCTL = 0x%08x\n", value);
723 return -EINVAL;
724 }
725 } while (1);
726
727 if (!nodes) {
728 printk(KERN_DEBUG "No CPU node configured for IBS\n");
729 return -ENODEV;
730 }
731
732 return 0;
733}
734
735/*
736 * This runs only on the current cpu. We try to find an LVT offset and
737 * setup the local APIC. For this we must disable preemption. On
738 * success we initialize all nodes with this offset. This updates then
739 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
740 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
741 * is using the new offset.
742 */
743static int force_ibs_eilvt_setup(void)
744{
745 int offset;
746 int ret;
747
748 preempt_disable();
749 /* find the next free available EILVT entry, skip offset 0 */
750 for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
751 if (get_eilvt(offset))
752 break;
753 }
754 preempt_enable();
755
756 if (offset == APIC_EILVT_NR_MAX) {
757 printk(KERN_DEBUG "No EILVT entry available\n");
758 return -EBUSY;
759 }
760
761 ret = setup_ibs_ctl(offset);
762 if (ret)
763 goto out;
764
765 if (!ibs_eilvt_valid()) {
766 ret = -EFAULT;
767 goto out;
768 }
769
770 pr_info("IBS: LVT offset %d assigned\n", offset);
771
772 return 0;
773out:
774 preempt_disable();
775 put_eilvt(offset);
776 preempt_enable();
777 return ret;
778}
779
780static inline int get_ibs_lvt_offset(void)
781{
782 u64 val;
783
784 rdmsrl(MSR_AMD64_IBSCTL, val);
785 if (!(val & IBSCTL_LVT_OFFSET_VALID))
786 return -EINVAL;
787
788 return val & IBSCTL_LVT_OFFSET_MASK;
789}
790
791static void setup_APIC_ibs(void *dummy)
792{
793 int offset;
794
795 offset = get_ibs_lvt_offset();
796 if (offset < 0)
797 goto failed;
798
799 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
800 return;
801failed:
802 pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
803 smp_processor_id());
804}
805
806static void clear_APIC_ibs(void *dummy)
807{
808 int offset;
809
810 offset = get_ibs_lvt_offset();
811 if (offset >= 0)
812 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
813}
814
815static int __cpuinit
816perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
817{
818 switch (action & ~CPU_TASKS_FROZEN) {
819 case CPU_STARTING:
820 setup_APIC_ibs(NULL);
821 break;
822 case CPU_DYING:
823 clear_APIC_ibs(NULL);
824 break;
825 default:
826 break;
827 }
828
829 return NOTIFY_OK;
830}
831
832static __init int amd_ibs_init(void)
833{
834 u32 caps;
835 int ret = -EINVAL;
836
837 caps = __get_ibs_caps();
838 if (!caps)
839 return -ENODEV; /* ibs not supported by the cpu */
840
841 /*
842 * Force LVT offset assignment for family 10h: The offsets are
843 * not assigned by the BIOS for this family, so the OS is
844 * responsible for doing it. If the OS assignment fails, fall
845 * back to BIOS settings and try to setup this.
846 */
847 if (boot_cpu_data.x86 == 0x10)
848 force_ibs_eilvt_setup();
849
850 if (!ibs_eilvt_valid())
851 goto out;
852
853 get_online_cpus();
854 ibs_caps = caps;
855 /* make ibs_caps visible to other cpus: */
856 smp_mb();
857 perf_cpu_notifier(perf_ibs_cpu_notifier);
858 smp_call_function(setup_APIC_ibs, NULL, 1);
859 put_online_cpus();
860
861 ret = perf_event_ibs_init();
862out:
863 if (ret)
864 pr_err("Failed to setup IBS, %d\n", ret);
865 return ret;
866}
867
868/* Since we need the pci subsystem to init ibs we can't do this earlier: */
869device_initcall(amd_ibs_init);