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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9 */
10#include <linux/cpumask.h>
11#include <linux/hardirq.h>
12#include <linux/proc_fs.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/export.h>
16#include <linux/string.h>
17#include <linux/ctype.h>
18#include <linux/sched.h>
19#include <linux/timer.h>
20#include <linux/slab.h>
21#include <linux/cpu.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/pci.h>
25#include <linux/kdebug.h>
26#include <linux/delay.h>
27#include <linux/crash_dump.h>
28#include <linux/reboot.h>
29
30#include <asm/uv/uv_mmrs.h>
31#include <asm/uv/uv_hub.h>
32#include <asm/current.h>
33#include <asm/pgtable.h>
34#include <asm/uv/bios.h>
35#include <asm/uv/uv.h>
36#include <asm/apic.h>
37#include <asm/e820/api.h>
38#include <asm/ipi.h>
39#include <asm/smp.h>
40#include <asm/x86_init.h>
41#include <asm/nmi.h>
42
43DEFINE_PER_CPU(int, x2apic_extra_bits);
44
45static enum uv_system_type uv_system_type;
46static bool uv_hubless_system;
47static u64 gru_start_paddr, gru_end_paddr;
48static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49static u64 gru_dist_lmask, gru_dist_umask;
50static union uvh_apicid uvh_apicid;
51
52/* Information derived from CPUID: */
53static struct {
54 unsigned int apicid_shift;
55 unsigned int apicid_mask;
56 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
57 unsigned int pnode_mask;
58 unsigned int gpa_shift;
59 unsigned int gnode_shift;
60} uv_cpuid;
61
62int uv_min_hub_revision_id;
63EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
64
65unsigned int uv_apicid_hibits;
66EXPORT_SYMBOL_GPL(uv_apicid_hibits);
67
68static struct apic apic_x2apic_uv_x;
69static struct uv_hub_info_s uv_hub_info_node0;
70
71/* Set this to use hardware error handler instead of kernel panic: */
72static int disable_uv_undefined_panic = 1;
73
74unsigned long uv_undefined(char *str)
75{
76 if (likely(!disable_uv_undefined_panic))
77 panic("UV: error: undefined MMR: %s\n", str);
78 else
79 pr_crit("UV: error: undefined MMR: %s\n", str);
80
81 /* Cause a machine fault: */
82 return ~0ul;
83}
84EXPORT_SYMBOL(uv_undefined);
85
86static unsigned long __init uv_early_read_mmr(unsigned long addr)
87{
88 unsigned long val, *mmr;
89
90 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
91 val = *mmr;
92 early_iounmap(mmr, sizeof(*mmr));
93
94 return val;
95}
96
97static inline bool is_GRU_range(u64 start, u64 end)
98{
99 if (gru_dist_base) {
100 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */
101 u64 sl = start & gru_dist_lmask; /* Base offset bits */
102 u64 eu = end & gru_dist_umask;
103 u64 el = end & gru_dist_lmask;
104
105 /* Must reside completely within a single GRU range: */
106 return (sl == gru_dist_base && el == gru_dist_base &&
107 su >= gru_first_node_paddr &&
108 su <= gru_last_node_paddr &&
109 eu == su);
110 } else {
111 return start >= gru_start_paddr && end <= gru_end_paddr;
112 }
113}
114
115static bool uv_is_untracked_pat_range(u64 start, u64 end)
116{
117 return is_ISA_range(start, end) || is_GRU_range(start, end);
118}
119
120static int __init early_get_pnodeid(void)
121{
122 union uvh_node_id_u node_id;
123 union uvh_rh_gam_config_mmr_u m_n_config;
124 int pnode;
125
126 /* Currently, all blades have same revision number */
127 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
128 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
129 uv_min_hub_revision_id = node_id.s.revision;
130
131 switch (node_id.s.part_number) {
132 case UV2_HUB_PART_NUMBER:
133 case UV2_HUB_PART_NUMBER_X:
134 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
135 break;
136 case UV3_HUB_PART_NUMBER:
137 case UV3_HUB_PART_NUMBER_X:
138 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
139 break;
140
141 /* Update: UV4A has only a modified revision to indicate HUB fixes */
142 case UV4_HUB_PART_NUMBER:
143 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
144 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
145 break;
146 }
147
148 uv_hub_info->hub_revision = uv_min_hub_revision_id;
149 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
150 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
151 uv_cpuid.gpa_shift = 46; /* Default unless changed */
152
153 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
154 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
155 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
156 return pnode;
157}
158
159static void __init uv_tsc_check_sync(void)
160{
161 u64 mmr;
162 int sync_state;
163 int mmr_shift;
164 char *state;
165 bool valid;
166
167 /* Accommodate different UV arch BIOSes */
168 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
169 mmr_shift =
170 is_uv1_hub() ? 0 :
171 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
172 if (mmr_shift)
173 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
174 else
175 sync_state = 0;
176
177 switch (sync_state) {
178 case UVH_TSC_SYNC_VALID:
179 state = "in sync";
180 valid = true;
181 break;
182
183 case UVH_TSC_SYNC_INVALID:
184 state = "unstable";
185 valid = false;
186 break;
187 default:
188 state = "unknown: assuming valid";
189 valid = true;
190 break;
191 }
192 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
193
194 /* Mark flag that says TSC != 0 is valid for socket 0 */
195 if (valid)
196 mark_tsc_async_resets("UV BIOS");
197 else
198 mark_tsc_unstable("UV BIOS");
199}
200
201/* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
202
203#define SMT_LEVEL 0 /* Leaf 0xb SMT level */
204#define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
205#define SMT_TYPE 1
206#define CORE_TYPE 2
207#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
208#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
209
210static void set_x2apic_bits(void)
211{
212 unsigned int eax, ebx, ecx, edx, sub_index;
213 unsigned int sid_shift;
214
215 cpuid(0, &eax, &ebx, &ecx, &edx);
216 if (eax < 0xb) {
217 pr_info("UV: CPU does not have CPUID.11\n");
218 return;
219 }
220
221 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
222 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
223 pr_info("UV: CPUID.11 not implemented\n");
224 return;
225 }
226
227 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
228 sub_index = 1;
229 do {
230 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
231 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
232 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
233 break;
234 }
235 sub_index++;
236 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
237
238 uv_cpuid.apicid_shift = 0;
239 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
240 uv_cpuid.socketid_shift = sid_shift;
241}
242
243static void __init early_get_apic_socketid_shift(void)
244{
245 if (is_uv2_hub() || is_uv3_hub())
246 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
247
248 set_x2apic_bits();
249
250 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
251 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
252}
253
254/*
255 * Add an extra bit as dictated by bios to the destination apicid of
256 * interrupts potentially passing through the UV HUB. This prevents
257 * a deadlock between interrupts and IO port operations.
258 */
259static void __init uv_set_apicid_hibit(void)
260{
261 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
262
263 if (is_uv1_hub()) {
264 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
265 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
266 }
267}
268
269static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
270{
271 int pnodeid;
272 int uv_apic;
273
274 if (strncmp(oem_id, "SGI", 3) != 0) {
275 if (strncmp(oem_id, "NSGI", 4) == 0) {
276 uv_hubless_system = true;
277 pr_info("UV: OEM IDs %s/%s, HUBLESS\n",
278 oem_id, oem_table_id);
279 }
280 return 0;
281 }
282
283 if (numa_off) {
284 pr_err("UV: NUMA is off, disabling UV support\n");
285 return 0;
286 }
287
288 /* Set up early hub type field in uv_hub_info for Node 0 */
289 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
290
291 /*
292 * Determine UV arch type.
293 * SGI: UV100/1000
294 * SGI2: UV2000/3000
295 * SGI3: UV300 (truncated to 4 chars because of different varieties)
296 * SGI4: UV400 (truncated to 4 chars because of different varieties)
297 */
298 uv_hub_info->hub_revision =
299 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
300 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
301 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
302 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
303
304 if (uv_hub_info->hub_revision == 0)
305 goto badbios;
306
307 pnodeid = early_get_pnodeid();
308 early_get_apic_socketid_shift();
309
310 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
311 x86_platform.nmi_init = uv_nmi_init;
312
313 if (!strcmp(oem_table_id, "UVX")) {
314 /* This is the most common hardware variant: */
315 uv_system_type = UV_X2APIC;
316 uv_apic = 0;
317
318 } else if (!strcmp(oem_table_id, "UVH")) {
319 /* Only UV1 systems: */
320 uv_system_type = UV_NON_UNIQUE_APIC;
321 x86_platform.legacy.warm_reset = 0;
322 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
323 uv_set_apicid_hibit();
324 uv_apic = 1;
325
326 } else if (!strcmp(oem_table_id, "UVL")) {
327 /* Only used for very small systems: */
328 uv_system_type = UV_LEGACY_APIC;
329 uv_apic = 0;
330
331 } else {
332 goto badbios;
333 }
334
335 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
336 uv_tsc_check_sync();
337
338 return uv_apic;
339
340badbios:
341 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
342 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
343 BUG();
344}
345
346enum uv_system_type get_uv_system_type(void)
347{
348 return uv_system_type;
349}
350
351int is_uv_system(void)
352{
353 return uv_system_type != UV_NONE;
354}
355EXPORT_SYMBOL_GPL(is_uv_system);
356
357int is_uv_hubless(void)
358{
359 return uv_hubless_system;
360}
361EXPORT_SYMBOL_GPL(is_uv_hubless);
362
363void **__uv_hub_info_list;
364EXPORT_SYMBOL_GPL(__uv_hub_info_list);
365
366DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
367EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
368
369short uv_possible_blades;
370EXPORT_SYMBOL_GPL(uv_possible_blades);
371
372unsigned long sn_rtc_cycles_per_second;
373EXPORT_SYMBOL(sn_rtc_cycles_per_second);
374
375/* The following values are used for the per node hub info struct */
376static __initdata unsigned short *_node_to_pnode;
377static __initdata unsigned short _min_socket, _max_socket;
378static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
379static __initdata struct uv_gam_range_entry *uv_gre_table;
380static __initdata struct uv_gam_parameters *uv_gp_table;
381static __initdata unsigned short *_socket_to_node;
382static __initdata unsigned short *_socket_to_pnode;
383static __initdata unsigned short *_pnode_to_socket;
384
385static __initdata struct uv_gam_range_s *_gr_table;
386
387#define SOCK_EMPTY ((unsigned short)~0)
388
389extern int uv_hub_info_version(void)
390{
391 return UV_HUB_INFO_VERSION;
392}
393EXPORT_SYMBOL(uv_hub_info_version);
394
395/* Build GAM range lookup table: */
396static __init void build_uv_gr_table(void)
397{
398 struct uv_gam_range_entry *gre = uv_gre_table;
399 struct uv_gam_range_s *grt;
400 unsigned long last_limit = 0, ram_limit = 0;
401 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
402
403 if (!gre)
404 return;
405
406 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
407 grt = kzalloc(bytes, GFP_KERNEL);
408 BUG_ON(!grt);
409 _gr_table = grt;
410
411 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
412 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
413 if (!ram_limit) {
414 /* Mark hole between RAM/non-RAM: */
415 ram_limit = last_limit;
416 last_limit = gre->limit;
417 lsid++;
418 continue;
419 }
420 last_limit = gre->limit;
421 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
422 continue;
423 }
424 if (_max_socket < gre->sockid) {
425 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
426 continue;
427 }
428 sid = gre->sockid - _min_socket;
429 if (lsid < sid) {
430 /* New range: */
431 grt = &_gr_table[indx];
432 grt->base = lindx;
433 grt->nasid = gre->nasid;
434 grt->limit = last_limit = gre->limit;
435 lsid = sid;
436 lindx = indx++;
437 continue;
438 }
439 /* Update range: */
440 if (lsid == sid && !ram_limit) {
441 /* .. if contiguous: */
442 if (grt->limit == last_limit) {
443 grt->limit = last_limit = gre->limit;
444 continue;
445 }
446 }
447 /* Non-contiguous RAM range: */
448 if (!ram_limit) {
449 grt++;
450 grt->base = lindx;
451 grt->nasid = gre->nasid;
452 grt->limit = last_limit = gre->limit;
453 continue;
454 }
455 /* Non-contiguous/non-RAM: */
456 grt++;
457 /* base is this entry */
458 grt->base = grt - _gr_table;
459 grt->nasid = gre->nasid;
460 grt->limit = last_limit = gre->limit;
461 lsid++;
462 }
463
464 /* Shorten table if possible */
465 grt++;
466 i = grt - _gr_table;
467 if (i < _gr_table_len) {
468 void *ret;
469
470 bytes = i * sizeof(struct uv_gam_range_s);
471 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
472 if (ret) {
473 _gr_table = ret;
474 _gr_table_len = i;
475 }
476 }
477
478 /* Display resultant GAM range table: */
479 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
480 unsigned long start, end;
481 int gb = grt->base;
482
483 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
484 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
485
486 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
487 }
488}
489
490static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
491{
492 unsigned long val;
493 int pnode;
494
495 pnode = uv_apicid_to_pnode(phys_apicid);
496 phys_apicid |= uv_apicid_hibits;
497
498 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
499 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
500 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
501 APIC_DM_INIT;
502
503 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
504
505 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
506 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
507 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
508 APIC_DM_STARTUP;
509
510 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
511
512 return 0;
513}
514
515static void uv_send_IPI_one(int cpu, int vector)
516{
517 unsigned long apicid;
518 int pnode;
519
520 apicid = per_cpu(x86_cpu_to_apicid, cpu);
521 pnode = uv_apicid_to_pnode(apicid);
522 uv_hub_send_ipi(pnode, apicid, vector);
523}
524
525static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
526{
527 unsigned int cpu;
528
529 for_each_cpu(cpu, mask)
530 uv_send_IPI_one(cpu, vector);
531}
532
533static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
534{
535 unsigned int this_cpu = smp_processor_id();
536 unsigned int cpu;
537
538 for_each_cpu(cpu, mask) {
539 if (cpu != this_cpu)
540 uv_send_IPI_one(cpu, vector);
541 }
542}
543
544static void uv_send_IPI_allbutself(int vector)
545{
546 unsigned int this_cpu = smp_processor_id();
547 unsigned int cpu;
548
549 for_each_online_cpu(cpu) {
550 if (cpu != this_cpu)
551 uv_send_IPI_one(cpu, vector);
552 }
553}
554
555static void uv_send_IPI_all(int vector)
556{
557 uv_send_IPI_mask(cpu_online_mask, vector);
558}
559
560static int uv_apic_id_valid(u32 apicid)
561{
562 return 1;
563}
564
565static int uv_apic_id_registered(void)
566{
567 return 1;
568}
569
570static void uv_init_apic_ldr(void)
571{
572}
573
574static u32 apic_uv_calc_apicid(unsigned int cpu)
575{
576 return apic_default_calc_apicid(cpu) | uv_apicid_hibits;
577}
578
579static unsigned int x2apic_get_apic_id(unsigned long x)
580{
581 unsigned int id;
582
583 WARN_ON(preemptible() && num_online_cpus() > 1);
584 id = x | __this_cpu_read(x2apic_extra_bits);
585
586 return id;
587}
588
589static u32 set_apic_id(unsigned int id)
590{
591 /* CHECKME: Do we need to mask out the xapic extra bits? */
592 return id;
593}
594
595static unsigned int uv_read_apic_id(void)
596{
597 return x2apic_get_apic_id(apic_read(APIC_ID));
598}
599
600static int uv_phys_pkg_id(int initial_apicid, int index_msb)
601{
602 return uv_read_apic_id() >> index_msb;
603}
604
605static void uv_send_IPI_self(int vector)
606{
607 apic_write(APIC_SELF_IPI, vector);
608}
609
610static int uv_probe(void)
611{
612 return apic == &apic_x2apic_uv_x;
613}
614
615static struct apic apic_x2apic_uv_x __ro_after_init = {
616
617 .name = "UV large system",
618 .probe = uv_probe,
619 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
620 .apic_id_valid = uv_apic_id_valid,
621 .apic_id_registered = uv_apic_id_registered,
622
623 .irq_delivery_mode = dest_Fixed,
624 .irq_dest_mode = 0, /* Physical */
625
626 .disable_esr = 0,
627 .dest_logical = APIC_DEST_LOGICAL,
628 .check_apicid_used = NULL,
629
630 .init_apic_ldr = uv_init_apic_ldr,
631
632 .ioapic_phys_id_map = NULL,
633 .setup_apic_routing = NULL,
634 .cpu_present_to_apicid = default_cpu_present_to_apicid,
635 .apicid_to_cpu_present = NULL,
636 .check_phys_apicid_present = default_check_phys_apicid_present,
637 .phys_pkg_id = uv_phys_pkg_id,
638
639 .get_apic_id = x2apic_get_apic_id,
640 .set_apic_id = set_apic_id,
641
642 .calc_dest_apicid = apic_uv_calc_apicid,
643
644 .send_IPI = uv_send_IPI_one,
645 .send_IPI_mask = uv_send_IPI_mask,
646 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
647 .send_IPI_allbutself = uv_send_IPI_allbutself,
648 .send_IPI_all = uv_send_IPI_all,
649 .send_IPI_self = uv_send_IPI_self,
650
651 .wakeup_secondary_cpu = uv_wakeup_secondary,
652 .inquire_remote_apic = NULL,
653
654 .read = native_apic_msr_read,
655 .write = native_apic_msr_write,
656 .eoi_write = native_apic_msr_eoi_write,
657 .icr_read = native_x2apic_icr_read,
658 .icr_write = native_x2apic_icr_write,
659 .wait_icr_idle = native_x2apic_wait_icr_idle,
660 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
661};
662
663static void set_x2apic_extra_bits(int pnode)
664{
665 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
666}
667
668#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
669#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
670
671static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
672{
673 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
674 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
675 unsigned long m_redirect;
676 unsigned long m_overlay;
677 int i;
678
679 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
680 switch (i) {
681 case 0:
682 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
683 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
684 break;
685 case 1:
686 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
687 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
688 break;
689 case 2:
690 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
691 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
692 break;
693 }
694 alias.v = uv_read_local_mmr(m_overlay);
695 if (alias.s.enable && alias.s.base == 0) {
696 *size = (1UL << alias.s.m_alias);
697 redirect.v = uv_read_local_mmr(m_redirect);
698 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
699 return;
700 }
701 }
702 *base = *size = 0;
703}
704
705enum map_type {map_wb, map_uc};
706
707static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
708{
709 unsigned long bytes, paddr;
710
711 paddr = base << pshift;
712 bytes = (1UL << bshift) * (max_pnode + 1);
713 if (!paddr) {
714 pr_info("UV: Map %s_HI base address NULL\n", id);
715 return;
716 }
717 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
718 if (map_type == map_uc)
719 init_extra_mapping_uc(paddr, bytes);
720 else
721 init_extra_mapping_wb(paddr, bytes);
722}
723
724static __init void map_gru_distributed(unsigned long c)
725{
726 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
727 u64 paddr;
728 unsigned long bytes;
729 int nid;
730
731 gru.v = c;
732
733 /* Only base bits 42:28 relevant in dist mode */
734 gru_dist_base = gru.v & 0x000007fff0000000UL;
735 if (!gru_dist_base) {
736 pr_info("UV: Map GRU_DIST base address NULL\n");
737 return;
738 }
739
740 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
741 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
742 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
743 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
744
745 for_each_online_node(nid) {
746 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
747 gru_dist_base;
748 init_extra_mapping_wb(paddr, bytes);
749 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
750 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
751 }
752
753 /* Save upper (63:M) bits of address only for is_GRU_range */
754 gru_first_node_paddr &= gru_dist_umask;
755 gru_last_node_paddr &= gru_dist_umask;
756
757 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
758}
759
760static __init void map_gru_high(int max_pnode)
761{
762 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
763 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
764 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
765 unsigned long base;
766
767 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
768 if (!gru.s.enable) {
769 pr_info("UV: GRU disabled\n");
770 return;
771 }
772
773 /* Only UV3 has distributed GRU mode */
774 if (is_uv3_hub() && gru.s3.mode) {
775 map_gru_distributed(gru.v);
776 return;
777 }
778
779 base = (gru.v & mask) >> shift;
780 map_high("GRU", base, shift, shift, max_pnode, map_wb);
781 gru_start_paddr = ((u64)base << shift);
782 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
783}
784
785static __init void map_mmr_high(int max_pnode)
786{
787 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
788 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
789
790 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
791 if (mmr.s.enable)
792 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
793 else
794 pr_info("UV: MMR disabled\n");
795}
796
797/* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
798static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
799{
800 unsigned long overlay;
801 unsigned long mmr;
802 unsigned long base;
803 unsigned long nasid_mask;
804 unsigned long m_overlay;
805 int i, n, shift, m_io, max_io;
806 int nasid, lnasid, fi, li;
807 char *id;
808
809 if (index == 0) {
810 id = "MMIOH0";
811 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
812 overlay = uv_read_local_mmr(m_overlay);
813 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
814 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
815 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
816 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
817 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
818 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
819 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
820 } else {
821 id = "MMIOH1";
822 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
823 overlay = uv_read_local_mmr(m_overlay);
824 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
825 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
826 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
827 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
828 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
829 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
830 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
831 }
832 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
833 if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
834 pr_info("UV: %s disabled\n", id);
835 return;
836 }
837
838 /* Convert to NASID: */
839 min_pnode *= 2;
840 max_pnode *= 2;
841 max_io = lnasid = fi = li = -1;
842
843 for (i = 0; i < n; i++) {
844 unsigned long m_redirect = mmr + i * 8;
845 unsigned long redirect = uv_read_local_mmr(m_redirect);
846
847 nasid = redirect & nasid_mask;
848 if (i == 0)
849 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
850 id, redirect, m_redirect, nasid);
851
852 /* Invalid NASID: */
853 if (nasid < min_pnode || max_pnode < nasid)
854 nasid = -1;
855
856 if (nasid == lnasid) {
857 li = i;
858 /* Last entry check: */
859 if (i != n-1)
860 continue;
861 }
862
863 /* Check if we have a cached (or last) redirect to print: */
864 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
865 unsigned long addr1, addr2;
866 int f, l;
867
868 if (lnasid == -1) {
869 f = l = i;
870 lnasid = nasid;
871 } else {
872 f = fi;
873 l = li;
874 }
875 addr1 = (base << shift) + f * (1ULL << m_io);
876 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
877 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
878 if (max_io < l)
879 max_io = l;
880 }
881 fi = li = i;
882 lnasid = nasid;
883 }
884
885 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
886
887 if (max_io >= 0)
888 map_high(id, base, shift, m_io, max_io, map_uc);
889}
890
891static __init void map_mmioh_high(int min_pnode, int max_pnode)
892{
893 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
894 unsigned long mmr, base;
895 int shift, enable, m_io, n_io;
896
897 if (is_uv3_hub() || is_uv4_hub()) {
898 /* Map both MMIOH regions: */
899 map_mmioh_high_uv34(0, min_pnode, max_pnode);
900 map_mmioh_high_uv34(1, min_pnode, max_pnode);
901 return;
902 }
903
904 if (is_uv1_hub()) {
905 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
906 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
907 mmioh.v = uv_read_local_mmr(mmr);
908 enable = !!mmioh.s1.enable;
909 base = mmioh.s1.base;
910 m_io = mmioh.s1.m_io;
911 n_io = mmioh.s1.n_io;
912 } else if (is_uv2_hub()) {
913 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
914 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
915 mmioh.v = uv_read_local_mmr(mmr);
916 enable = !!mmioh.s2.enable;
917 base = mmioh.s2.base;
918 m_io = mmioh.s2.m_io;
919 n_io = mmioh.s2.n_io;
920 } else {
921 return;
922 }
923
924 if (enable) {
925 max_pnode &= (1 << n_io) - 1;
926 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
927 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
928 } else {
929 pr_info("UV: MMIOH disabled\n");
930 }
931}
932
933static __init void map_low_mmrs(void)
934{
935 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
936 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
937}
938
939static __init void uv_rtc_init(void)
940{
941 long status;
942 u64 ticks_per_sec;
943
944 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
945
946 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
947 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
948
949 /* BIOS gives wrong value for clock frequency, so guess: */
950 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
951 } else {
952 sn_rtc_cycles_per_second = ticks_per_sec;
953 }
954}
955
956/*
957 * percpu heartbeat timer
958 */
959static void uv_heartbeat(struct timer_list *timer)
960{
961 unsigned char bits = uv_scir_info->state;
962
963 /* Flip heartbeat bit: */
964 bits ^= SCIR_CPU_HEARTBEAT;
965
966 /* Is this CPU idle? */
967 if (idle_cpu(raw_smp_processor_id()))
968 bits &= ~SCIR_CPU_ACTIVITY;
969 else
970 bits |= SCIR_CPU_ACTIVITY;
971
972 /* Update system controller interface reg: */
973 uv_set_scir_bits(bits);
974
975 /* Enable next timer period: */
976 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
977}
978
979static int uv_heartbeat_enable(unsigned int cpu)
980{
981 while (!uv_cpu_scir_info(cpu)->enabled) {
982 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
983
984 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
985 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
986 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
987 add_timer_on(timer, cpu);
988 uv_cpu_scir_info(cpu)->enabled = 1;
989
990 /* Also ensure that boot CPU is enabled: */
991 cpu = 0;
992 }
993 return 0;
994}
995
996#ifdef CONFIG_HOTPLUG_CPU
997static int uv_heartbeat_disable(unsigned int cpu)
998{
999 if (uv_cpu_scir_info(cpu)->enabled) {
1000 uv_cpu_scir_info(cpu)->enabled = 0;
1001 del_timer(&uv_cpu_scir_info(cpu)->timer);
1002 }
1003 uv_set_cpu_scir_bits(cpu, 0xff);
1004 return 0;
1005}
1006
1007static __init void uv_scir_register_cpu_notifier(void)
1008{
1009 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
1010 uv_heartbeat_enable, uv_heartbeat_disable);
1011}
1012
1013#else /* !CONFIG_HOTPLUG_CPU */
1014
1015static __init void uv_scir_register_cpu_notifier(void)
1016{
1017}
1018
1019static __init int uv_init_heartbeat(void)
1020{
1021 int cpu;
1022
1023 if (is_uv_system()) {
1024 for_each_online_cpu(cpu)
1025 uv_heartbeat_enable(cpu);
1026 }
1027
1028 return 0;
1029}
1030
1031late_initcall(uv_init_heartbeat);
1032
1033#endif /* !CONFIG_HOTPLUG_CPU */
1034
1035/* Direct Legacy VGA I/O traffic to designated IOH */
1036int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1037{
1038 int domain, bus, rc;
1039
1040 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1041 return 0;
1042
1043 if ((command_bits & PCI_COMMAND_IO) == 0)
1044 return 0;
1045
1046 domain = pci_domain_nr(pdev->bus);
1047 bus = pdev->bus->number;
1048
1049 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1050
1051 return rc;
1052}
1053
1054/*
1055 * Called on each CPU to initialize the per_cpu UV data area.
1056 * FIXME: hotplug not supported yet
1057 */
1058void uv_cpu_init(void)
1059{
1060 /* CPU 0 initialization will be done via uv_system_init. */
1061 if (smp_processor_id() == 0)
1062 return;
1063
1064 uv_hub_info->nr_online_cpus++;
1065
1066 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1067 set_x2apic_extra_bits(uv_hub_info->pnode);
1068}
1069
1070struct mn {
1071 unsigned char m_val;
1072 unsigned char n_val;
1073 unsigned char m_shift;
1074 unsigned char n_lshift;
1075};
1076
1077static void get_mn(struct mn *mnp)
1078{
1079 union uvh_rh_gam_config_mmr_u m_n_config;
1080 union uv3h_gr0_gam_gr_config_u m_gr_config;
1081
1082 /* Make sure the whole structure is well initialized: */
1083 memset(mnp, 0, sizeof(*mnp));
1084
1085 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1086 mnp->n_val = m_n_config.s.n_skt;
1087
1088 if (is_uv4_hub()) {
1089 mnp->m_val = 0;
1090 mnp->n_lshift = 0;
1091 } else if (is_uv3_hub()) {
1092 mnp->m_val = m_n_config.s3.m_skt;
1093 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1094 mnp->n_lshift = m_gr_config.s3.m_skt;
1095 } else if (is_uv2_hub()) {
1096 mnp->m_val = m_n_config.s2.m_skt;
1097 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1098 } else if (is_uv1_hub()) {
1099 mnp->m_val = m_n_config.s1.m_skt;
1100 mnp->n_lshift = mnp->m_val;
1101 }
1102 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1103}
1104
1105void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1106{
1107 union uvh_node_id_u node_id;
1108 struct mn mn;
1109
1110 get_mn(&mn);
1111 hi->gpa_mask = mn.m_val ?
1112 (1UL << (mn.m_val + mn.n_val)) - 1 :
1113 (1UL << uv_cpuid.gpa_shift) - 1;
1114
1115 hi->m_val = mn.m_val;
1116 hi->n_val = mn.n_val;
1117 hi->m_shift = mn.m_shift;
1118 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1119 hi->hub_revision = uv_hub_info->hub_revision;
1120 hi->pnode_mask = uv_cpuid.pnode_mask;
1121 hi->min_pnode = _min_pnode;
1122 hi->min_socket = _min_socket;
1123 hi->pnode_to_socket = _pnode_to_socket;
1124 hi->socket_to_node = _socket_to_node;
1125 hi->socket_to_pnode = _socket_to_pnode;
1126 hi->gr_table_len = _gr_table_len;
1127 hi->gr_table = _gr_table;
1128
1129 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1130 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1131 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1132 if (mn.m_val)
1133 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1134
1135 if (uv_gp_table) {
1136 hi->global_mmr_base = uv_gp_table->mmr_base;
1137 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1138 hi->global_gru_base = uv_gp_table->gru_base;
1139 hi->global_gru_shift = uv_gp_table->gru_shift;
1140 hi->gpa_shift = uv_gp_table->gpa_shift;
1141 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1142 } else {
1143 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1144 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1145 }
1146
1147 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1148
1149 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1150
1151 /* Show system specific info: */
1152 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1153 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1154 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1155 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1156}
1157
1158static void __init decode_gam_params(unsigned long ptr)
1159{
1160 uv_gp_table = (struct uv_gam_parameters *)ptr;
1161
1162 pr_info("UV: GAM Params...\n");
1163 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1164 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1165 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1166 uv_gp_table->gpa_shift);
1167}
1168
1169static void __init decode_gam_rng_tbl(unsigned long ptr)
1170{
1171 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1172 unsigned long lgre = 0;
1173 int index = 0;
1174 int sock_min = 999999, pnode_min = 99999;
1175 int sock_max = -1, pnode_max = -1;
1176
1177 uv_gre_table = gre;
1178 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1179 unsigned long size = ((unsigned long)(gre->limit - lgre)
1180 << UV_GAM_RANGE_SHFT);
1181 int order = 0;
1182 char suffix[] = " KMGTPE";
1183
1184 while (size > 9999 && order < sizeof(suffix)) {
1185 size /= 1024;
1186 order++;
1187 }
1188
1189 if (!index) {
1190 pr_info("UV: GAM Range Table...\n");
1191 pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1192 }
1193 pr_info("UV: %2d: 0x%014lx-0x%014lx %5lu%c %3d %04x %02x %02x\n",
1194 index++,
1195 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1196 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1197 size, suffix[order],
1198 gre->type, gre->nasid, gre->sockid, gre->pnode);
1199
1200 lgre = gre->limit;
1201 if (sock_min > gre->sockid)
1202 sock_min = gre->sockid;
1203 if (sock_max < gre->sockid)
1204 sock_max = gre->sockid;
1205 if (pnode_min > gre->pnode)
1206 pnode_min = gre->pnode;
1207 if (pnode_max < gre->pnode)
1208 pnode_max = gre->pnode;
1209 }
1210 _min_socket = sock_min;
1211 _max_socket = sock_max;
1212 _min_pnode = pnode_min;
1213 _max_pnode = pnode_max;
1214 _gr_table_len = index;
1215
1216 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1217}
1218
1219static int __init decode_uv_systab(void)
1220{
1221 struct uv_systab *st;
1222 int i;
1223
1224 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1225 return 0; /* No extended UVsystab required */
1226
1227 st = uv_systab;
1228 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1229 int rev = st ? st->revision : 0;
1230
1231 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1232 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1233 uv_system_type = UV_NONE;
1234
1235 return -EINVAL;
1236 }
1237
1238 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1239 unsigned long ptr = st->entry[i].offset;
1240
1241 if (!ptr)
1242 continue;
1243
1244 ptr = ptr + (unsigned long)st;
1245
1246 switch (st->entry[i].type) {
1247 case UV_SYSTAB_TYPE_GAM_PARAMS:
1248 decode_gam_params(ptr);
1249 break;
1250
1251 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1252 decode_gam_rng_tbl(ptr);
1253 break;
1254 }
1255 }
1256 return 0;
1257}
1258
1259/*
1260 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1261 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1262 * .. being replaced by GAM Range Table
1263 */
1264static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1265{
1266 int i, uv_pb = 0;
1267
1268 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1269 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1270 unsigned long np;
1271
1272 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1273 if (np)
1274 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1275
1276 uv_pb += hweight64(np);
1277 }
1278 if (uv_possible_blades != uv_pb)
1279 uv_possible_blades = uv_pb;
1280}
1281
1282static void __init build_socket_tables(void)
1283{
1284 struct uv_gam_range_entry *gre = uv_gre_table;
1285 int num, nump;
1286 int cpu, i, lnid;
1287 int minsock = _min_socket;
1288 int maxsock = _max_socket;
1289 int minpnode = _min_pnode;
1290 int maxpnode = _max_pnode;
1291 size_t bytes;
1292
1293 if (!gre) {
1294 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1295 pr_info("UV: No UVsystab socket table, ignoring\n");
1296 return;
1297 }
1298 pr_crit("UV: Error: UVsystab address translations not available!\n");
1299 BUG();
1300 }
1301
1302 /* Build socket id -> node id, pnode */
1303 num = maxsock - minsock + 1;
1304 bytes = num * sizeof(_socket_to_node[0]);
1305 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1306 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1307
1308 nump = maxpnode - minpnode + 1;
1309 bytes = nump * sizeof(_pnode_to_socket[0]);
1310 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1311 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1312
1313 for (i = 0; i < num; i++)
1314 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1315
1316 for (i = 0; i < nump; i++)
1317 _pnode_to_socket[i] = SOCK_EMPTY;
1318
1319 /* Fill in pnode/node/addr conversion list values: */
1320 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1321 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1322 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1323 continue;
1324 i = gre->sockid - minsock;
1325 /* Duplicate: */
1326 if (_socket_to_pnode[i] != SOCK_EMPTY)
1327 continue;
1328 _socket_to_pnode[i] = gre->pnode;
1329
1330 i = gre->pnode - minpnode;
1331 _pnode_to_socket[i] = gre->sockid;
1332
1333 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1334 gre->sockid, gre->type, gre->nasid,
1335 _socket_to_pnode[gre->sockid - minsock],
1336 _pnode_to_socket[gre->pnode - minpnode]);
1337 }
1338
1339 /* Set socket -> node values: */
1340 lnid = -1;
1341 for_each_present_cpu(cpu) {
1342 int nid = cpu_to_node(cpu);
1343 int apicid, sockid;
1344
1345 if (lnid == nid)
1346 continue;
1347 lnid = nid;
1348 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1349 sockid = apicid >> uv_cpuid.socketid_shift;
1350 _socket_to_node[sockid - minsock] = nid;
1351 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1352 sockid, apicid, nid);
1353 }
1354
1355 /* Set up physical blade to pnode translation from GAM Range Table: */
1356 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1357 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1358 BUG_ON(!_node_to_pnode);
1359
1360 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1361 unsigned short sockid;
1362
1363 for (sockid = minsock; sockid <= maxsock; sockid++) {
1364 if (lnid == _socket_to_node[sockid - minsock]) {
1365 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1366 break;
1367 }
1368 }
1369 if (sockid > maxsock) {
1370 pr_err("UV: socket for node %d not found!\n", lnid);
1371 BUG();
1372 }
1373 }
1374
1375 /*
1376 * If socket id == pnode or socket id == node for all nodes,
1377 * system runs faster by removing corresponding conversion table.
1378 */
1379 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1380 if (minsock == 0) {
1381 for (i = 0; i < num; i++)
1382 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1383 break;
1384 if (i >= num) {
1385 kfree(_socket_to_node);
1386 _socket_to_node = NULL;
1387 pr_info("UV: 1:1 socket_to_node table removed\n");
1388 }
1389 }
1390 if (minsock == minpnode) {
1391 for (i = 0; i < num; i++)
1392 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1393 _socket_to_pnode[i] != i + minpnode)
1394 break;
1395 if (i >= num) {
1396 kfree(_socket_to_pnode);
1397 _socket_to_pnode = NULL;
1398 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1399 }
1400 }
1401}
1402
1403static void __init uv_system_init_hub(void)
1404{
1405 struct uv_hub_info_s hub_info = {0};
1406 int bytes, cpu, nodeid;
1407 unsigned short min_pnode = 9999, max_pnode = 0;
1408 char *hub = is_uv4_hub() ? "UV400" :
1409 is_uv3_hub() ? "UV300" :
1410 is_uv2_hub() ? "UV2000/3000" :
1411 is_uv1_hub() ? "UV100/1000" : NULL;
1412
1413 if (!hub) {
1414 pr_err("UV: Unknown/unsupported UV hub\n");
1415 return;
1416 }
1417 pr_info("UV: Found %s hub\n", hub);
1418
1419 map_low_mmrs();
1420
1421 /* Get uv_systab for decoding: */
1422 uv_bios_init();
1423
1424 /* If there's an UVsystab problem then abort UV init: */
1425 if (decode_uv_systab() < 0)
1426 return;
1427
1428 build_socket_tables();
1429 build_uv_gr_table();
1430 uv_init_hub_info(&hub_info);
1431 uv_possible_blades = num_possible_nodes();
1432 if (!_node_to_pnode)
1433 boot_init_possible_blades(&hub_info);
1434
1435 /* uv_num_possible_blades() is really the hub count: */
1436 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1437
1438 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1439 hub_info.coherency_domain_number = sn_coherency_id;
1440 uv_rtc_init();
1441
1442 bytes = sizeof(void *) * uv_num_possible_blades();
1443 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1444 BUG_ON(!__uv_hub_info_list);
1445
1446 bytes = sizeof(struct uv_hub_info_s);
1447 for_each_node(nodeid) {
1448 struct uv_hub_info_s *new_hub;
1449
1450 if (__uv_hub_info_list[nodeid]) {
1451 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1452 BUG();
1453 }
1454
1455 /* Allocate new per hub info list */
1456 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1457 BUG_ON(!new_hub);
1458 __uv_hub_info_list[nodeid] = new_hub;
1459 new_hub = uv_hub_info_list(nodeid);
1460 BUG_ON(!new_hub);
1461 *new_hub = hub_info;
1462
1463 /* Use information from GAM table if available: */
1464 if (_node_to_pnode)
1465 new_hub->pnode = _node_to_pnode[nodeid];
1466 else /* Or fill in during CPU loop: */
1467 new_hub->pnode = 0xffff;
1468
1469 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1470 new_hub->memory_nid = -1;
1471 new_hub->nr_possible_cpus = 0;
1472 new_hub->nr_online_cpus = 0;
1473 }
1474
1475 /* Initialize per CPU info: */
1476 for_each_possible_cpu(cpu) {
1477 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1478 int numa_node_id;
1479 unsigned short pnode;
1480
1481 nodeid = cpu_to_node(cpu);
1482 numa_node_id = numa_cpu_node(cpu);
1483 pnode = uv_apicid_to_pnode(apicid);
1484
1485 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1486 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1487 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1488 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1489
1490 /* Init memoryless node: */
1491 if (nodeid != numa_node_id &&
1492 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1493 uv_hub_info_list(numa_node_id)->pnode = pnode;
1494 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1495 uv_cpu_hub_info(cpu)->pnode = pnode;
1496
1497 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1498 }
1499
1500 for_each_node(nodeid) {
1501 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1502
1503 /* Add pnode info for pre-GAM list nodes without CPUs: */
1504 if (pnode == 0xffff) {
1505 unsigned long paddr;
1506
1507 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1508 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1509 uv_hub_info_list(nodeid)->pnode = pnode;
1510 }
1511 min_pnode = min(pnode, min_pnode);
1512 max_pnode = max(pnode, max_pnode);
1513 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1514 nodeid,
1515 uv_hub_info_list(nodeid)->pnode,
1516 uv_hub_info_list(nodeid)->nr_possible_cpus);
1517 }
1518
1519 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1520 map_gru_high(max_pnode);
1521 map_mmr_high(max_pnode);
1522 map_mmioh_high(min_pnode, max_pnode);
1523
1524 uv_nmi_setup();
1525 uv_cpu_init();
1526 uv_scir_register_cpu_notifier();
1527 proc_mkdir("sgi_uv", NULL);
1528
1529 /* Register Legacy VGA I/O redirection handler: */
1530 pci_register_set_vga_state(uv_set_vga_state);
1531
1532 /*
1533 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1534 * EFI is not enabled in the kdump kernel:
1535 */
1536 if (is_kdump_kernel())
1537 reboot_type = BOOT_ACPI;
1538}
1539
1540/*
1541 * There is a small amount of UV specific code needed to initialize a
1542 * UV system that does not have a "UV HUB" (referred to as "hubless").
1543 */
1544void __init uv_system_init(void)
1545{
1546 if (likely(!is_uv_system() && !is_uv_hubless()))
1547 return;
1548
1549 if (is_uv_system())
1550 uv_system_init_hub();
1551 else
1552 uv_nmi_setup_hubless();
1553}
1554
1555apic_driver(apic_x2apic_uv_x);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
9 */
10#include <linux/cpumask.h>
11#include <linux/hardirq.h>
12#include <linux/proc_fs.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/ctype.h>
18#include <linux/sched.h>
19#include <linux/timer.h>
20#include <linux/slab.h>
21#include <linux/cpu.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/pci.h>
25#include <linux/kdebug.h>
26#include <linux/delay.h>
27#include <linux/crash_dump.h>
28
29#include <asm/uv/uv_mmrs.h>
30#include <asm/uv/uv_hub.h>
31#include <asm/current.h>
32#include <asm/pgtable.h>
33#include <asm/uv/bios.h>
34#include <asm/uv/uv.h>
35#include <asm/apic.h>
36#include <asm/ipi.h>
37#include <asm/smp.h>
38#include <asm/x86_init.h>
39#include <asm/emergency-restart.h>
40#include <asm/nmi.h>
41
42/* BMC sets a bit this MMR non-zero before sending an NMI */
43#define UVH_NMI_MMR UVH_SCRATCH5
44#define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8)
45#define UV_NMI_PENDING_MASK (1UL << 63)
46DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
47
48DEFINE_PER_CPU(int, x2apic_extra_bits);
49
50#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
51
52static enum uv_system_type uv_system_type;
53static u64 gru_start_paddr, gru_end_paddr;
54static union uvh_apicid uvh_apicid;
55int uv_min_hub_revision_id;
56EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
57unsigned int uv_apicid_hibits;
58EXPORT_SYMBOL_GPL(uv_apicid_hibits);
59static DEFINE_SPINLOCK(uv_nmi_lock);
60
61static struct apic apic_x2apic_uv_x;
62
63static unsigned long __init uv_early_read_mmr(unsigned long addr)
64{
65 unsigned long val, *mmr;
66
67 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
68 val = *mmr;
69 early_iounmap(mmr, sizeof(*mmr));
70 return val;
71}
72
73static inline bool is_GRU_range(u64 start, u64 end)
74{
75 return start >= gru_start_paddr && end <= gru_end_paddr;
76}
77
78static bool uv_is_untracked_pat_range(u64 start, u64 end)
79{
80 return is_ISA_range(start, end) || is_GRU_range(start, end);
81}
82
83static int __init early_get_pnodeid(void)
84{
85 union uvh_node_id_u node_id;
86 union uvh_rh_gam_config_mmr_u m_n_config;
87 int pnode;
88
89 /* Currently, all blades have same revision number */
90 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
91 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
92 uv_min_hub_revision_id = node_id.s.revision;
93
94 if (node_id.s.part_number == UV2_HUB_PART_NUMBER)
95 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
96 if (node_id.s.part_number == UV2_HUB_PART_NUMBER_X)
97 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
98
99 uv_hub_info->hub_revision = uv_min_hub_revision_id;
100 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
101 return pnode;
102}
103
104static void __init early_get_apic_pnode_shift(void)
105{
106 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
107 if (!uvh_apicid.v)
108 /*
109 * Old bios, use default value
110 */
111 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
112}
113
114/*
115 * Add an extra bit as dictated by bios to the destination apicid of
116 * interrupts potentially passing through the UV HUB. This prevents
117 * a deadlock between interrupts and IO port operations.
118 */
119static void __init uv_set_apicid_hibit(void)
120{
121 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
122
123 if (is_uv1_hub()) {
124 apicid_mask.v =
125 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
126 uv_apicid_hibits =
127 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
128 }
129}
130
131static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
132{
133 int pnodeid, is_uv1, is_uv2;
134
135 is_uv1 = !strcmp(oem_id, "SGI");
136 is_uv2 = !strcmp(oem_id, "SGI2");
137 if (is_uv1 || is_uv2) {
138 uv_hub_info->hub_revision =
139 is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE;
140 pnodeid = early_get_pnodeid();
141 early_get_apic_pnode_shift();
142 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
143 x86_platform.nmi_init = uv_nmi_init;
144 if (!strcmp(oem_table_id, "UVL"))
145 uv_system_type = UV_LEGACY_APIC;
146 else if (!strcmp(oem_table_id, "UVX"))
147 uv_system_type = UV_X2APIC;
148 else if (!strcmp(oem_table_id, "UVH")) {
149 __this_cpu_write(x2apic_extra_bits,
150 pnodeid << uvh_apicid.s.pnode_shift);
151 uv_system_type = UV_NON_UNIQUE_APIC;
152 uv_set_apicid_hibit();
153 return 1;
154 }
155 }
156 return 0;
157}
158
159enum uv_system_type get_uv_system_type(void)
160{
161 return uv_system_type;
162}
163
164int is_uv_system(void)
165{
166 return uv_system_type != UV_NONE;
167}
168EXPORT_SYMBOL_GPL(is_uv_system);
169
170DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
171EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
172
173struct uv_blade_info *uv_blade_info;
174EXPORT_SYMBOL_GPL(uv_blade_info);
175
176short *uv_node_to_blade;
177EXPORT_SYMBOL_GPL(uv_node_to_blade);
178
179short *uv_cpu_to_blade;
180EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
181
182short uv_possible_blades;
183EXPORT_SYMBOL_GPL(uv_possible_blades);
184
185unsigned long sn_rtc_cycles_per_second;
186EXPORT_SYMBOL(sn_rtc_cycles_per_second);
187
188static const struct cpumask *uv_target_cpus(void)
189{
190 return cpu_online_mask;
191}
192
193static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
194{
195 cpumask_clear(retmask);
196 cpumask_set_cpu(cpu, retmask);
197}
198
199static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
200{
201#ifdef CONFIG_SMP
202 unsigned long val;
203 int pnode;
204
205 pnode = uv_apicid_to_pnode(phys_apicid);
206 phys_apicid |= uv_apicid_hibits;
207 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
208 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
209 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
210 APIC_DM_INIT;
211 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
212
213 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
214 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
215 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
216 APIC_DM_STARTUP;
217 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
218
219 atomic_set(&init_deasserted, 1);
220#endif
221 return 0;
222}
223
224static void uv_send_IPI_one(int cpu, int vector)
225{
226 unsigned long apicid;
227 int pnode;
228
229 apicid = per_cpu(x86_cpu_to_apicid, cpu);
230 pnode = uv_apicid_to_pnode(apicid);
231 uv_hub_send_ipi(pnode, apicid, vector);
232}
233
234static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
235{
236 unsigned int cpu;
237
238 for_each_cpu(cpu, mask)
239 uv_send_IPI_one(cpu, vector);
240}
241
242static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
243{
244 unsigned int this_cpu = smp_processor_id();
245 unsigned int cpu;
246
247 for_each_cpu(cpu, mask) {
248 if (cpu != this_cpu)
249 uv_send_IPI_one(cpu, vector);
250 }
251}
252
253static void uv_send_IPI_allbutself(int vector)
254{
255 unsigned int this_cpu = smp_processor_id();
256 unsigned int cpu;
257
258 for_each_online_cpu(cpu) {
259 if (cpu != this_cpu)
260 uv_send_IPI_one(cpu, vector);
261 }
262}
263
264static void uv_send_IPI_all(int vector)
265{
266 uv_send_IPI_mask(cpu_online_mask, vector);
267}
268
269static int uv_apic_id_valid(int apicid)
270{
271 return 1;
272}
273
274static int uv_apic_id_registered(void)
275{
276 return 1;
277}
278
279static void uv_init_apic_ldr(void)
280{
281}
282
283static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
284{
285 /*
286 * We're using fixed IRQ delivery, can only return one phys APIC ID.
287 * May as well be the first.
288 */
289 int cpu = cpumask_first(cpumask);
290
291 if ((unsigned)cpu < nr_cpu_ids)
292 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
293 else
294 return BAD_APICID;
295}
296
297static unsigned int
298uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
299 const struct cpumask *andmask)
300{
301 int cpu;
302
303 /*
304 * We're using fixed IRQ delivery, can only return one phys APIC ID.
305 * May as well be the first.
306 */
307 for_each_cpu_and(cpu, cpumask, andmask) {
308 if (cpumask_test_cpu(cpu, cpu_online_mask))
309 break;
310 }
311 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
312}
313
314static unsigned int x2apic_get_apic_id(unsigned long x)
315{
316 unsigned int id;
317
318 WARN_ON(preemptible() && num_online_cpus() > 1);
319 id = x | __this_cpu_read(x2apic_extra_bits);
320
321 return id;
322}
323
324static unsigned long set_apic_id(unsigned int id)
325{
326 unsigned long x;
327
328 /* maskout x2apic_extra_bits ? */
329 x = id;
330 return x;
331}
332
333static unsigned int uv_read_apic_id(void)
334{
335
336 return x2apic_get_apic_id(apic_read(APIC_ID));
337}
338
339static int uv_phys_pkg_id(int initial_apicid, int index_msb)
340{
341 return uv_read_apic_id() >> index_msb;
342}
343
344static void uv_send_IPI_self(int vector)
345{
346 apic_write(APIC_SELF_IPI, vector);
347}
348
349static int uv_probe(void)
350{
351 return apic == &apic_x2apic_uv_x;
352}
353
354static struct apic __refdata apic_x2apic_uv_x = {
355
356 .name = "UV large system",
357 .probe = uv_probe,
358 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
359 .apic_id_valid = uv_apic_id_valid,
360 .apic_id_registered = uv_apic_id_registered,
361
362 .irq_delivery_mode = dest_Fixed,
363 .irq_dest_mode = 0, /* physical */
364
365 .target_cpus = uv_target_cpus,
366 .disable_esr = 0,
367 .dest_logical = APIC_DEST_LOGICAL,
368 .check_apicid_used = NULL,
369 .check_apicid_present = NULL,
370
371 .vector_allocation_domain = uv_vector_allocation_domain,
372 .init_apic_ldr = uv_init_apic_ldr,
373
374 .ioapic_phys_id_map = NULL,
375 .setup_apic_routing = NULL,
376 .multi_timer_check = NULL,
377 .cpu_present_to_apicid = default_cpu_present_to_apicid,
378 .apicid_to_cpu_present = NULL,
379 .setup_portio_remap = NULL,
380 .check_phys_apicid_present = default_check_phys_apicid_present,
381 .enable_apic_mode = NULL,
382 .phys_pkg_id = uv_phys_pkg_id,
383 .mps_oem_check = NULL,
384
385 .get_apic_id = x2apic_get_apic_id,
386 .set_apic_id = set_apic_id,
387 .apic_id_mask = 0xFFFFFFFFu,
388
389 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
390 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
391
392 .send_IPI_mask = uv_send_IPI_mask,
393 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
394 .send_IPI_allbutself = uv_send_IPI_allbutself,
395 .send_IPI_all = uv_send_IPI_all,
396 .send_IPI_self = uv_send_IPI_self,
397
398 .wakeup_secondary_cpu = uv_wakeup_secondary,
399 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
400 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
401 .wait_for_init_deassert = NULL,
402 .smp_callin_clear_local_apic = NULL,
403 .inquire_remote_apic = NULL,
404
405 .read = native_apic_msr_read,
406 .write = native_apic_msr_write,
407 .eoi_write = native_apic_msr_eoi_write,
408 .icr_read = native_x2apic_icr_read,
409 .icr_write = native_x2apic_icr_write,
410 .wait_icr_idle = native_x2apic_wait_icr_idle,
411 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
412};
413
414static __cpuinit void set_x2apic_extra_bits(int pnode)
415{
416 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
417}
418
419/*
420 * Called on boot cpu.
421 */
422static __init int boot_pnode_to_blade(int pnode)
423{
424 int blade;
425
426 for (blade = 0; blade < uv_num_possible_blades(); blade++)
427 if (pnode == uv_blade_info[blade].pnode)
428 return blade;
429 BUG();
430}
431
432struct redir_addr {
433 unsigned long redirect;
434 unsigned long alias;
435};
436
437#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
438
439static __initdata struct redir_addr redir_addrs[] = {
440 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
441 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
442 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
443};
444
445static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
446{
447 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
448 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
449 int i;
450
451 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
452 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
453 if (alias.s.enable && alias.s.base == 0) {
454 *size = (1UL << alias.s.m_alias);
455 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
456 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
457 return;
458 }
459 }
460 *base = *size = 0;
461}
462
463enum map_type {map_wb, map_uc};
464
465static __init void map_high(char *id, unsigned long base, int pshift,
466 int bshift, int max_pnode, enum map_type map_type)
467{
468 unsigned long bytes, paddr;
469
470 paddr = base << pshift;
471 bytes = (1UL << bshift) * (max_pnode + 1);
472 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
473 paddr + bytes);
474 if (map_type == map_uc)
475 init_extra_mapping_uc(paddr, bytes);
476 else
477 init_extra_mapping_wb(paddr, bytes);
478
479}
480static __init void map_gru_high(int max_pnode)
481{
482 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
483 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
484
485 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
486 if (gru.s.enable) {
487 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
488 gru_start_paddr = ((u64)gru.s.base << shift);
489 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
490
491 }
492}
493
494static __init void map_mmr_high(int max_pnode)
495{
496 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
497 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
498
499 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
500 if (mmr.s.enable)
501 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
502}
503
504static __init void map_mmioh_high(int max_pnode)
505{
506 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
507 int shift;
508
509 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
510 if (is_uv1_hub() && mmioh.s1.enable) {
511 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
512 map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io,
513 max_pnode, map_uc);
514 }
515 if (is_uv2_hub() && mmioh.s2.enable) {
516 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
517 map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io,
518 max_pnode, map_uc);
519 }
520}
521
522static __init void map_low_mmrs(void)
523{
524 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
525 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
526}
527
528static __init void uv_rtc_init(void)
529{
530 long status;
531 u64 ticks_per_sec;
532
533 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
534 &ticks_per_sec);
535 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
536 printk(KERN_WARNING
537 "unable to determine platform RTC clock frequency, "
538 "guessing.\n");
539 /* BIOS gives wrong value for clock freq. so guess */
540 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
541 } else
542 sn_rtc_cycles_per_second = ticks_per_sec;
543}
544
545/*
546 * percpu heartbeat timer
547 */
548static void uv_heartbeat(unsigned long ignored)
549{
550 struct timer_list *timer = &uv_hub_info->scir.timer;
551 unsigned char bits = uv_hub_info->scir.state;
552
553 /* flip heartbeat bit */
554 bits ^= SCIR_CPU_HEARTBEAT;
555
556 /* is this cpu idle? */
557 if (idle_cpu(raw_smp_processor_id()))
558 bits &= ~SCIR_CPU_ACTIVITY;
559 else
560 bits |= SCIR_CPU_ACTIVITY;
561
562 /* update system controller interface reg */
563 uv_set_scir_bits(bits);
564
565 /* enable next timer period */
566 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
567}
568
569static void __cpuinit uv_heartbeat_enable(int cpu)
570{
571 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
572 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
573
574 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
575 setup_timer(timer, uv_heartbeat, cpu);
576 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
577 add_timer_on(timer, cpu);
578 uv_cpu_hub_info(cpu)->scir.enabled = 1;
579
580 /* also ensure that boot cpu is enabled */
581 cpu = 0;
582 }
583}
584
585#ifdef CONFIG_HOTPLUG_CPU
586static void __cpuinit uv_heartbeat_disable(int cpu)
587{
588 if (uv_cpu_hub_info(cpu)->scir.enabled) {
589 uv_cpu_hub_info(cpu)->scir.enabled = 0;
590 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
591 }
592 uv_set_cpu_scir_bits(cpu, 0xff);
593}
594
595/*
596 * cpu hotplug notifier
597 */
598static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
599 unsigned long action, void *hcpu)
600{
601 long cpu = (long)hcpu;
602
603 switch (action) {
604 case CPU_ONLINE:
605 uv_heartbeat_enable(cpu);
606 break;
607 case CPU_DOWN_PREPARE:
608 uv_heartbeat_disable(cpu);
609 break;
610 default:
611 break;
612 }
613 return NOTIFY_OK;
614}
615
616static __init void uv_scir_register_cpu_notifier(void)
617{
618 hotcpu_notifier(uv_scir_cpu_notify, 0);
619}
620
621#else /* !CONFIG_HOTPLUG_CPU */
622
623static __init void uv_scir_register_cpu_notifier(void)
624{
625}
626
627static __init int uv_init_heartbeat(void)
628{
629 int cpu;
630
631 if (is_uv_system())
632 for_each_online_cpu(cpu)
633 uv_heartbeat_enable(cpu);
634 return 0;
635}
636
637late_initcall(uv_init_heartbeat);
638
639#endif /* !CONFIG_HOTPLUG_CPU */
640
641/* Direct Legacy VGA I/O traffic to designated IOH */
642int uv_set_vga_state(struct pci_dev *pdev, bool decode,
643 unsigned int command_bits, u32 flags)
644{
645 int domain, bus, rc;
646
647 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
648 pdev->devfn, decode, command_bits, flags);
649
650 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
651 return 0;
652
653 if ((command_bits & PCI_COMMAND_IO) == 0)
654 return 0;
655
656 domain = pci_domain_nr(pdev->bus);
657 bus = pdev->bus->number;
658
659 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
660 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
661
662 return rc;
663}
664
665/*
666 * Called on each cpu to initialize the per_cpu UV data area.
667 * FIXME: hotplug not supported yet
668 */
669void __cpuinit uv_cpu_init(void)
670{
671 /* CPU 0 initilization will be done via uv_system_init. */
672 if (!uv_blade_info)
673 return;
674
675 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
676
677 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
678 set_x2apic_extra_bits(uv_hub_info->pnode);
679}
680
681/*
682 * When NMI is received, print a stack trace.
683 */
684int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
685{
686 unsigned long real_uv_nmi;
687 int bid;
688
689 /*
690 * Each blade has an MMR that indicates when an NMI has been sent
691 * to cpus on the blade. If an NMI is detected, atomically
692 * clear the MMR and update a per-blade NMI count used to
693 * cause each cpu on the blade to notice a new NMI.
694 */
695 bid = uv_numa_blade_id();
696 real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
697
698 if (unlikely(real_uv_nmi)) {
699 spin_lock(&uv_blade_info[bid].nmi_lock);
700 real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
701 if (real_uv_nmi) {
702 uv_blade_info[bid].nmi_count++;
703 uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
704 }
705 spin_unlock(&uv_blade_info[bid].nmi_lock);
706 }
707
708 if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
709 return NMI_DONE;
710
711 __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
712
713 /*
714 * Use a lock so only one cpu prints at a time.
715 * This prevents intermixed output.
716 */
717 spin_lock(&uv_nmi_lock);
718 pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
719 dump_stack();
720 spin_unlock(&uv_nmi_lock);
721
722 return NMI_HANDLED;
723}
724
725void uv_register_nmi_notifier(void)
726{
727 if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
728 printk(KERN_WARNING "UV NMI handler failed to register\n");
729}
730
731void uv_nmi_init(void)
732{
733 unsigned int value;
734
735 /*
736 * Unmask NMI on all cpus
737 */
738 value = apic_read(APIC_LVT1) | APIC_DM_NMI;
739 value &= ~APIC_LVT_MASKED;
740 apic_write(APIC_LVT1, value);
741}
742
743void __init uv_system_init(void)
744{
745 union uvh_rh_gam_config_mmr_u m_n_config;
746 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
747 union uvh_node_id_u node_id;
748 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
749 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
750 int gnode_extra, max_pnode = 0;
751 unsigned long mmr_base, present, paddr;
752 unsigned short pnode_mask, pnode_io_mask;
753
754 printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2");
755 map_low_mmrs();
756
757 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
758 m_val = m_n_config.s.m_skt;
759 n_val = m_n_config.s.n_skt;
760 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
761 n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io;
762 mmr_base =
763 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
764 ~UV_MMR_ENABLE;
765 pnode_mask = (1 << n_val) - 1;
766 pnode_io_mask = (1 << n_io) - 1;
767
768 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
769 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
770 gnode_upper = ((unsigned long)gnode_extra << m_val);
771 printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
772 n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
773
774 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
775
776 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
777 uv_possible_blades +=
778 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
779
780 /* uv_num_possible_blades() is really the hub count */
781 printk(KERN_INFO "UV: Found %d blades, %d hubs\n",
782 is_uv1_hub() ? uv_num_possible_blades() :
783 (uv_num_possible_blades() + 1) / 2,
784 uv_num_possible_blades());
785
786 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
787 uv_blade_info = kzalloc(bytes, GFP_KERNEL);
788 BUG_ON(!uv_blade_info);
789
790 for (blade = 0; blade < uv_num_possible_blades(); blade++)
791 uv_blade_info[blade].memory_nid = -1;
792
793 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
794
795 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
796 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
797 BUG_ON(!uv_node_to_blade);
798 memset(uv_node_to_blade, 255, bytes);
799
800 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
801 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
802 BUG_ON(!uv_cpu_to_blade);
803 memset(uv_cpu_to_blade, 255, bytes);
804
805 blade = 0;
806 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
807 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
808 for (j = 0; j < 64; j++) {
809 if (!test_bit(j, &present))
810 continue;
811 pnode = (i * 64 + j) & pnode_mask;
812 uv_blade_info[blade].pnode = pnode;
813 uv_blade_info[blade].nr_possible_cpus = 0;
814 uv_blade_info[blade].nr_online_cpus = 0;
815 spin_lock_init(&uv_blade_info[blade].nmi_lock);
816 max_pnode = max(pnode, max_pnode);
817 blade++;
818 }
819 }
820
821 uv_bios_init();
822 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
823 &sn_region_size, &system_serial_number);
824 uv_rtc_init();
825
826 for_each_present_cpu(cpu) {
827 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
828
829 nid = cpu_to_node(cpu);
830 /*
831 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
832 */
833 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
834 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
835 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
836
837 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
838 uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ?
839 (m_val == 40 ? 40 : 39) : m_val;
840
841 pnode = uv_apicid_to_pnode(apicid);
842 blade = boot_pnode_to_blade(pnode);
843 lcpu = uv_blade_info[blade].nr_possible_cpus;
844 uv_blade_info[blade].nr_possible_cpus++;
845
846 /* Any node on the blade, else will contain -1. */
847 uv_blade_info[blade].memory_nid = nid;
848
849 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
850 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
851 uv_cpu_hub_info(cpu)->m_val = m_val;
852 uv_cpu_hub_info(cpu)->n_val = n_val;
853 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
854 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
855 uv_cpu_hub_info(cpu)->pnode = pnode;
856 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
857 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
858 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
859 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
860 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
861 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
862 uv_node_to_blade[nid] = blade;
863 uv_cpu_to_blade[cpu] = blade;
864 }
865
866 /* Add blade/pnode info for nodes without cpus */
867 for_each_online_node(nid) {
868 if (uv_node_to_blade[nid] >= 0)
869 continue;
870 paddr = node_start_pfn(nid) << PAGE_SHIFT;
871 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
872 blade = boot_pnode_to_blade(pnode);
873 uv_node_to_blade[nid] = blade;
874 }
875
876 map_gru_high(max_pnode);
877 map_mmr_high(max_pnode);
878 map_mmioh_high(max_pnode & pnode_io_mask);
879
880 uv_cpu_init();
881 uv_scir_register_cpu_notifier();
882 uv_register_nmi_notifier();
883 proc_mkdir("sgi_uv", NULL);
884
885 /* register Legacy VGA I/O redirection handler */
886 pci_register_set_vga_state(uv_set_vga_state);
887
888 /*
889 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
890 * EFI is not enabled in the kdump kernel.
891 */
892 if (is_kdump_kernel())
893 reboot_type = BOOT_ACPI;
894}
895
896apic_driver(apic_x2apic_uv_x);