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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
4 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
5 * Copyright (C) 2004 Maciej W. Rozycki
6 */
7#include <linux/delay.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/seq_file.h>
11#include <asm/bootinfo.h>
12#include <asm/cpu.h>
13#include <asm/cpu-features.h>
14#include <asm/idle.h>
15#include <asm/mipsregs.h>
16#include <asm/processor.h>
17#include <asm/prom.h>
18
19unsigned int vced_count, vcei_count;
20
21/*
22 * * No lock; only written during early bootup by CPU 0.
23 * */
24static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
25
26int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
27{
28 return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
29}
30
31int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
32{
33 return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
34}
35
36static int show_cpuinfo(struct seq_file *m, void *v)
37{
38 struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
39 unsigned long n = (unsigned long) v - 1;
40 unsigned int version = cpu_data[n].processor_id;
41 unsigned int fp_vers = cpu_data[n].fpu_id;
42 char fmt [64];
43 int i;
44
45#ifdef CONFIG_SMP
46 if (!cpu_online(n))
47 return 0;
48#endif
49
50 /*
51 * For the first processor also print the system type
52 */
53 if (n == 0) {
54 seq_printf(m, "system type\t\t: %s\n", get_system_type());
55 if (mips_get_machine_name())
56 seq_printf(m, "machine\t\t\t: %s\n",
57 mips_get_machine_name());
58 }
59
60 seq_printf(m, "processor\t\t: %ld\n", n);
61 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
62 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
63 seq_printf(m, fmt, __cpu_name[n],
64 (version >> 4) & 0x0f, version & 0x0f,
65 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
66 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
67 cpu_data[n].udelay_val / (500000/HZ),
68 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
69 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
70 seq_printf(m, "microsecond timers\t: %s\n",
71 cpu_has_counter ? "yes" : "no");
72 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
73 seq_printf(m, "extra interrupt vector\t: %s\n",
74 cpu_has_divec ? "yes" : "no");
75 seq_printf(m, "hardware watchpoint\t: %s",
76 cpu_has_watch ? "yes, " : "no\n");
77 if (cpu_has_watch) {
78 seq_printf(m, "count: %d, address/irw mask: [",
79 cpu_data[n].watch_reg_count);
80 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
81 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
82 cpu_data[n].watch_reg_masks[i]);
83 seq_printf(m, "]\n");
84 }
85
86 seq_printf(m, "isa\t\t\t:");
87 if (cpu_has_mips_1)
88 seq_printf(m, " mips1");
89 if (cpu_has_mips_2)
90 seq_printf(m, "%s", " mips2");
91 if (cpu_has_mips_3)
92 seq_printf(m, "%s", " mips3");
93 if (cpu_has_mips_4)
94 seq_printf(m, "%s", " mips4");
95 if (cpu_has_mips_5)
96 seq_printf(m, "%s", " mips5");
97 if (cpu_has_mips32r1)
98 seq_printf(m, "%s", " mips32r1");
99 if (cpu_has_mips32r2)
100 seq_printf(m, "%s", " mips32r2");
101 if (cpu_has_mips32r6)
102 seq_printf(m, "%s", " mips32r6");
103 if (cpu_has_mips64r1)
104 seq_printf(m, "%s", " mips64r1");
105 if (cpu_has_mips64r2)
106 seq_printf(m, "%s", " mips64r2");
107 if (cpu_has_mips64r6)
108 seq_printf(m, "%s", " mips64r6");
109 seq_printf(m, "\n");
110
111 seq_printf(m, "ASEs implemented\t:");
112 if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
113 if (cpu_has_mips16e2) seq_printf(m, "%s", " mips16e2");
114 if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
115 if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
116 if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
117 if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
118 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
119 if (cpu_has_dsp3) seq_printf(m, "%s", " dsp3");
120 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
121 if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
122 if (cpu_has_vz) seq_printf(m, "%s", " vz");
123 if (cpu_has_msa) seq_printf(m, "%s", " msa");
124 if (cpu_has_eva) seq_printf(m, "%s", " eva");
125 if (cpu_has_htw) seq_printf(m, "%s", " htw");
126 if (cpu_has_xpa) seq_printf(m, "%s", " xpa");
127 seq_printf(m, "\n");
128
129 if (cpu_has_mmips) {
130 seq_printf(m, "micromips kernel\t: %s\n",
131 (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no");
132 }
133 seq_printf(m, "shadow register sets\t: %d\n",
134 cpu_data[n].srsets);
135 seq_printf(m, "kscratch registers\t: %d\n",
136 hweight8(cpu_data[n].kscratch_mask));
137 seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
138 seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
139
140#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
141 if (cpu_has_mipsmt)
142 seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
143 else if (cpu_has_vp)
144 seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
145#endif
146
147 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
148 cpu_has_vce ? "%u" : "not available");
149 seq_printf(m, fmt, 'D', vced_count);
150 seq_printf(m, fmt, 'I', vcei_count);
151
152 proc_cpuinfo_notifier_args.m = m;
153 proc_cpuinfo_notifier_args.n = n;
154
155 raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
156 &proc_cpuinfo_notifier_args);
157
158 seq_printf(m, "\n");
159
160 return 0;
161}
162
163static void *c_start(struct seq_file *m, loff_t *pos)
164{
165 unsigned long i = *pos;
166
167 return i < NR_CPUS ? (void *) (i + 1) : NULL;
168}
169
170static void *c_next(struct seq_file *m, void *v, loff_t *pos)
171{
172 ++*pos;
173 return c_start(m, pos);
174}
175
176static void c_stop(struct seq_file *m, void *v)
177{
178}
179
180const struct seq_operations cpuinfo_op = {
181 .start = c_start,
182 .next = c_next,
183 .stop = c_stop,
184 .show = show_cpuinfo,
185};
1/*
2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2004 Maciej W. Rozycki
5 */
6#include <linux/delay.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/seq_file.h>
10#include <asm/bootinfo.h>
11#include <asm/cpu.h>
12#include <asm/cpu-features.h>
13#include <asm/mipsregs.h>
14#include <asm/processor.h>
15#include <asm/mips_machine.h>
16
17unsigned int vced_count, vcei_count;
18
19static int show_cpuinfo(struct seq_file *m, void *v)
20{
21 unsigned long n = (unsigned long) v - 1;
22 unsigned int version = cpu_data[n].processor_id;
23 unsigned int fp_vers = cpu_data[n].fpu_id;
24 char fmt [64];
25 int i;
26
27#ifdef CONFIG_SMP
28 if (!cpu_online(n))
29 return 0;
30#endif
31
32 /*
33 * For the first processor also print the system type
34 */
35 if (n == 0) {
36 seq_printf(m, "system type\t\t: %s\n", get_system_type());
37 if (mips_get_machine_name())
38 seq_printf(m, "machine\t\t\t: %s\n",
39 mips_get_machine_name());
40 }
41
42 seq_printf(m, "processor\t\t: %ld\n", n);
43 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
44 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
45 seq_printf(m, fmt, __cpu_name[n],
46 (version >> 4) & 0x0f, version & 0x0f,
47 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
48 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
49 cpu_data[n].udelay_val / (500000/HZ),
50 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
51 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
52 seq_printf(m, "microsecond timers\t: %s\n",
53 cpu_has_counter ? "yes" : "no");
54 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
55 seq_printf(m, "extra interrupt vector\t: %s\n",
56 cpu_has_divec ? "yes" : "no");
57 seq_printf(m, "hardware watchpoint\t: %s",
58 cpu_has_watch ? "yes, " : "no\n");
59 if (cpu_has_watch) {
60 seq_printf(m, "count: %d, address/irw mask: [",
61 cpu_data[n].watch_reg_count);
62 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
63 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
64 cpu_data[n].watch_reg_masks[i]);
65 seq_printf(m, "]\n");
66 }
67 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
68 cpu_has_mips16 ? " mips16" : "",
69 cpu_has_mdmx ? " mdmx" : "",
70 cpu_has_mips3d ? " mips3d" : "",
71 cpu_has_smartmips ? " smartmips" : "",
72 cpu_has_dsp ? " dsp" : "",
73 cpu_has_mipsmt ? " mt" : ""
74 );
75 seq_printf(m, "shadow register sets\t: %d\n",
76 cpu_data[n].srsets);
77 seq_printf(m, "kscratch registers\t: %d\n",
78 hweight8(cpu_data[n].kscratch_mask));
79 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
80
81 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
82 cpu_has_vce ? "%u" : "not available");
83 seq_printf(m, fmt, 'D', vced_count);
84 seq_printf(m, fmt, 'I', vcei_count);
85 seq_printf(m, "\n");
86
87 return 0;
88}
89
90static void *c_start(struct seq_file *m, loff_t *pos)
91{
92 unsigned long i = *pos;
93
94 return i < NR_CPUS ? (void *) (i + 1) : NULL;
95}
96
97static void *c_next(struct seq_file *m, void *v, loff_t *pos)
98{
99 ++*pos;
100 return c_start(m, pos);
101}
102
103static void c_stop(struct seq_file *m, void *v)
104{
105}
106
107const struct seq_operations cpuinfo_op = {
108 .start = c_start,
109 .next = c_next,
110 .stop = c_stop,
111 .show = show_cpuinfo,
112};