Loading...
Note: File does not exist in v3.5.6.
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "skeleton.dtsi"
46
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/thermal/thermal.h>
49#include <dt-bindings/dma/sun4i-a10.h>
50#include <dt-bindings/clock/sun7i-a20-ccu.h>
51#include <dt-bindings/reset/sun4i-a10-ccu.h>
52
53/ {
54 interrupt-parent = <&gic>;
55
56 aliases {
57 ethernet0 = &gmac;
58 };
59
60 chosen {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
72 <&ccu CLK_HDMI>;
73 status = "disabled";
74 };
75
76 framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
83 status = "disabled";
84 };
85
86 framebuffer@2 {
87 compatible = "allwinner,simple-framebuffer",
88 "simple-framebuffer";
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 <&ccu CLK_AHB_DE_BE0>,
92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
94 status = "disabled";
95 };
96 };
97
98 cpus {
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 cpu0: cpu@0 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <0>;
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
109 /* kHz uV */
110 960000 1400000
111 912000 1400000
112 864000 1300000
113 720000 1200000
114 528000 1100000
115 312000 1000000
116 144000 1000000
117 >;
118 #cooling-cells = <2>;
119 };
120
121 cpu@1 {
122 compatible = "arm,cortex-a7";
123 device_type = "cpu";
124 reg = <1>;
125 };
126 };
127
128 thermal-zones {
129 cpu_thermal {
130 /* milliseconds */
131 polling-delay-passive = <250>;
132 polling-delay = <1000>;
133 thermal-sensors = <&rtp>;
134
135 cooling-maps {
136 map0 {
137 trip = <&cpu_alert0>;
138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
139 };
140 };
141
142 trips {
143 cpu_alert0: cpu_alert0 {
144 /* milliCelsius */
145 temperature = <75000>;
146 hysteresis = <2000>;
147 type = "passive";
148 };
149
150 cpu_crit: cpu_crit {
151 /* milliCelsius */
152 temperature = <100000>;
153 hysteresis = <2000>;
154 type = "critical";
155 };
156 };
157 };
158 };
159
160 memory {
161 reg = <0x40000000 0x80000000>;
162 };
163
164 timer {
165 compatible = "arm,armv7-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
170 };
171
172 pmu {
173 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
174 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
176 };
177
178 clocks {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges;
182
183 osc24M: clk@1c20050 {
184 #clock-cells = <0>;
185 compatible = "fixed-clock";
186 clock-frequency = <24000000>;
187 clock-output-names = "osc24M";
188 };
189
190 osc32k: clk@0 {
191 #clock-cells = <0>;
192 compatible = "fixed-clock";
193 clock-frequency = <32768>;
194 clock-output-names = "osc32k";
195 };
196
197 /*
198 * The following two are dummy clocks, placeholders
199 * used in the gmac_tx clock. The gmac driver will
200 * choose one parent depending on the PHY interface
201 * mode, using clk_set_rate auto-reparenting.
202 *
203 * The actual TX clock rate is not controlled by the
204 * gmac_tx clock.
205 */
206 mii_phy_tx_clk: clk@1 {
207 #clock-cells = <0>;
208 compatible = "fixed-clock";
209 clock-frequency = <25000000>;
210 clock-output-names = "mii_phy_tx";
211 };
212
213 gmac_int_tx_clk: clk@2 {
214 #clock-cells = <0>;
215 compatible = "fixed-clock";
216 clock-frequency = <125000000>;
217 clock-output-names = "gmac_int_tx";
218 };
219
220 gmac_tx_clk: clk@1c20164 {
221 #clock-cells = <0>;
222 compatible = "allwinner,sun7i-a20-gmac-clk";
223 reg = <0x01c20164 0x4>;
224 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
225 clock-output-names = "gmac_tx";
226 };
227 };
228
229
230 de: display-engine {
231 compatible = "allwinner,sun7i-a20-display-engine";
232 allwinner,pipelines = <&fe0>, <&fe1>;
233 status = "disabled";
234 };
235
236 soc@1c00000 {
237 compatible = "simple-bus";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges;
241
242 sram-controller@1c00000 {
243 compatible = "allwinner,sun4i-a10-sram-controller";
244 reg = <0x01c00000 0x30>;
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges;
248
249 sram_a: sram@0 {
250 compatible = "mmio-sram";
251 reg = <0x00000000 0xc000>;
252 #address-cells = <1>;
253 #size-cells = <1>;
254 ranges = <0 0x00000000 0xc000>;
255
256 emac_sram: sram-section@8000 {
257 compatible = "allwinner,sun4i-a10-sram-a3-a4";
258 reg = <0x8000 0x4000>;
259 status = "disabled";
260 };
261 };
262
263 sram_d: sram@10000 {
264 compatible = "mmio-sram";
265 reg = <0x00010000 0x1000>;
266 #address-cells = <1>;
267 #size-cells = <1>;
268 ranges = <0 0x00010000 0x1000>;
269
270 otg_sram: sram-section@0 {
271 compatible = "allwinner,sun4i-a10-sram-d";
272 reg = <0x0000 0x1000>;
273 status = "disabled";
274 };
275 };
276 };
277
278 nmi_intc: interrupt-controller@1c00030 {
279 compatible = "allwinner,sun7i-a20-sc-nmi";
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 reg = <0x01c00030 0x0c>;
283 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
284 };
285
286 dma: dma-controller@1c02000 {
287 compatible = "allwinner,sun4i-a10-dma";
288 reg = <0x01c02000 0x1000>;
289 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&ccu CLK_AHB_DMA>;
291 #dma-cells = <2>;
292 };
293
294 nfc: nand@1c03000 {
295 compatible = "allwinner,sun4i-a10-nand";
296 reg = <0x01c03000 0x1000>;
297 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
299 clock-names = "ahb", "mod";
300 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
301 dma-names = "rxtx";
302 status = "disabled";
303 #address-cells = <1>;
304 #size-cells = <0>;
305 };
306
307 spi0: spi@1c05000 {
308 compatible = "allwinner,sun4i-a10-spi";
309 reg = <0x01c05000 0x1000>;
310 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
312 clock-names = "ahb", "mod";
313 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
314 <&dma SUN4I_DMA_DEDICATED 26>;
315 dma-names = "rx", "tx";
316 status = "disabled";
317 #address-cells = <1>;
318 #size-cells = <0>;
319 num-cs = <4>;
320 };
321
322 spi1: spi@1c06000 {
323 compatible = "allwinner,sun4i-a10-spi";
324 reg = <0x01c06000 0x1000>;
325 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
327 clock-names = "ahb", "mod";
328 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
329 <&dma SUN4I_DMA_DEDICATED 8>;
330 dma-names = "rx", "tx";
331 status = "disabled";
332 #address-cells = <1>;
333 #size-cells = <0>;
334 num-cs = <1>;
335 };
336
337 emac: ethernet@1c0b000 {
338 compatible = "allwinner,sun4i-a10-emac";
339 reg = <0x01c0b000 0x1000>;
340 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&ccu CLK_AHB_EMAC>;
342 allwinner,sram = <&emac_sram 1>;
343 status = "disabled";
344 };
345
346 mdio: mdio@1c0b080 {
347 compatible = "allwinner,sun4i-a10-mdio";
348 reg = <0x01c0b080 0x14>;
349 status = "disabled";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 };
353
354 tcon0: lcd-controller@1c0c000 {
355 compatible = "allwinner,sun7i-a20-tcon";
356 reg = <0x01c0c000 0x1000>;
357 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
358 resets = <&ccu RST_TCON0>;
359 reset-names = "lcd";
360 clocks = <&ccu CLK_AHB_LCD0>,
361 <&ccu CLK_TCON0_CH0>,
362 <&ccu CLK_TCON0_CH1>;
363 clock-names = "ahb",
364 "tcon-ch0",
365 "tcon-ch1";
366 clock-output-names = "tcon0-pixel-clock";
367 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
368
369 ports {
370 #address-cells = <1>;
371 #size-cells = <0>;
372
373 tcon0_in: port@0 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 reg = <0>;
377
378 tcon0_in_be0: endpoint@0 {
379 reg = <0>;
380 remote-endpoint = <&be0_out_tcon0>;
381 };
382
383 tcon0_in_be1: endpoint@1 {
384 reg = <1>;
385 remote-endpoint = <&be1_out_tcon0>;
386 };
387 };
388
389 tcon0_out: port@1 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 reg = <1>;
393
394 tcon0_out_hdmi: endpoint@1 {
395 reg = <1>;
396 remote-endpoint = <&hdmi_in_tcon0>;
397 allwinner,tcon-channel = <1>;
398 };
399 };
400 };
401 };
402
403 tcon1: lcd-controller@1c0d000 {
404 compatible = "allwinner,sun7i-a20-tcon";
405 reg = <0x01c0d000 0x1000>;
406 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
407 resets = <&ccu RST_TCON1>;
408 reset-names = "lcd";
409 clocks = <&ccu CLK_AHB_LCD1>,
410 <&ccu CLK_TCON1_CH0>,
411 <&ccu CLK_TCON1_CH1>;
412 clock-names = "ahb",
413 "tcon-ch0",
414 "tcon-ch1";
415 clock-output-names = "tcon1-pixel-clock";
416 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
417
418 ports {
419 #address-cells = <1>;
420 #size-cells = <0>;
421
422 tcon1_in: port@0 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 reg = <0>;
426
427 tcon1_in_be0: endpoint@0 {
428 reg = <0>;
429 remote-endpoint = <&be0_out_tcon1>;
430 };
431
432 tcon1_in_be1: endpoint@1 {
433 reg = <1>;
434 remote-endpoint = <&be1_out_tcon1>;
435 };
436 };
437
438 tcon1_out: port@1 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 reg = <1>;
442
443 tcon1_out_hdmi: endpoint@1 {
444 reg = <1>;
445 remote-endpoint = <&hdmi_in_tcon1>;
446 allwinner,tcon-channel = <1>;
447 };
448 };
449 };
450 };
451
452 mmc0: mmc@1c0f000 {
453 compatible = "allwinner,sun7i-a20-mmc";
454 reg = <0x01c0f000 0x1000>;
455 clocks = <&ccu CLK_AHB_MMC0>,
456 <&ccu CLK_MMC0>,
457 <&ccu CLK_MMC0_OUTPUT>,
458 <&ccu CLK_MMC0_SAMPLE>;
459 clock-names = "ahb",
460 "mmc",
461 "output",
462 "sample";
463 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
464 status = "disabled";
465 #address-cells = <1>;
466 #size-cells = <0>;
467 };
468
469 mmc1: mmc@1c10000 {
470 compatible = "allwinner,sun7i-a20-mmc";
471 reg = <0x01c10000 0x1000>;
472 clocks = <&ccu CLK_AHB_MMC1>,
473 <&ccu CLK_MMC1>,
474 <&ccu CLK_MMC1_OUTPUT>,
475 <&ccu CLK_MMC1_SAMPLE>;
476 clock-names = "ahb",
477 "mmc",
478 "output",
479 "sample";
480 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
481 status = "disabled";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 };
485
486 mmc2: mmc@1c11000 {
487 compatible = "allwinner,sun7i-a20-mmc";
488 reg = <0x01c11000 0x1000>;
489 clocks = <&ccu CLK_AHB_MMC2>,
490 <&ccu CLK_MMC2>,
491 <&ccu CLK_MMC2_OUTPUT>,
492 <&ccu CLK_MMC2_SAMPLE>;
493 clock-names = "ahb",
494 "mmc",
495 "output",
496 "sample";
497 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
498 status = "disabled";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 };
502
503 mmc3: mmc@1c12000 {
504 compatible = "allwinner,sun7i-a20-mmc";
505 reg = <0x01c12000 0x1000>;
506 clocks = <&ccu CLK_AHB_MMC3>,
507 <&ccu CLK_MMC3>,
508 <&ccu CLK_MMC3_OUTPUT>,
509 <&ccu CLK_MMC3_SAMPLE>;
510 clock-names = "ahb",
511 "mmc",
512 "output",
513 "sample";
514 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
515 status = "disabled";
516 #address-cells = <1>;
517 #size-cells = <0>;
518 };
519
520 usb_otg: usb@1c13000 {
521 compatible = "allwinner,sun4i-a10-musb";
522 reg = <0x01c13000 0x0400>;
523 clocks = <&ccu CLK_AHB_OTG>;
524 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
525 interrupt-names = "mc";
526 phys = <&usbphy 0>;
527 phy-names = "usb";
528 extcon = <&usbphy 0>;
529 allwinner,sram = <&otg_sram 1>;
530 status = "disabled";
531 };
532
533 usbphy: phy@1c13400 {
534 #phy-cells = <1>;
535 compatible = "allwinner,sun7i-a20-usb-phy";
536 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
537 reg-names = "phy_ctrl", "pmu1", "pmu2";
538 clocks = <&ccu CLK_USB_PHY>;
539 clock-names = "usb_phy";
540 resets = <&ccu RST_USB_PHY0>,
541 <&ccu RST_USB_PHY1>,
542 <&ccu RST_USB_PHY2>;
543 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
544 status = "disabled";
545 };
546
547 ehci0: usb@1c14000 {
548 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
549 reg = <0x01c14000 0x100>;
550 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&ccu CLK_AHB_EHCI0>;
552 phys = <&usbphy 1>;
553 phy-names = "usb";
554 status = "disabled";
555 };
556
557 ohci0: usb@1c14400 {
558 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
559 reg = <0x01c14400 0x100>;
560 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
562 phys = <&usbphy 1>;
563 phy-names = "usb";
564 status = "disabled";
565 };
566
567 crypto: crypto-engine@1c15000 {
568 compatible = "allwinner,sun7i-a20-crypto",
569 "allwinner,sun4i-a10-crypto";
570 reg = <0x01c15000 0x1000>;
571 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
573 clock-names = "ahb", "mod";
574 };
575
576 hdmi: hdmi@1c16000 {
577 compatible = "allwinner,sun7i-a20-hdmi",
578 "allwinner,sun5i-a10s-hdmi";
579 reg = <0x01c16000 0x1000>;
580 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
582 <&ccu CLK_PLL_VIDEO0_2X>,
583 <&ccu CLK_PLL_VIDEO1_2X>;
584 clock-names = "ahb", "mod", "pll-0", "pll-1";
585 dmas = <&dma SUN4I_DMA_NORMAL 16>,
586 <&dma SUN4I_DMA_NORMAL 16>,
587 <&dma SUN4I_DMA_DEDICATED 24>;
588 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
589 status = "disabled";
590
591 ports {
592 #address-cells = <1>;
593 #size-cells = <0>;
594
595 hdmi_in: port@0 {
596 #address-cells = <1>;
597 #size-cells = <0>;
598 reg = <0>;
599
600 hdmi_in_tcon0: endpoint@0 {
601 reg = <0>;
602 remote-endpoint = <&tcon0_out_hdmi>;
603 };
604
605 hdmi_in_tcon1: endpoint@1 {
606 reg = <1>;
607 remote-endpoint = <&tcon1_out_hdmi>;
608 };
609 };
610
611 hdmi_out: port@1 {
612 #address-cells = <1>;
613 #size-cells = <0>;
614 reg = <1>;
615 };
616 };
617 };
618
619 spi2: spi@1c17000 {
620 compatible = "allwinner,sun4i-a10-spi";
621 reg = <0x01c17000 0x1000>;
622 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
624 clock-names = "ahb", "mod";
625 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
626 <&dma SUN4I_DMA_DEDICATED 28>;
627 dma-names = "rx", "tx";
628 status = "disabled";
629 #address-cells = <1>;
630 #size-cells = <0>;
631 num-cs = <1>;
632 };
633
634 ahci: sata@1c18000 {
635 compatible = "allwinner,sun4i-a10-ahci";
636 reg = <0x01c18000 0x1000>;
637 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
639 status = "disabled";
640 };
641
642 ehci1: usb@1c1c000 {
643 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
644 reg = <0x01c1c000 0x100>;
645 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&ccu CLK_AHB_EHCI1>;
647 phys = <&usbphy 2>;
648 phy-names = "usb";
649 status = "disabled";
650 };
651
652 ohci1: usb@1c1c400 {
653 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
654 reg = <0x01c1c400 0x100>;
655 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
657 phys = <&usbphy 2>;
658 phy-names = "usb";
659 status = "disabled";
660 };
661
662 spi3: spi@1c1f000 {
663 compatible = "allwinner,sun4i-a10-spi";
664 reg = <0x01c1f000 0x1000>;
665 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
667 clock-names = "ahb", "mod";
668 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
669 <&dma SUN4I_DMA_DEDICATED 30>;
670 dma-names = "rx", "tx";
671 status = "disabled";
672 #address-cells = <1>;
673 #size-cells = <0>;
674 num-cs = <1>;
675 };
676
677 ccu: clock@1c20000 {
678 compatible = "allwinner,sun7i-a20-ccu";
679 reg = <0x01c20000 0x400>;
680 clocks = <&osc24M>, <&osc32k>;
681 clock-names = "hosc", "losc";
682 #clock-cells = <1>;
683 #reset-cells = <1>;
684 };
685
686 pio: pinctrl@1c20800 {
687 compatible = "allwinner,sun7i-a20-pinctrl";
688 reg = <0x01c20800 0x400>;
689 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
691 clock-names = "apb", "hosc", "losc";
692 gpio-controller;
693 interrupt-controller;
694 #interrupt-cells = <3>;
695 #gpio-cells = <3>;
696
697 can0_pins_a: can0@0 {
698 pins = "PH20", "PH21";
699 function = "can";
700 };
701
702 clk_out_a_pins_a: clk_out_a@0 {
703 pins = "PI12";
704 function = "clk_out_a";
705 };
706
707 clk_out_b_pins_a: clk_out_b@0 {
708 pins = "PI13";
709 function = "clk_out_b";
710 };
711
712 emac_pins_a: emac0@0 {
713 pins = "PA0", "PA1", "PA2",
714 "PA3", "PA4", "PA5", "PA6",
715 "PA7", "PA8", "PA9", "PA10",
716 "PA11", "PA12", "PA13", "PA14",
717 "PA15", "PA16";
718 function = "emac";
719 };
720
721 gmac_pins_mii_a: gmac_mii@0 {
722 pins = "PA0", "PA1", "PA2",
723 "PA3", "PA4", "PA5", "PA6",
724 "PA7", "PA8", "PA9", "PA10",
725 "PA11", "PA12", "PA13", "PA14",
726 "PA15", "PA16";
727 function = "gmac";
728 };
729
730 gmac_pins_rgmii_a: gmac_rgmii@0 {
731 pins = "PA0", "PA1", "PA2",
732 "PA3", "PA4", "PA5", "PA6",
733 "PA7", "PA8", "PA10",
734 "PA11", "PA12", "PA13",
735 "PA15", "PA16";
736 function = "gmac";
737 /*
738 * data lines in RGMII mode use DDR mode
739 * and need a higher signal drive strength
740 */
741 drive-strength = <40>;
742 };
743
744 i2c0_pins_a: i2c0@0 {
745 pins = "PB0", "PB1";
746 function = "i2c0";
747 };
748
749 i2c1_pins_a: i2c1@0 {
750 pins = "PB18", "PB19";
751 function = "i2c1";
752 };
753
754 i2c2_pins_a: i2c2@0 {
755 pins = "PB20", "PB21";
756 function = "i2c2";
757 };
758
759 i2c3_pins_a: i2c3@0 {
760 pins = "PI0", "PI1";
761 function = "i2c3";
762 };
763
764 ir0_rx_pins_a: ir0@0 {
765 pins = "PB4";
766 function = "ir0";
767 };
768
769 ir0_tx_pins_a: ir0@1 {
770 pins = "PB3";
771 function = "ir0";
772 };
773
774 ir1_rx_pins_a: ir1@0 {
775 pins = "PB23";
776 function = "ir1";
777 };
778
779 ir1_tx_pins_a: ir1@1 {
780 pins = "PB22";
781 function = "ir1";
782 };
783
784 mmc0_pins_a: mmc0@0 {
785 pins = "PF0", "PF1", "PF2",
786 "PF3", "PF4", "PF5";
787 function = "mmc0";
788 drive-strength = <30>;
789 bias-pull-up;
790 };
791
792 mmc2_pins_a: mmc2@0 {
793 pins = "PC6", "PC7", "PC8",
794 "PC9", "PC10", "PC11";
795 function = "mmc2";
796 drive-strength = <30>;
797 bias-pull-up;
798 };
799
800 mmc3_pins_a: mmc3@0 {
801 pins = "PI4", "PI5", "PI6",
802 "PI7", "PI8", "PI9";
803 function = "mmc3";
804 drive-strength = <30>;
805 bias-pull-up;
806 };
807
808 ps20_pins_a: ps20@0 {
809 pins = "PI20", "PI21";
810 function = "ps2";
811 };
812
813 ps21_pins_a: ps21@0 {
814 pins = "PH12", "PH13";
815 function = "ps2";
816 };
817
818 pwm0_pins_a: pwm0@0 {
819 pins = "PB2";
820 function = "pwm";
821 };
822
823 pwm1_pins_a: pwm1@0 {
824 pins = "PI3";
825 function = "pwm";
826 };
827
828 spdif_tx_pins_a: spdif@0 {
829 pins = "PB13";
830 function = "spdif";
831 bias-pull-up;
832 };
833
834 spi0_pins_a: spi0@0 {
835 pins = "PI11", "PI12", "PI13";
836 function = "spi0";
837 };
838
839 spi0_cs0_pins_a: spi0_cs0@0 {
840 pins = "PI10";
841 function = "spi0";
842 };
843
844 spi0_cs1_pins_a: spi0_cs1@0 {
845 pins = "PI14";
846 function = "spi0";
847 };
848
849 spi1_pins_a: spi1@0 {
850 pins = "PI17", "PI18", "PI19";
851 function = "spi1";
852 };
853
854 spi1_cs0_pins_a: spi1_cs0@0 {
855 pins = "PI16";
856 function = "spi1";
857 };
858
859 spi2_pins_a: spi2@0 {
860 pins = "PC20", "PC21", "PC22";
861 function = "spi2";
862 };
863
864 spi2_pins_b: spi2@1 {
865 pins = "PB15", "PB16", "PB17";
866 function = "spi2";
867 };
868
869 spi2_cs0_pins_a: spi2_cs0@0 {
870 pins = "PC19";
871 function = "spi2";
872 };
873
874 spi2_cs0_pins_b: spi2_cs0@1 {
875 pins = "PB14";
876 function = "spi2";
877 };
878
879 uart0_pins_a: uart0@0 {
880 pins = "PB22", "PB23";
881 function = "uart0";
882 };
883
884 uart2_pins_a: uart2@0 {
885 pins = "PI16", "PI17", "PI18", "PI19";
886 function = "uart2";
887 };
888
889 uart3_pins_a: uart3@0 {
890 pins = "PG6", "PG7", "PG8", "PG9";
891 function = "uart3";
892 };
893
894 uart3_pins_b: uart3@1 {
895 pins = "PH0", "PH1";
896 function = "uart3";
897 };
898
899 uart4_pins_a: uart4@0 {
900 pins = "PG10", "PG11";
901 function = "uart4";
902 };
903
904 uart4_pins_b: uart4@1 {
905 pins = "PH4", "PH5";
906 function = "uart4";
907 };
908
909 uart5_pins_a: uart5@0 {
910 pins = "PI10", "PI11";
911 function = "uart5";
912 };
913
914 uart6_pins_a: uart6@0 {
915 pins = "PI12", "PI13";
916 function = "uart6";
917 };
918
919 uart7_pins_a: uart7@0 {
920 pins = "PI20", "PI21";
921 function = "uart7";
922 };
923 };
924
925 timer@1c20c00 {
926 compatible = "allwinner,sun4i-a10-timer";
927 reg = <0x01c20c00 0x90>;
928 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&osc24M>;
935 };
936
937 wdt: watchdog@1c20c90 {
938 compatible = "allwinner,sun4i-a10-wdt";
939 reg = <0x01c20c90 0x10>;
940 };
941
942 rtc: rtc@1c20d00 {
943 compatible = "allwinner,sun7i-a20-rtc";
944 reg = <0x01c20d00 0x20>;
945 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
946 };
947
948 pwm: pwm@1c20e00 {
949 compatible = "allwinner,sun7i-a20-pwm";
950 reg = <0x01c20e00 0xc>;
951 clocks = <&osc24M>;
952 #pwm-cells = <3>;
953 status = "disabled";
954 };
955
956 spdif: spdif@1c21000 {
957 #sound-dai-cells = <0>;
958 compatible = "allwinner,sun4i-a10-spdif";
959 reg = <0x01c21000 0x400>;
960 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
962 clock-names = "apb", "spdif";
963 dmas = <&dma SUN4I_DMA_NORMAL 2>,
964 <&dma SUN4I_DMA_NORMAL 2>;
965 dma-names = "rx", "tx";
966 status = "disabled";
967 };
968
969 ir0: ir@1c21800 {
970 compatible = "allwinner,sun4i-a10-ir";
971 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
972 clock-names = "apb", "ir";
973 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
974 reg = <0x01c21800 0x40>;
975 status = "disabled";
976 };
977
978 ir1: ir@1c21c00 {
979 compatible = "allwinner,sun4i-a10-ir";
980 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
981 clock-names = "apb", "ir";
982 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
983 reg = <0x01c21c00 0x40>;
984 status = "disabled";
985 };
986
987 i2s1: i2s@1c22000 {
988 #sound-dai-cells = <0>;
989 compatible = "allwinner,sun4i-a10-i2s";
990 reg = <0x01c22000 0x400>;
991 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
993 clock-names = "apb", "mod";
994 dmas = <&dma SUN4I_DMA_NORMAL 4>,
995 <&dma SUN4I_DMA_NORMAL 4>;
996 dma-names = "rx", "tx";
997 status = "disabled";
998 };
999
1000 i2s0: i2s@1c22400 {
1001 #sound-dai-cells = <0>;
1002 compatible = "allwinner,sun4i-a10-i2s";
1003 reg = <0x01c22400 0x400>;
1004 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1006 clock-names = "apb", "mod";
1007 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1008 <&dma SUN4I_DMA_NORMAL 3>;
1009 dma-names = "rx", "tx";
1010 status = "disabled";
1011 };
1012
1013 lradc: lradc@1c22800 {
1014 compatible = "allwinner,sun4i-a10-lradc-keys";
1015 reg = <0x01c22800 0x100>;
1016 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1017 status = "disabled";
1018 };
1019
1020 codec: codec@1c22c00 {
1021 #sound-dai-cells = <0>;
1022 compatible = "allwinner,sun7i-a20-codec";
1023 reg = <0x01c22c00 0x40>;
1024 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1026 clock-names = "apb", "codec";
1027 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1028 <&dma SUN4I_DMA_NORMAL 19>;
1029 dma-names = "rx", "tx";
1030 status = "disabled";
1031 };
1032
1033 sid: eeprom@1c23800 {
1034 compatible = "allwinner,sun7i-a20-sid";
1035 reg = <0x01c23800 0x200>;
1036 };
1037
1038 i2s2: i2s@1c24400 {
1039 #sound-dai-cells = <0>;
1040 compatible = "allwinner,sun4i-a10-i2s";
1041 reg = <0x01c24400 0x400>;
1042 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1044 clock-names = "apb", "mod";
1045 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1046 <&dma SUN4I_DMA_NORMAL 6>;
1047 dma-names = "rx", "tx";
1048 status = "disabled";
1049 };
1050
1051 rtp: rtp@1c25000 {
1052 compatible = "allwinner,sun5i-a13-ts";
1053 reg = <0x01c25000 0x100>;
1054 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1055 #thermal-sensor-cells = <0>;
1056 };
1057
1058 uart0: serial@1c28000 {
1059 compatible = "snps,dw-apb-uart";
1060 reg = <0x01c28000 0x400>;
1061 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1062 reg-shift = <2>;
1063 reg-io-width = <4>;
1064 clocks = <&ccu CLK_APB1_UART0>;
1065 status = "disabled";
1066 };
1067
1068 uart1: serial@1c28400 {
1069 compatible = "snps,dw-apb-uart";
1070 reg = <0x01c28400 0x400>;
1071 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1072 reg-shift = <2>;
1073 reg-io-width = <4>;
1074 clocks = <&ccu CLK_APB1_UART1>;
1075 status = "disabled";
1076 };
1077
1078 uart2: serial@1c28800 {
1079 compatible = "snps,dw-apb-uart";
1080 reg = <0x01c28800 0x400>;
1081 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1082 reg-shift = <2>;
1083 reg-io-width = <4>;
1084 clocks = <&ccu CLK_APB1_UART2>;
1085 status = "disabled";
1086 };
1087
1088 uart3: serial@1c28c00 {
1089 compatible = "snps,dw-apb-uart";
1090 reg = <0x01c28c00 0x400>;
1091 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1092 reg-shift = <2>;
1093 reg-io-width = <4>;
1094 clocks = <&ccu CLK_APB1_UART3>;
1095 status = "disabled";
1096 };
1097
1098 uart4: serial@1c29000 {
1099 compatible = "snps,dw-apb-uart";
1100 reg = <0x01c29000 0x400>;
1101 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1102 reg-shift = <2>;
1103 reg-io-width = <4>;
1104 clocks = <&ccu CLK_APB1_UART4>;
1105 status = "disabled";
1106 };
1107
1108 uart5: serial@1c29400 {
1109 compatible = "snps,dw-apb-uart";
1110 reg = <0x01c29400 0x400>;
1111 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1112 reg-shift = <2>;
1113 reg-io-width = <4>;
1114 clocks = <&ccu CLK_APB1_UART5>;
1115 status = "disabled";
1116 };
1117
1118 uart6: serial@1c29800 {
1119 compatible = "snps,dw-apb-uart";
1120 reg = <0x01c29800 0x400>;
1121 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1122 reg-shift = <2>;
1123 reg-io-width = <4>;
1124 clocks = <&ccu CLK_APB1_UART6>;
1125 status = "disabled";
1126 };
1127
1128 uart7: serial@1c29c00 {
1129 compatible = "snps,dw-apb-uart";
1130 reg = <0x01c29c00 0x400>;
1131 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1132 reg-shift = <2>;
1133 reg-io-width = <4>;
1134 clocks = <&ccu CLK_APB1_UART7>;
1135 status = "disabled";
1136 };
1137
1138 ps20: ps2@1c2a000 {
1139 compatible = "allwinner,sun4i-a10-ps2";
1140 reg = <0x01c2a000 0x400>;
1141 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&ccu CLK_APB1_PS20>;
1143 status = "disabled";
1144 };
1145
1146 ps21: ps2@1c2a400 {
1147 compatible = "allwinner,sun4i-a10-ps2";
1148 reg = <0x01c2a400 0x400>;
1149 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&ccu CLK_APB1_PS21>;
1151 status = "disabled";
1152 };
1153
1154 i2c0: i2c@1c2ac00 {
1155 compatible = "allwinner,sun7i-a20-i2c",
1156 "allwinner,sun4i-a10-i2c";
1157 reg = <0x01c2ac00 0x400>;
1158 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1159 clocks = <&ccu CLK_APB1_I2C0>;
1160 status = "disabled";
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163 };
1164
1165 i2c1: i2c@1c2b000 {
1166 compatible = "allwinner,sun7i-a20-i2c",
1167 "allwinner,sun4i-a10-i2c";
1168 reg = <0x01c2b000 0x400>;
1169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&ccu CLK_APB1_I2C1>;
1171 status = "disabled";
1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 };
1175
1176 i2c2: i2c@1c2b400 {
1177 compatible = "allwinner,sun7i-a20-i2c",
1178 "allwinner,sun4i-a10-i2c";
1179 reg = <0x01c2b400 0x400>;
1180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&ccu CLK_APB1_I2C2>;
1182 status = "disabled";
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 };
1186
1187 i2c3: i2c@1c2b800 {
1188 compatible = "allwinner,sun7i-a20-i2c",
1189 "allwinner,sun4i-a10-i2c";
1190 reg = <0x01c2b800 0x400>;
1191 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&ccu CLK_APB1_I2C3>;
1193 status = "disabled";
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1196 };
1197
1198 can0: can@1c2bc00 {
1199 compatible = "allwinner,sun7i-a20-can",
1200 "allwinner,sun4i-a10-can";
1201 reg = <0x01c2bc00 0x400>;
1202 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&ccu CLK_APB1_CAN>;
1204 status = "disabled";
1205 };
1206
1207 i2c4: i2c@1c2c000 {
1208 compatible = "allwinner,sun7i-a20-i2c",
1209 "allwinner,sun4i-a10-i2c";
1210 reg = <0x01c2c000 0x400>;
1211 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1212 clocks = <&ccu CLK_APB1_I2C4>;
1213 status = "disabled";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 };
1217
1218 mali: gpu@1c40000 {
1219 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1220 reg = <0x01c40000 0x10000>;
1221 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1228 interrupt-names = "gp",
1229 "gpmmu",
1230 "pp0",
1231 "ppmmu0",
1232 "pp1",
1233 "ppmmu1",
1234 "pmu";
1235 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1236 clock-names = "bus", "core";
1237 resets = <&ccu RST_GPU>;
1238
1239 assigned-clocks = <&ccu CLK_GPU>;
1240 assigned-clock-rates = <384000000>;
1241 };
1242
1243 gmac: ethernet@1c50000 {
1244 compatible = "allwinner,sun7i-a20-gmac";
1245 reg = <0x01c50000 0x10000>;
1246 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1247 interrupt-names = "macirq";
1248 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1249 clock-names = "stmmaceth", "allwinner_gmac_tx";
1250 snps,pbl = <2>;
1251 snps,fixed-burst;
1252 snps,force_sf_dma_mode;
1253 status = "disabled";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1256 };
1257
1258 hstimer@1c60000 {
1259 compatible = "allwinner,sun7i-a20-hstimer";
1260 reg = <0x01c60000 0x1000>;
1261 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1265 clocks = <&ccu CLK_AHB_HSTIMER>;
1266 };
1267
1268 gic: interrupt-controller@1c81000 {
1269 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1270 reg = <0x01c81000 0x1000>,
1271 <0x01c82000 0x2000>,
1272 <0x01c84000 0x2000>,
1273 <0x01c86000 0x2000>;
1274 interrupt-controller;
1275 #interrupt-cells = <3>;
1276 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1277 };
1278
1279 fe0: display-frontend@1e00000 {
1280 compatible = "allwinner,sun7i-a20-display-frontend";
1281 reg = <0x01e00000 0x20000>;
1282 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1284 <&ccu CLK_DRAM_DE_FE0>;
1285 clock-names = "ahb", "mod",
1286 "ram";
1287 resets = <&ccu RST_DE_FE0>;
1288
1289 ports {
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1292
1293 fe0_out: port@1 {
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1296 reg = <1>;
1297
1298 fe0_out_be0: endpoint@0 {
1299 reg = <0>;
1300 remote-endpoint = <&be0_in_fe0>;
1301 };
1302
1303 fe0_out_be1: endpoint@1 {
1304 reg = <1>;
1305 remote-endpoint = <&be1_in_fe0>;
1306 };
1307 };
1308 };
1309 };
1310
1311 fe1: display-frontend@1e20000 {
1312 compatible = "allwinner,sun7i-a20-display-frontend";
1313 reg = <0x01e20000 0x20000>;
1314 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1315 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1316 <&ccu CLK_DRAM_DE_FE1>;
1317 clock-names = "ahb", "mod",
1318 "ram";
1319 resets = <&ccu RST_DE_FE1>;
1320
1321 ports {
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1324
1325 fe1_out: port@1 {
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328 reg = <1>;
1329
1330 fe1_out_be0: endpoint@0 {
1331 reg = <0>;
1332 remote-endpoint = <&be0_in_fe1>;
1333 };
1334
1335 fe1_out_be1: endpoint@1 {
1336 reg = <1>;
1337 remote-endpoint = <&be1_in_fe1>;
1338 };
1339 };
1340 };
1341 };
1342
1343 be1: display-backend@1e40000 {
1344 compatible = "allwinner,sun7i-a20-display-backend";
1345 reg = <0x01e40000 0x10000>;
1346 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1348 <&ccu CLK_DRAM_DE_BE1>;
1349 clock-names = "ahb", "mod",
1350 "ram";
1351 resets = <&ccu RST_DE_BE1>;
1352
1353 ports {
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1356
1357 be1_in: port@0 {
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360 reg = <0>;
1361
1362 be1_in_fe0: endpoint@0 {
1363 reg = <0>;
1364 remote-endpoint = <&fe0_out_be1>;
1365 };
1366
1367 be1_in_fe1: endpoint@1 {
1368 reg = <1>;
1369 remote-endpoint = <&fe1_out_be1>;
1370 };
1371 };
1372
1373 be1_out: port@1 {
1374 #address-cells = <1>;
1375 #size-cells = <0>;
1376 reg = <1>;
1377
1378 be1_out_tcon0: endpoint@0 {
1379 reg = <0>;
1380 remote-endpoint = <&tcon0_in_be1>;
1381 };
1382
1383 be1_out_tcon1: endpoint@1 {
1384 reg = <1>;
1385 remote-endpoint = <&tcon1_in_be1>;
1386 };
1387 };
1388 };
1389 };
1390
1391 be0: display-backend@1e60000 {
1392 compatible = "allwinner,sun7i-a20-display-backend";
1393 reg = <0x01e60000 0x10000>;
1394 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1396 <&ccu CLK_DRAM_DE_BE0>;
1397 clock-names = "ahb", "mod",
1398 "ram";
1399 resets = <&ccu RST_DE_BE0>;
1400
1401 ports {
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1404
1405 be0_in: port@0 {
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1408 reg = <0>;
1409
1410 be0_in_fe0: endpoint@0 {
1411 reg = <0>;
1412 remote-endpoint = <&fe0_out_be0>;
1413 };
1414
1415 be0_in_fe1: endpoint@1 {
1416 reg = <1>;
1417 remote-endpoint = <&fe1_out_be0>;
1418 };
1419 };
1420
1421 be0_out: port@1 {
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1424 reg = <1>;
1425
1426 be0_out_tcon0: endpoint@0 {
1427 reg = <0>;
1428 remote-endpoint = <&tcon0_in_be0>;
1429 };
1430
1431 be0_out_tcon1: endpoint@1 {
1432 reg = <1>;
1433 remote-endpoint = <&tcon1_in_be0>;
1434 };
1435 };
1436 };
1437 };
1438 };
1439};