1/*
  2 * Common Device Tree Source for IGEP COM MODULE
  3 *
  4 * Copyright (C) 2014 Javier Martinez Canillas <javier@osg.samsung.com>
  5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License version 2 as
  9 * published by the Free Software Foundation.
 10 */
 11
 12#include "omap3-igep.dtsi"
 13
 14/ {
 15	leds: gpio_leds {
 16		compatible = "gpio-leds";
 17
 18		user0 {
 19			 label = "omap3:red:user0";
 20			 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;	/* LEDA */
 21			 default-state = "off";
 22		};
 23
 24		user1 {
 25			 label = "omap3:green:user1";
 26			 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;	/* LEDB */
 27			 default-state = "off";
 28		};
 29
 30		user2 {
 31			 label = "omap3:red:user1";
 32			 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;		/* gpio_16 */
 33			 default-state = "off";
 34		};
 35	};
 36
 37	hsusb2_phy: hsusb2_phy {
 38		compatible = "usb-nop-xceiv";
 39		reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;		/* gpio_54 */
 40		#phy-cells = <0>;
 41	};
 42};
 43
 44&omap3_pmx_core {
 45	pinctrl-names = "default";
 46	pinctrl-0 = <&hsusb2_pins>;
 47
 48	hsusb2_pins: pinmux_hsusb2_pins {
 49		pinctrl-single,pins = <
 50			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
 51			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
 52			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
 53			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
 54			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
 55			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
 56		>;
 57	};
 58
 59	uart2_pins: pinmux_uart2_pins {
 60		pinctrl-single,pins = <
 61			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */
 62			OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_dr.uart2_rts */
 63			OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_clk.uart2_tx */
 64			OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)	/* mcbsp3_fsx.uart2_rx */
 65		>;
 66	};
 67};
 68
 69&omap3_pmx_core2 {
 70	pinctrl-names = "default";
 71	pinctrl-0 = <&hsusb2_core2_pins>;
 72
 73	hsusb2_core2_pins: pinmux_hsusb2_core2_pins {
 74		pinctrl-single,pins = <
 75			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		      /* etk_d10.hsusb2_clk */
 76			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		      /* etk_d11.hsusb2_stp */
 77			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
 78			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
 79			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
 80			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
 81		>;
 82	};
 83
 84	leds_core2_pins: pinmux_leds_core2_pins {
 85		pinctrl-single,pins = <
 86			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)	/* etk_d2.gpio_16 */
 87		>;
 88	};
 89};
 90
 91&usbhshost {
 92	port2-mode = "ehci-phy";
 93};
 94
 95&usbhsehci {
 96	phys = <0 &hsusb2_phy>;
 97};
 98
 99&uart2 {
100	pinctrl-names = "default";
101	pinctrl-0 = <&uart2_pins>;
102};
103
104&gpmc {
105	ranges = <0 0 0x30000000 0x01000000>;   /* CS0: 16MB for NAND */
106};