1/*
  2 * PHYTEC phyCORE-LPC3250 board
  3 *
  4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
  5 *
  6 * The code contained herein is licensed under the GNU General Public
  7 * License. You may obtain a copy of the GNU General Public License
  8 * Version 2 or later at the following locations:
  9 *
 10 * http://www.opensource.org/licenses/gpl-license.html
 11 * http://www.gnu.org/copyleft/gpl.html
 12 */
 13
 14/dts-v1/;
 15#include "lpc32xx.dtsi"
 16
 17/ {
 18	model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
 19	compatible = "phytec,phy3250", "nxp,lpc3250";
 20	#address-cells = <1>;
 21	#size-cells = <1>;
 22
 23	memory {
 24		device_type = "memory";
 25		reg = <0x80000000 0x4000000>;
 26	};
 27
 28	regulators {
 29		backlight_reg: regulator@0 {
 30			compatible = "regulator-fixed";
 31			regulator-name = "backlight_reg";
 32			regulator-min-microvolt = <1800000>;
 33			regulator-max-microvolt = <1800000>;
 34			gpio = <&gpio 5 4 0>;
 35			enable-active-high;
 36			regulator-boot-on;
 37		};
 38
 39		lcd_reg: regulator@1 {
 40			compatible = "regulator-fixed";
 41			regulator-name = "lcd_reg";
 42			regulator-min-microvolt = <1800000>;
 43			regulator-max-microvolt = <1800000>;
 44			gpio = <&gpio 5 0 0>;
 45			enable-active-high;
 46			regulator-boot-on;
 47		};
 48
 49		sd_reg: regulator@2 {
 50			compatible = "regulator-fixed";
 51			regulator-name = "sd_reg";
 52			regulator-min-microvolt = <1800000>;
 53			regulator-max-microvolt = <1800000>;
 54			gpio = <&gpio 5 5 0>;
 55			enable-active-high;
 56		};
 57	};
 58
 59	leds {
 60		compatible = "gpio-leds";
 61
 62		led0 { /* red */
 63			gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
 64			default-state = "off";
 65		};
 66
 67		led1 { /* green */
 68			gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
 69			linux,default-trigger = "heartbeat";
 70		};
 71	};
 72};
 73
 74&clcd {
 75	status = "okay";
 76};
 77
 78&i2c1 {
 79	clock-frequency = <100000>;
 80
 81	uda1380: uda1380@18 {
 82		compatible = "nxp,uda1380";
 83		reg = <0x18>;
 84		power-gpio = <&gpio 3 10 0>;
 85		reset-gpio = <&gpio 3 2 0>;
 86		dac-clk = "wspll";
 87	};
 88
 89	pcf8563: rtc@51 {
 90		compatible = "nxp,pcf8563";
 91		reg = <0x51>;
 92	};
 93};
 94
 95&i2c2 {
 96	clock-frequency = <100000>;
 97};
 98
 99&i2cusb {
100	clock-frequency = <100000>;
101
102	isp1301: usb-transceiver@2c {
103		compatible = "nxp,isp1301";
104		reg = <0x2c>;
105	};
106};
107
108&key {
109	keypad,num-rows = <1>;
110	keypad,num-columns = <1>;
111	nxp,debounce-delay-ms = <3>;
112	nxp,scan-delay-ms = <34>;
113	linux,keymap = <0x00000002>;
114	status = "okay";
115};
116
117&mac {
118	phy-mode = "rmii";
119	use-iram;
120};
121
122/* Here, choose exactly one from: ohci, usbd */
123&ohci /* &usbd */ {
124	transceiver = <&isp1301>;
125	status = "okay";
126};
127
128&sd {
129	wp-gpios = <&gpio 3 0 0>;
130	cd-gpios = <&gpio 3 1 0>;
131	cd-inverted;
132	bus-width = <4>;
133	vmmc-supply = <&sd_reg>;
134	status = "okay";
135};
136
137/* 64MB Flash via SLC NAND controller */
138&slc {
139	status = "okay";
140
141	nxp,wdr-clks = <14>;
142	nxp,wwidth = <40000000>;
143	nxp,whold = <100000000>;
144	nxp,wsetup = <100000000>;
145	nxp,rdr-clks = <14>;
146	nxp,rwidth = <40000000>;
147	nxp,rhold = <66666666>;
148	nxp,rsetup = <100000000>;
149	nand-on-flash-bbt;
150	gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
151
152	partitions {
153		compatible = "fixed-partitions";
154		#address-cells = <1>;
155		#size-cells = <1>;
156
157		mtd0@0 {
158			label = "phy3250-boot";
159			reg = <0x00000000 0x00064000>;
160			read-only;
161		};
162
163		mtd1@64000 {
164			label = "phy3250-uboot";
165			reg = <0x00064000 0x00190000>;
166			read-only;
167		};
168
169		mtd2@1f4000 {
170			label = "phy3250-ubt-prms";
171			reg = <0x001f4000 0x00010000>;
172		};
173
174		mtd3@204000 {
175			label = "phy3250-kernel";
176			reg = <0x00204000 0x00400000>;
177		};
178
179		mtd4@604000 {
180			label = "phy3250-rootfs";
181			reg = <0x00604000 0x039fc000>;
182		};
183	};
184};
185
186&ssp0 {
187	#address-cells = <1>;
188	#size-cells = <0>;
189	num-cs = <1>;
190	cs-gpios = <&gpio 3 5 0>;
191	status = "okay";
192
193	eeprom: at25@0 {
194		compatible = "atmel,at25";
195		reg = <0>;
196		spi-max-frequency = <5000000>;
197
198		pl022,interface = <0>;
199		pl022,com-mode = <0>;
200		pl022,rx-level-trig = <1>;
201		pl022,tx-level-trig = <1>;
202		pl022,ctrl-len = <11>;
203		pl022,wait-state = <0>;
204		pl022,duplex = <0>;
205
206		at25,byte-len = <0x8000>;
207		at25,addr-mode = <2>;
208		at25,page-size = <64>;
209	};
210};
211
212&tsc {
213	status = "okay";
214};
215
216&uart2 {
217	status = "okay";
218};
219
220&uart3 {
221	status = "okay";
222};
223
224&uart5 {
225	status = "okay";
226};