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1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6sx-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6sx-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; };
26
27 aliases {
28 can0 = &flexcan1;
29 can1 = &flexcan2;
30 ethernet0 = &fec1;
31 ethernet1 = &fec2;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 gpio6 = &gpio7;
39 i2c0 = &i2c1;
40 i2c1 = &i2c2;
41 i2c2 = &i2c3;
42 i2c3 = &i2c4;
43 mmc0 = &usdhc1;
44 mmc1 = &usdhc2;
45 mmc2 = &usdhc3;
46 mmc3 = &usdhc4;
47 serial0 = &uart1;
48 serial1 = &uart2;
49 serial2 = &uart3;
50 serial3 = &uart4;
51 serial4 = &uart5;
52 serial5 = &uart6;
53 spi0 = &ecspi1;
54 spi1 = &ecspi2;
55 spi2 = &ecspi3;
56 spi3 = &ecspi4;
57 spi4 = &ecspi5;
58 usbphy0 = &usbphy1;
59 usbphy1 = &usbphy2;
60 };
61
62 cpus {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 cpu0: cpu@0 {
67 compatible = "arm,cortex-a9";
68 device_type = "cpu";
69 reg = <0>;
70 next-level-cache = <&L2>;
71 operating-points = <
72 /* kHz uV */
73 996000 1250000
74 792000 1175000
75 396000 1075000
76 198000 975000
77 >;
78 fsl,soc-operating-points = <
79 /* ARM kHz SOC uV */
80 996000 1175000
81 792000 1175000
82 396000 1175000
83 198000 1175000
84 >;
85 clock-latency = <61036>; /* two CLK32 periods */
86 clocks = <&clks IMX6SX_CLK_ARM>,
87 <&clks IMX6SX_CLK_PLL2_PFD2>,
88 <&clks IMX6SX_CLK_STEP>,
89 <&clks IMX6SX_CLK_PLL1_SW>,
90 <&clks IMX6SX_CLK_PLL1_SYS>;
91 clock-names = "arm", "pll2_pfd2_396m", "step",
92 "pll1_sw", "pll1_sys";
93 arm-supply = <®_arm>;
94 soc-supply = <®_soc>;
95 };
96 };
97
98 intc: interrupt-controller@a01000 {
99 compatible = "arm,cortex-a9-gic";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x00a01000 0x1000>,
103 <0x00a00100 0x100>;
104 interrupt-parent = <&intc>;
105 };
106
107 clocks {
108 #address-cells = <1>;
109 #size-cells = <0>;
110
111 ckil: clock@0 {
112 compatible = "fixed-clock";
113 reg = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <32768>;
116 clock-output-names = "ckil";
117 };
118
119 osc: clock@1 {
120 compatible = "fixed-clock";
121 reg = <1>;
122 #clock-cells = <0>;
123 clock-frequency = <24000000>;
124 clock-output-names = "osc";
125 };
126
127 ipp_di0: clock@2 {
128 compatible = "fixed-clock";
129 reg = <2>;
130 #clock-cells = <0>;
131 clock-frequency = <0>;
132 clock-output-names = "ipp_di0";
133 };
134
135 ipp_di1: clock@3 {
136 compatible = "fixed-clock";
137 reg = <3>;
138 #clock-cells = <0>;
139 clock-frequency = <0>;
140 clock-output-names = "ipp_di1";
141 };
142 };
143
144 tempmon: tempmon {
145 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
146 interrupt-parent = <&gpc>;
147 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
148 fsl,tempmon = <&anatop>;
149 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
150 nvmem-cell-names = "calib", "temp_grade";
151 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
152 };
153
154 pmu {
155 compatible = "arm,cortex-a9-pmu";
156 interrupt-parent = <&gpc>;
157 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
158 };
159
160 soc {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "simple-bus";
164 interrupt-parent = <&gpc>;
165 ranges;
166
167 ocram: sram@900000 {
168 compatible = "mmio-sram";
169 reg = <0x00900000 0x20000>;
170 clocks = <&clks IMX6SX_CLK_OCRAM>;
171 };
172
173 L2: l2-cache@a02000 {
174 compatible = "arm,pl310-cache";
175 reg = <0x00a02000 0x1000>;
176 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
177 cache-unified;
178 cache-level = <2>;
179 arm,tag-latency = <4 2 3>;
180 arm,data-latency = <4 2 3>;
181 };
182
183 gpu: gpu@1800000 {
184 compatible = "vivante,gc";
185 reg = <0x01800000 0x4000>;
186 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clks IMX6SX_CLK_GPU>,
188 <&clks IMX6SX_CLK_GPU>,
189 <&clks IMX6SX_CLK_GPU>;
190 clock-names = "bus", "core", "shader";
191 power-domains = <&pd_pu>;
192 };
193
194 dma_apbh: dma-apbh@1804000 {
195 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
196 reg = <0x01804000 0x2000>;
197 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
202 #dma-cells = <1>;
203 dma-channels = <4>;
204 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
205 };
206
207 gpmi: gpmi-nand@1806000{
208 compatible = "fsl,imx6sx-gpmi-nand";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
212 reg-names = "gpmi-nand", "bch";
213 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
214 interrupt-names = "bch";
215 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
216 <&clks IMX6SX_CLK_GPMI_APB>,
217 <&clks IMX6SX_CLK_GPMI_BCH>,
218 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
219 <&clks IMX6SX_CLK_PER1_BCH>;
220 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
221 "gpmi_bch_apb", "per1_bch";
222 dmas = <&dma_apbh 0>;
223 dma-names = "rx-tx";
224 status = "disabled";
225 };
226
227 aips1: aips-bus@2000000 {
228 compatible = "fsl,aips-bus", "simple-bus";
229 #address-cells = <1>;
230 #size-cells = <1>;
231 reg = <0x02000000 0x100000>;
232 ranges;
233
234 spba-bus@2000000 {
235 compatible = "fsl,spba-bus", "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 reg = <0x02000000 0x40000>;
239 ranges;
240
241 spdif: spdif@2004000 {
242 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
243 reg = <0x02004000 0x4000>;
244 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
245 dmas = <&sdma 14 18 0>,
246 <&sdma 15 18 0>;
247 dma-names = "rx", "tx";
248 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
249 <&clks IMX6SX_CLK_OSC>,
250 <&clks IMX6SX_CLK_SPDIF>,
251 <&clks 0>, <&clks 0>, <&clks 0>,
252 <&clks IMX6SX_CLK_IPG>,
253 <&clks 0>, <&clks 0>,
254 <&clks IMX6SX_CLK_SPBA>;
255 clock-names = "core", "rxtx0",
256 "rxtx1", "rxtx2",
257 "rxtx3", "rxtx4",
258 "rxtx5", "rxtx6",
259 "rxtx7", "spba";
260 status = "disabled";
261 };
262
263 ecspi1: ecspi@2008000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02008000 0x4000>;
268 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI1>,
270 <&clks IMX6SX_CLK_ECSPI1>;
271 clock-names = "ipg", "per";
272 status = "disabled";
273 };
274
275 ecspi2: ecspi@200c000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
279 reg = <0x0200c000 0x4000>;
280 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6SX_CLK_ECSPI2>,
282 <&clks IMX6SX_CLK_ECSPI2>;
283 clock-names = "ipg", "per";
284 status = "disabled";
285 };
286
287 ecspi3: ecspi@2010000 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
291 reg = <0x02010000 0x4000>;
292 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6SX_CLK_ECSPI3>,
294 <&clks IMX6SX_CLK_ECSPI3>;
295 clock-names = "ipg", "per";
296 status = "disabled";
297 };
298
299 ecspi4: ecspi@2014000 {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
303 reg = <0x02014000 0x4000>;
304 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clks IMX6SX_CLK_ECSPI4>,
306 <&clks IMX6SX_CLK_ECSPI4>;
307 clock-names = "ipg", "per";
308 status = "disabled";
309 };
310
311 uart1: serial@2020000 {
312 compatible = "fsl,imx6sx-uart",
313 "fsl,imx6q-uart", "fsl,imx21-uart";
314 reg = <0x02020000 0x4000>;
315 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clks IMX6SX_CLK_UART_IPG>,
317 <&clks IMX6SX_CLK_UART_SERIAL>;
318 clock-names = "ipg", "per";
319 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
320 dma-names = "rx", "tx";
321 status = "disabled";
322 };
323
324 esai: esai@2024000 {
325 reg = <0x02024000 0x4000>;
326 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
328 <&clks IMX6SX_CLK_ESAI_MEM>,
329 <&clks IMX6SX_CLK_ESAI_EXTAL>,
330 <&clks IMX6SX_CLK_ESAI_IPG>,
331 <&clks IMX6SX_CLK_SPBA>;
332 clock-names = "core", "mem", "extal",
333 "fsys", "spba";
334 status = "disabled";
335 };
336
337 ssi1: ssi@2028000 {
338 #sound-dai-cells = <0>;
339 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
340 reg = <0x02028000 0x4000>;
341 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
343 <&clks IMX6SX_CLK_SSI1>;
344 clock-names = "ipg", "baud";
345 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
346 dma-names = "rx", "tx";
347 fsl,fifo-depth = <15>;
348 status = "disabled";
349 };
350
351 ssi2: ssi@202c000 {
352 #sound-dai-cells = <0>;
353 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
354 reg = <0x0202c000 0x4000>;
355 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
357 <&clks IMX6SX_CLK_SSI2>;
358 clock-names = "ipg", "baud";
359 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
360 dma-names = "rx", "tx";
361 fsl,fifo-depth = <15>;
362 status = "disabled";
363 };
364
365 ssi3: ssi@2030000 {
366 #sound-dai-cells = <0>;
367 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
368 reg = <0x02030000 0x4000>;
369 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
371 <&clks IMX6SX_CLK_SSI3>;
372 clock-names = "ipg", "baud";
373 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
374 dma-names = "rx", "tx";
375 fsl,fifo-depth = <15>;
376 status = "disabled";
377 };
378
379 asrc: asrc@2034000 {
380 reg = <0x02034000 0x4000>;
381 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
383 <&clks IMX6SX_CLK_ASRC_IPG>,
384 <&clks IMX6SX_CLK_SPDIF>,
385 <&clks IMX6SX_CLK_SPBA>;
386 clock-names = "mem", "ipg", "asrck", "spba";
387 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
388 <&sdma 19 20 1>, <&sdma 20 20 1>,
389 <&sdma 21 20 1>, <&sdma 22 20 1>;
390 dma-names = "rxa", "rxb", "rxc",
391 "txa", "txb", "txc";
392 status = "okay";
393 };
394 };
395
396 pwm1: pwm@2080000 {
397 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
398 reg = <0x02080000 0x4000>;
399 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6SX_CLK_PWM1>,
401 <&clks IMX6SX_CLK_PWM1>;
402 clock-names = "ipg", "per";
403 #pwm-cells = <2>;
404 };
405
406 pwm2: pwm@2084000 {
407 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
408 reg = <0x02084000 0x4000>;
409 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6SX_CLK_PWM2>,
411 <&clks IMX6SX_CLK_PWM2>;
412 clock-names = "ipg", "per";
413 #pwm-cells = <2>;
414 };
415
416 pwm3: pwm@2088000 {
417 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
418 reg = <0x02088000 0x4000>;
419 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6SX_CLK_PWM3>,
421 <&clks IMX6SX_CLK_PWM3>;
422 clock-names = "ipg", "per";
423 #pwm-cells = <2>;
424 };
425
426 pwm4: pwm@208c000 {
427 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
428 reg = <0x0208c000 0x4000>;
429 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX6SX_CLK_PWM4>,
431 <&clks IMX6SX_CLK_PWM4>;
432 clock-names = "ipg", "per";
433 #pwm-cells = <2>;
434 };
435
436 flexcan1: can@2090000 {
437 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
438 reg = <0x02090000 0x4000>;
439 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
441 <&clks IMX6SX_CLK_CAN1_SERIAL>;
442 clock-names = "ipg", "per";
443 status = "disabled";
444 };
445
446 flexcan2: can@2094000 {
447 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
448 reg = <0x02094000 0x4000>;
449 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
451 <&clks IMX6SX_CLK_CAN2_SERIAL>;
452 clock-names = "ipg", "per";
453 status = "disabled";
454 };
455
456 gpt: gpt@2098000 {
457 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
458 reg = <0x02098000 0x4000>;
459 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
461 <&clks IMX6SX_CLK_GPT_3M>;
462 clock-names = "ipg", "per";
463 };
464
465 gpio1: gpio@209c000 {
466 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
467 reg = <0x0209c000 0x4000>;
468 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
470 gpio-controller;
471 #gpio-cells = <2>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 gpio-ranges = <&iomuxc 0 5 26>;
475 };
476
477 gpio2: gpio@20a0000 {
478 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
479 reg = <0x020a0000 0x4000>;
480 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
482 gpio-controller;
483 #gpio-cells = <2>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 gpio-ranges = <&iomuxc 0 31 20>;
487 };
488
489 gpio3: gpio@20a4000 {
490 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
491 reg = <0x020a4000 0x4000>;
492 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
494 gpio-controller;
495 #gpio-cells = <2>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 gpio-ranges = <&iomuxc 0 51 29>;
499 };
500
501 gpio4: gpio@20a8000 {
502 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
503 reg = <0x020a8000 0x4000>;
504 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
506 gpio-controller;
507 #gpio-cells = <2>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 gpio-ranges = <&iomuxc 0 80 32>;
511 };
512
513 gpio5: gpio@20ac000 {
514 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
515 reg = <0x020ac000 0x4000>;
516 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
518 gpio-controller;
519 #gpio-cells = <2>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
522 gpio-ranges = <&iomuxc 0 112 24>;
523 };
524
525 gpio6: gpio@20b0000 {
526 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
527 reg = <0x020b0000 0x4000>;
528 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
530 gpio-controller;
531 #gpio-cells = <2>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
535 };
536
537 gpio7: gpio@20b4000 {
538 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
539 reg = <0x020b4000 0x4000>;
540 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
542 gpio-controller;
543 #gpio-cells = <2>;
544 interrupt-controller;
545 #interrupt-cells = <2>;
546 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
547 };
548
549 kpp: kpp@20b8000 {
550 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
551 reg = <0x020b8000 0x4000>;
552 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&clks IMX6SX_CLK_DUMMY>;
554 status = "disabled";
555 };
556
557 wdog1: wdog@20bc000 {
558 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
559 reg = <0x020bc000 0x4000>;
560 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clks IMX6SX_CLK_DUMMY>;
562 };
563
564 wdog2: wdog@20c0000 {
565 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
566 reg = <0x020c0000 0x4000>;
567 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&clks IMX6SX_CLK_DUMMY>;
569 status = "disabled";
570 };
571
572 clks: ccm@20c4000 {
573 compatible = "fsl,imx6sx-ccm";
574 reg = <0x020c4000 0x4000>;
575 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
577 #clock-cells = <1>;
578 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
579 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
580 };
581
582 anatop: anatop@20c8000 {
583 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
584 "syscon", "simple-bus";
585 reg = <0x020c8000 0x1000>;
586 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
589 #address-cells = <1>;
590 #size-cells = <0>;
591
592 regulator-1p1@20c8110 {
593 reg = <0x20c8110>;
594 compatible = "fsl,anatop-regulator";
595 regulator-name = "vdd1p1";
596 regulator-min-microvolt = <800000>;
597 regulator-max-microvolt = <1375000>;
598 regulator-always-on;
599 anatop-reg-offset = <0x110>;
600 anatop-vol-bit-shift = <8>;
601 anatop-vol-bit-width = <5>;
602 anatop-min-bit-val = <4>;
603 anatop-min-voltage = <800000>;
604 anatop-max-voltage = <1375000>;
605 anatop-enable-bit = <0>;
606 };
607
608 regulator-3p0@20c8120 {
609 reg = <0x20c8120>;
610 compatible = "fsl,anatop-regulator";
611 regulator-name = "vdd3p0";
612 regulator-min-microvolt = <2800000>;
613 regulator-max-microvolt = <3150000>;
614 regulator-always-on;
615 anatop-reg-offset = <0x120>;
616 anatop-vol-bit-shift = <8>;
617 anatop-vol-bit-width = <5>;
618 anatop-min-bit-val = <0>;
619 anatop-min-voltage = <2625000>;
620 anatop-max-voltage = <3400000>;
621 anatop-enable-bit = <0>;
622 };
623
624 regulator-2p5@20c8130 {
625 reg = <0x20c8130>;
626 compatible = "fsl,anatop-regulator";
627 regulator-name = "vdd2p5";
628 regulator-min-microvolt = <2100000>;
629 regulator-max-microvolt = <2875000>;
630 regulator-always-on;
631 anatop-reg-offset = <0x130>;
632 anatop-vol-bit-shift = <8>;
633 anatop-vol-bit-width = <5>;
634 anatop-min-bit-val = <0>;
635 anatop-min-voltage = <2100000>;
636 anatop-max-voltage = <2875000>;
637 anatop-enable-bit = <0>;
638 };
639
640 reg_arm: regulator-vddcore@20c8140 {
641 reg = <0x20c8140>;
642 compatible = "fsl,anatop-regulator";
643 regulator-name = "vddarm";
644 regulator-min-microvolt = <725000>;
645 regulator-max-microvolt = <1450000>;
646 regulator-always-on;
647 anatop-reg-offset = <0x140>;
648 anatop-vol-bit-shift = <0>;
649 anatop-vol-bit-width = <5>;
650 anatop-delay-reg-offset = <0x170>;
651 anatop-delay-bit-shift = <24>;
652 anatop-delay-bit-width = <2>;
653 anatop-min-bit-val = <1>;
654 anatop-min-voltage = <725000>;
655 anatop-max-voltage = <1450000>;
656 };
657
658 reg_pcie: regulator-vddpcie@20c8140 {
659 reg = <0x20c8140>;
660 compatible = "fsl,anatop-regulator";
661 regulator-name = "vddpcie";
662 regulator-min-microvolt = <725000>;
663 regulator-max-microvolt = <1450000>;
664 anatop-reg-offset = <0x140>;
665 anatop-vol-bit-shift = <9>;
666 anatop-vol-bit-width = <5>;
667 anatop-delay-reg-offset = <0x170>;
668 anatop-delay-bit-shift = <26>;
669 anatop-delay-bit-width = <2>;
670 anatop-min-bit-val = <1>;
671 anatop-min-voltage = <725000>;
672 anatop-max-voltage = <1450000>;
673 };
674
675 reg_soc: regulator-vddsoc@20c8140 {
676 reg = <0x20c8140>;
677 compatible = "fsl,anatop-regulator";
678 regulator-name = "vddsoc";
679 regulator-min-microvolt = <725000>;
680 regulator-max-microvolt = <1450000>;
681 regulator-always-on;
682 anatop-reg-offset = <0x140>;
683 anatop-vol-bit-shift = <18>;
684 anatop-vol-bit-width = <5>;
685 anatop-delay-reg-offset = <0x170>;
686 anatop-delay-bit-shift = <28>;
687 anatop-delay-bit-width = <2>;
688 anatop-min-bit-val = <1>;
689 anatop-min-voltage = <725000>;
690 anatop-max-voltage = <1450000>;
691 };
692 };
693
694 usbphy1: usbphy@20c9000 {
695 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
696 reg = <0x020c9000 0x1000>;
697 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clks IMX6SX_CLK_USBPHY1>;
699 fsl,anatop = <&anatop>;
700 };
701
702 usbphy2: usbphy@20ca000 {
703 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
704 reg = <0x020ca000 0x1000>;
705 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&clks IMX6SX_CLK_USBPHY2>;
707 fsl,anatop = <&anatop>;
708 };
709
710 snvs: snvs@20cc000 {
711 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
712 reg = <0x020cc000 0x4000>;
713
714 snvs_rtc: snvs-rtc-lp {
715 compatible = "fsl,sec-v4.0-mon-rtc-lp";
716 regmap = <&snvs>;
717 offset = <0x34>;
718 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
719 };
720
721 snvs_poweroff: snvs-poweroff {
722 compatible = "syscon-poweroff";
723 regmap = <&snvs>;
724 offset = <0x38>;
725 value = <0x60>;
726 mask = <0x60>;
727 status = "disabled";
728 };
729
730 snvs_pwrkey: snvs-powerkey {
731 compatible = "fsl,sec-v4.0-pwrkey";
732 regmap = <&snvs>;
733 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
734 linux,keycode = <KEY_POWER>;
735 wakeup-source;
736 };
737 };
738
739 epit1: epit@20d0000 {
740 reg = <0x020d0000 0x4000>;
741 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
742 };
743
744 epit2: epit@20d4000 {
745 reg = <0x020d4000 0x4000>;
746 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
747 };
748
749 src: src@20d8000 {
750 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
751 reg = <0x020d8000 0x4000>;
752 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
754 #reset-cells = <1>;
755 };
756
757 gpc: gpc@20dc000 {
758 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
759 reg = <0x020dc000 0x4000>;
760 interrupt-controller;
761 #interrupt-cells = <3>;
762 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
763 interrupt-parent = <&intc>;
764 clocks = <&clks IMX6SX_CLK_IPG>;
765 clock-names = "ipg";
766
767 pgc {
768 #address-cells = <1>;
769 #size-cells = <0>;
770
771 power-domain@0 {
772 reg = <0>;
773 #power-domain-cells = <0>;
774 };
775
776 pd_pu: power-domain@1 {
777 reg = <1>;
778 #power-domain-cells = <0>;
779 power-supply = <®_soc>;
780 clocks = <&clks IMX6SX_CLK_GPU>;
781 };
782
783 pd_pci: power-domain@3 {
784 reg = <3>;
785 #power-domain-cells = <0>;
786 power-supply = <®_pcie>;
787 };
788 };
789 };
790
791 iomuxc: iomuxc@20e0000 {
792 compatible = "fsl,imx6sx-iomuxc";
793 reg = <0x020e0000 0x4000>;
794 };
795
796 gpr: iomuxc-gpr@20e4000 {
797 compatible = "fsl,imx6sx-iomuxc-gpr",
798 "fsl,imx6q-iomuxc-gpr", "syscon";
799 reg = <0x020e4000 0x4000>;
800 };
801
802 sdma: sdma@20ec000 {
803 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
804 reg = <0x020ec000 0x4000>;
805 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX6SX_CLK_SDMA>,
807 <&clks IMX6SX_CLK_SDMA>;
808 clock-names = "ipg", "ahb";
809 #dma-cells = <3>;
810 /* imx6sx reuses imx6q sdma firmware */
811 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
812 };
813 };
814
815 aips2: aips-bus@2100000 {
816 compatible = "fsl,aips-bus", "simple-bus";
817 #address-cells = <1>;
818 #size-cells = <1>;
819 reg = <0x02100000 0x100000>;
820 ranges;
821
822 crypto: caam@2100000 {
823 compatible = "fsl,sec-v4.0";
824 fsl,sec-era = <4>;
825 #address-cells = <1>;
826 #size-cells = <1>;
827 reg = <0x2100000 0x10000>;
828 ranges = <0 0x2100000 0x10000>;
829 interrupt-parent = <&intc>;
830 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
831 <&clks IMX6SX_CLK_CAAM_ACLK>,
832 <&clks IMX6SX_CLK_CAAM_IPG>,
833 <&clks IMX6SX_CLK_EIM_SLOW>;
834 clock-names = "mem", "aclk", "ipg", "emi_slow";
835
836 sec_jr0: jr0@1000 {
837 compatible = "fsl,sec-v4.0-job-ring";
838 reg = <0x1000 0x1000>;
839 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
840 };
841
842 sec_jr1: jr1@2000 {
843 compatible = "fsl,sec-v4.0-job-ring";
844 reg = <0x2000 0x1000>;
845 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
846 };
847 };
848
849 usbotg1: usb@2184000 {
850 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
851 reg = <0x02184000 0x200>;
852 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&clks IMX6SX_CLK_USBOH3>;
854 fsl,usbphy = <&usbphy1>;
855 fsl,usbmisc = <&usbmisc 0>;
856 fsl,anatop = <&anatop>;
857 ahb-burst-config = <0x0>;
858 tx-burst-size-dword = <0x10>;
859 rx-burst-size-dword = <0x10>;
860 status = "disabled";
861 };
862
863 usbotg2: usb@2184200 {
864 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
865 reg = <0x02184200 0x200>;
866 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&clks IMX6SX_CLK_USBOH3>;
868 fsl,usbphy = <&usbphy2>;
869 fsl,usbmisc = <&usbmisc 1>;
870 ahb-burst-config = <0x0>;
871 tx-burst-size-dword = <0x10>;
872 rx-burst-size-dword = <0x10>;
873 status = "disabled";
874 };
875
876 usbh: usb@2184400 {
877 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
878 reg = <0x02184400 0x200>;
879 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&clks IMX6SX_CLK_USBOH3>;
881 fsl,usbmisc = <&usbmisc 2>;
882 phy_type = "hsic";
883 fsl,anatop = <&anatop>;
884 dr_mode = "host";
885 ahb-burst-config = <0x0>;
886 tx-burst-size-dword = <0x10>;
887 rx-burst-size-dword = <0x10>;
888 status = "disabled";
889 };
890
891 usbmisc: usbmisc@2184800 {
892 #index-cells = <1>;
893 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
894 reg = <0x02184800 0x200>;
895 clocks = <&clks IMX6SX_CLK_USBOH3>;
896 };
897
898 fec1: ethernet@2188000 {
899 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
900 reg = <0x02188000 0x4000>;
901 interrupt-names = "int0", "pps";
902 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&clks IMX6SX_CLK_ENET>,
905 <&clks IMX6SX_CLK_ENET_AHB>,
906 <&clks IMX6SX_CLK_ENET_PTP>,
907 <&clks IMX6SX_CLK_ENET_REF>,
908 <&clks IMX6SX_CLK_ENET_PTP>;
909 clock-names = "ipg", "ahb", "ptp",
910 "enet_clk_ref", "enet_out";
911 fsl,num-tx-queues=<3>;
912 fsl,num-rx-queues=<3>;
913 status = "disabled";
914 };
915
916 mlb: mlb@218c000 {
917 reg = <0x0218c000 0x4000>;
918 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6SX_CLK_MLB>;
922 status = "disabled";
923 };
924
925 usdhc1: usdhc@2190000 {
926 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
927 reg = <0x02190000 0x4000>;
928 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX6SX_CLK_USDHC1>,
930 <&clks IMX6SX_CLK_USDHC1>,
931 <&clks IMX6SX_CLK_USDHC1>;
932 clock-names = "ipg", "ahb", "per";
933 bus-width = <4>;
934 status = "disabled";
935 };
936
937 usdhc2: usdhc@2194000 {
938 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
939 reg = <0x02194000 0x4000>;
940 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&clks IMX6SX_CLK_USDHC2>,
942 <&clks IMX6SX_CLK_USDHC2>,
943 <&clks IMX6SX_CLK_USDHC2>;
944 clock-names = "ipg", "ahb", "per";
945 bus-width = <4>;
946 status = "disabled";
947 };
948
949 usdhc3: usdhc@2198000 {
950 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
951 reg = <0x02198000 0x4000>;
952 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&clks IMX6SX_CLK_USDHC3>,
954 <&clks IMX6SX_CLK_USDHC3>,
955 <&clks IMX6SX_CLK_USDHC3>;
956 clock-names = "ipg", "ahb", "per";
957 bus-width = <4>;
958 status = "disabled";
959 };
960
961 usdhc4: usdhc@219c000 {
962 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
963 reg = <0x0219c000 0x4000>;
964 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&clks IMX6SX_CLK_USDHC4>,
966 <&clks IMX6SX_CLK_USDHC4>,
967 <&clks IMX6SX_CLK_USDHC4>;
968 clock-names = "ipg", "ahb", "per";
969 bus-width = <4>;
970 status = "disabled";
971 };
972
973 i2c1: i2c@21a0000 {
974 #address-cells = <1>;
975 #size-cells = <0>;
976 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
977 reg = <0x021a0000 0x4000>;
978 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&clks IMX6SX_CLK_I2C1>;
980 status = "disabled";
981 };
982
983 i2c2: i2c@21a4000 {
984 #address-cells = <1>;
985 #size-cells = <0>;
986 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
987 reg = <0x021a4000 0x4000>;
988 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&clks IMX6SX_CLK_I2C2>;
990 status = "disabled";
991 };
992
993 i2c3: i2c@21a8000 {
994 #address-cells = <1>;
995 #size-cells = <0>;
996 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
997 reg = <0x021a8000 0x4000>;
998 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&clks IMX6SX_CLK_I2C3>;
1000 status = "disabled";
1001 };
1002
1003 mmdc: mmdc@21b0000 {
1004 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1005 reg = <0x021b0000 0x4000>;
1006 };
1007
1008 fec2: ethernet@21b4000 {
1009 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1010 reg = <0x021b4000 0x4000>;
1011 interrupt-names = "int0", "pps";
1012 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&clks IMX6SX_CLK_ENET>,
1015 <&clks IMX6SX_CLK_ENET_AHB>,
1016 <&clks IMX6SX_CLK_ENET_PTP>,
1017 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1018 <&clks IMX6SX_CLK_ENET_PTP>;
1019 clock-names = "ipg", "ahb", "ptp",
1020 "enet_clk_ref", "enet_out";
1021 status = "disabled";
1022 };
1023
1024 weim: weim@21b8000 {
1025 #address-cells = <2>;
1026 #size-cells = <1>;
1027 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1028 reg = <0x021b8000 0x4000>;
1029 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1031 fsl,weim-cs-gpr = <&gpr>;
1032 status = "disabled";
1033 };
1034
1035 ocotp: ocotp@21bc000 {
1036 #address-cells = <1>;
1037 #size-cells = <1>;
1038 compatible = "fsl,imx6sx-ocotp", "syscon";
1039 reg = <0x021bc000 0x4000>;
1040 clocks = <&clks IMX6SX_CLK_OCOTP>;
1041
1042 tempmon_calib: calib@38 {
1043 reg = <0x38 4>;
1044 };
1045
1046 tempmon_temp_grade: temp-grade@20 {
1047 reg = <0x20 4>;
1048 };
1049 };
1050
1051 sai1: sai@21d4000 {
1052 compatible = "fsl,imx6sx-sai";
1053 reg = <0x021d4000 0x4000>;
1054 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1056 <&clks IMX6SX_CLK_SAI1>,
1057 <&clks 0>, <&clks 0>;
1058 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1059 dma-names = "rx", "tx";
1060 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1061 status = "disabled";
1062 };
1063
1064 audmux: audmux@21d8000 {
1065 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1066 reg = <0x021d8000 0x4000>;
1067 status = "disabled";
1068 };
1069
1070 sai2: sai@21dc000 {
1071 compatible = "fsl,imx6sx-sai";
1072 reg = <0x021dc000 0x4000>;
1073 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1075 <&clks IMX6SX_CLK_SAI2>,
1076 <&clks 0>, <&clks 0>;
1077 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1078 dma-names = "rx", "tx";
1079 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1080 status = "disabled";
1081 };
1082
1083 qspi1: qspi@21e0000 {
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 compatible = "fsl,imx6sx-qspi";
1087 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1088 reg-names = "QuadSPI", "QuadSPI-memory";
1089 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&clks IMX6SX_CLK_QSPI1>,
1091 <&clks IMX6SX_CLK_QSPI1>;
1092 clock-names = "qspi_en", "qspi";
1093 status = "disabled";
1094 };
1095
1096 qspi2: qspi@21e4000 {
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1099 compatible = "fsl,imx6sx-qspi";
1100 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1101 reg-names = "QuadSPI", "QuadSPI-memory";
1102 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&clks IMX6SX_CLK_QSPI2>,
1104 <&clks IMX6SX_CLK_QSPI2>;
1105 clock-names = "qspi_en", "qspi";
1106 status = "disabled";
1107 };
1108
1109 uart2: serial@21e8000 {
1110 compatible = "fsl,imx6sx-uart",
1111 "fsl,imx6q-uart", "fsl,imx21-uart";
1112 reg = <0x021e8000 0x4000>;
1113 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1115 <&clks IMX6SX_CLK_UART_SERIAL>;
1116 clock-names = "ipg", "per";
1117 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1118 dma-names = "rx", "tx";
1119 status = "disabled";
1120 };
1121
1122 uart3: serial@21ec000 {
1123 compatible = "fsl,imx6sx-uart",
1124 "fsl,imx6q-uart", "fsl,imx21-uart";
1125 reg = <0x021ec000 0x4000>;
1126 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1128 <&clks IMX6SX_CLK_UART_SERIAL>;
1129 clock-names = "ipg", "per";
1130 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1131 dma-names = "rx", "tx";
1132 status = "disabled";
1133 };
1134
1135 uart4: serial@21f0000 {
1136 compatible = "fsl,imx6sx-uart",
1137 "fsl,imx6q-uart", "fsl,imx21-uart";
1138 reg = <0x021f0000 0x4000>;
1139 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1140 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1141 <&clks IMX6SX_CLK_UART_SERIAL>;
1142 clock-names = "ipg", "per";
1143 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1144 dma-names = "rx", "tx";
1145 status = "disabled";
1146 };
1147
1148 uart5: serial@21f4000 {
1149 compatible = "fsl,imx6sx-uart",
1150 "fsl,imx6q-uart", "fsl,imx21-uart";
1151 reg = <0x021f4000 0x4000>;
1152 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1153 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1154 <&clks IMX6SX_CLK_UART_SERIAL>;
1155 clock-names = "ipg", "per";
1156 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1157 dma-names = "rx", "tx";
1158 status = "disabled";
1159 };
1160
1161 i2c4: i2c@21f8000 {
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1164 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1165 reg = <0x021f8000 0x4000>;
1166 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1167 clocks = <&clks IMX6SX_CLK_I2C4>;
1168 status = "disabled";
1169 };
1170 };
1171
1172 aips3: aips-bus@2200000 {
1173 compatible = "fsl,aips-bus", "simple-bus";
1174 #address-cells = <1>;
1175 #size-cells = <1>;
1176 reg = <0x02200000 0x100000>;
1177 ranges;
1178
1179 spba-bus@2240000 {
1180 compatible = "fsl,spba-bus", "simple-bus";
1181 #address-cells = <1>;
1182 #size-cells = <1>;
1183 reg = <0x02240000 0x40000>;
1184 ranges;
1185
1186 csi1: csi@2214000 {
1187 reg = <0x02214000 0x4000>;
1188 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1190 <&clks IMX6SX_CLK_CSI>,
1191 <&clks IMX6SX_CLK_DCIC1>;
1192 clock-names = "disp-axi", "csi_mclk", "dcic";
1193 status = "disabled";
1194 };
1195
1196 pxp: pxp@2218000 {
1197 reg = <0x02218000 0x4000>;
1198 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1200 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1201 clock-names = "pxp-axi", "disp-axi";
1202 status = "disabled";
1203 };
1204
1205 csi2: csi@221c000 {
1206 reg = <0x0221c000 0x4000>;
1207 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1209 <&clks IMX6SX_CLK_CSI>,
1210 <&clks IMX6SX_CLK_DCIC2>;
1211 clock-names = "disp-axi", "csi_mclk", "dcic";
1212 status = "disabled";
1213 };
1214
1215 lcdif1: lcdif@2220000 {
1216 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1217 reg = <0x02220000 0x4000>;
1218 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1219 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1220 <&clks IMX6SX_CLK_LCDIF_APB>,
1221 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1222 clock-names = "pix", "axi", "disp_axi";
1223 status = "disabled";
1224 };
1225
1226 lcdif2: lcdif@2224000 {
1227 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1228 reg = <0x02224000 0x4000>;
1229 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1230 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1231 <&clks IMX6SX_CLK_LCDIF_APB>,
1232 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1233 clock-names = "pix", "axi", "disp_axi";
1234 status = "disabled";
1235 };
1236
1237 vadc: vadc@2228000 {
1238 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1239 reg-names = "vadc-vafe", "vadc-vdec";
1240 clocks = <&clks IMX6SX_CLK_VADC>,
1241 <&clks IMX6SX_CLK_CSI>;
1242 clock-names = "vadc", "csi";
1243 status = "disabled";
1244 };
1245 };
1246
1247 adc1: adc@2280000 {
1248 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1249 reg = <0x02280000 0x4000>;
1250 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&clks IMX6SX_CLK_IPG>;
1252 clock-names = "adc";
1253 fsl,adck-max-frequency = <30000000>, <40000000>,
1254 <20000000>;
1255 status = "disabled";
1256 };
1257
1258 adc2: adc@2284000 {
1259 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1260 reg = <0x02284000 0x4000>;
1261 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&clks IMX6SX_CLK_IPG>;
1263 clock-names = "adc";
1264 fsl,adck-max-frequency = <30000000>, <40000000>,
1265 <20000000>;
1266 status = "disabled";
1267 };
1268
1269 wdog3: wdog@2288000 {
1270 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1271 reg = <0x02288000 0x4000>;
1272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&clks IMX6SX_CLK_DUMMY>;
1274 status = "disabled";
1275 };
1276
1277 ecspi5: ecspi@228c000 {
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1280 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1281 reg = <0x0228c000 0x4000>;
1282 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1284 <&clks IMX6SX_CLK_ECSPI5>;
1285 clock-names = "ipg", "per";
1286 status = "disabled";
1287 };
1288
1289 uart6: serial@22a0000 {
1290 compatible = "fsl,imx6sx-uart",
1291 "fsl,imx6q-uart", "fsl,imx21-uart";
1292 reg = <0x022a0000 0x4000>;
1293 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1294 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1295 <&clks IMX6SX_CLK_UART_SERIAL>;
1296 clock-names = "ipg", "per";
1297 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1298 dma-names = "rx", "tx";
1299 status = "disabled";
1300 };
1301
1302 pwm5: pwm@22a4000 {
1303 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1304 reg = <0x022a4000 0x4000>;
1305 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1306 clocks = <&clks IMX6SX_CLK_PWM5>,
1307 <&clks IMX6SX_CLK_PWM5>;
1308 clock-names = "ipg", "per";
1309 #pwm-cells = <2>;
1310 };
1311
1312 pwm6: pwm@22a8000 {
1313 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1314 reg = <0x022a8000 0x4000>;
1315 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1316 clocks = <&clks IMX6SX_CLK_PWM6>,
1317 <&clks IMX6SX_CLK_PWM6>;
1318 clock-names = "ipg", "per";
1319 #pwm-cells = <2>;
1320 };
1321
1322 pwm7: pwm@22ac000 {
1323 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1324 reg = <0x022ac000 0x4000>;
1325 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&clks IMX6SX_CLK_PWM7>,
1327 <&clks IMX6SX_CLK_PWM7>;
1328 clock-names = "ipg", "per";
1329 #pwm-cells = <2>;
1330 };
1331
1332 pwm8: pwm@22b0000 {
1333 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1334 reg = <0x0022b0000 0x4000>;
1335 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1336 clocks = <&clks IMX6SX_CLK_PWM8>,
1337 <&clks IMX6SX_CLK_PWM8>;
1338 clock-names = "ipg", "per";
1339 #pwm-cells = <2>;
1340 };
1341 };
1342
1343 pcie: pcie@8ffc000 {
1344 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1345 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1346 reg-names = "dbi", "config";
1347 #address-cells = <3>;
1348 #size-cells = <2>;
1349 device_type = "pci";
1350 bus-range = <0x00 0xff>;
1351 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
1352 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1353 num-lanes = <1>;
1354 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1355 interrupt-names = "msi";
1356 #interrupt-cells = <1>;
1357 interrupt-map-mask = <0 0 0 0x7>;
1358 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1359 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1360 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1361 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1363 <&clks IMX6SX_CLK_LVDS1_OUT>,
1364 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1365 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1366 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1367 power-domains = <&pd_pci>;
1368 status = "disabled";
1369 };
1370 };
1371};