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1/*
2 * EHRPWM PWM driver
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/pwm.h>
24#include <linux/io.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/pm_runtime.h>
28#include <linux/of_device.h>
29
30/* EHRPWM registers and bits definitions */
31
32/* Time base module registers */
33#define TBCTL 0x00
34#define TBPRD 0x0A
35
36#define TBCTL_RUN_MASK (BIT(15) | BIT(14))
37#define TBCTL_STOP_NEXT 0
38#define TBCTL_STOP_ON_CYCLE BIT(14)
39#define TBCTL_FREE_RUN (BIT(15) | BIT(14))
40#define TBCTL_PRDLD_MASK BIT(3)
41#define TBCTL_PRDLD_SHDW 0
42#define TBCTL_PRDLD_IMDT BIT(3)
43#define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
44 BIT(8) | BIT(7))
45#define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
46#define TBCTL_CTRMODE_UP 0
47#define TBCTL_CTRMODE_DOWN BIT(0)
48#define TBCTL_CTRMODE_UPDOWN BIT(1)
49#define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
50
51#define TBCTL_HSPCLKDIV_SHIFT 7
52#define TBCTL_CLKDIV_SHIFT 10
53
54#define CLKDIV_MAX 7
55#define HSPCLKDIV_MAX 7
56#define PERIOD_MAX 0xFFFF
57
58/* compare module registers */
59#define CMPA 0x12
60#define CMPB 0x14
61
62/* Action qualifier module registers */
63#define AQCTLA 0x16
64#define AQCTLB 0x18
65#define AQSFRC 0x1A
66#define AQCSFRC 0x1C
67
68#define AQCTL_CBU_MASK (BIT(9) | BIT(8))
69#define AQCTL_CBU_FRCLOW BIT(8)
70#define AQCTL_CBU_FRCHIGH BIT(9)
71#define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
72#define AQCTL_CAU_MASK (BIT(5) | BIT(4))
73#define AQCTL_CAU_FRCLOW BIT(4)
74#define AQCTL_CAU_FRCHIGH BIT(5)
75#define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
76#define AQCTL_PRD_MASK (BIT(3) | BIT(2))
77#define AQCTL_PRD_FRCLOW BIT(2)
78#define AQCTL_PRD_FRCHIGH BIT(3)
79#define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
80#define AQCTL_ZRO_MASK (BIT(1) | BIT(0))
81#define AQCTL_ZRO_FRCLOW BIT(0)
82#define AQCTL_ZRO_FRCHIGH BIT(1)
83#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
84
85#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
86 AQCTL_ZRO_FRCHIGH)
87#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
88 AQCTL_ZRO_FRCLOW)
89#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
90 AQCTL_ZRO_FRCHIGH)
91#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
92 AQCTL_ZRO_FRCLOW)
93
94#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
95#define AQSFRC_RLDCSF_ZRO 0
96#define AQSFRC_RLDCSF_PRD BIT(6)
97#define AQSFRC_RLDCSF_ZROPRD BIT(7)
98#define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6))
99
100#define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2))
101#define AQCSFRC_CSFB_FRCDIS 0
102#define AQCSFRC_CSFB_FRCLOW BIT(2)
103#define AQCSFRC_CSFB_FRCHIGH BIT(3)
104#define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2))
105#define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0))
106#define AQCSFRC_CSFA_FRCDIS 0
107#define AQCSFRC_CSFA_FRCLOW BIT(0)
108#define AQCSFRC_CSFA_FRCHIGH BIT(1)
109#define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0))
110
111#define NUM_PWM_CHANNEL 2 /* EHRPWM channels */
112
113struct ehrpwm_context {
114 u16 tbctl;
115 u16 tbprd;
116 u16 cmpa;
117 u16 cmpb;
118 u16 aqctla;
119 u16 aqctlb;
120 u16 aqsfrc;
121 u16 aqcsfrc;
122};
123
124struct ehrpwm_pwm_chip {
125 struct pwm_chip chip;
126 unsigned long clk_rate;
127 void __iomem *mmio_base;
128 unsigned long period_cycles[NUM_PWM_CHANNEL];
129 enum pwm_polarity polarity[NUM_PWM_CHANNEL];
130 struct clk *tbclk;
131 struct ehrpwm_context ctx;
132};
133
134static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
135{
136 return container_of(chip, struct ehrpwm_pwm_chip, chip);
137}
138
139static inline u16 ehrpwm_read(void __iomem *base, unsigned int offset)
140{
141 return readw(base + offset);
142}
143
144static inline void ehrpwm_write(void __iomem *base, unsigned int offset,
145 u16 value)
146{
147 writew(value, base + offset);
148}
149
150static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask,
151 u16 value)
152{
153 unsigned short val;
154
155 val = readw(base + offset);
156 val &= ~mask;
157 val |= value & mask;
158 writew(val, base + offset);
159}
160
161/**
162 * set_prescale_div - Set up the prescaler divider function
163 * @rqst_prescaler: prescaler value min
164 * @prescale_div: prescaler value set
165 * @tb_clk_div: Time Base Control prescaler bits
166 */
167static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
168 u16 *tb_clk_div)
169{
170 unsigned int clkdiv, hspclkdiv;
171
172 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {
173 for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) {
174 /*
175 * calculations for prescaler value :
176 * prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
177 * HSPCLKDIVIDER = 2 ** hspclkdiv
178 * CLKDIVIDER = (1), if clkdiv == 0 *OR*
179 * (2 * clkdiv), if clkdiv != 0
180 *
181 * Configure prescale_div value such that period
182 * register value is less than 65535.
183 */
184
185 *prescale_div = (1 << clkdiv) *
186 (hspclkdiv ? (hspclkdiv * 2) : 1);
187 if (*prescale_div > rqst_prescaler) {
188 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
189 (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
190 return 0;
191 }
192 }
193 }
194
195 return 1;
196}
197
198static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
199{
200 u16 aqctl_val, aqctl_mask;
201 unsigned int aqctl_reg;
202
203 /*
204 * Configure PWM output to HIGH/LOW level on counter
205 * reaches compare register value and LOW/HIGH level
206 * on counter value reaches period register value and
207 * zero value on counter
208 */
209 if (chan == 1) {
210 aqctl_reg = AQCTLB;
211 aqctl_mask = AQCTL_CBU_MASK;
212
213 if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
214 aqctl_val = AQCTL_CHANB_POLINVERSED;
215 else
216 aqctl_val = AQCTL_CHANB_POLNORMAL;
217 } else {
218 aqctl_reg = AQCTLA;
219 aqctl_mask = AQCTL_CAU_MASK;
220
221 if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
222 aqctl_val = AQCTL_CHANA_POLINVERSED;
223 else
224 aqctl_val = AQCTL_CHANA_POLNORMAL;
225 }
226
227 aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
228 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
229}
230
231/*
232 * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
233 * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
234 */
235static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
236 int duty_ns, int period_ns)
237{
238 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
239 u32 period_cycles, duty_cycles;
240 u16 ps_divval, tb_divval;
241 unsigned int i, cmp_reg;
242 unsigned long long c;
243
244 if (period_ns > NSEC_PER_SEC)
245 return -ERANGE;
246
247 c = pc->clk_rate;
248 c = c * period_ns;
249 do_div(c, NSEC_PER_SEC);
250 period_cycles = (unsigned long)c;
251
252 if (period_cycles < 1) {
253 period_cycles = 1;
254 duty_cycles = 1;
255 } else {
256 c = pc->clk_rate;
257 c = c * duty_ns;
258 do_div(c, NSEC_PER_SEC);
259 duty_cycles = (unsigned long)c;
260 }
261
262 /*
263 * Period values should be same for multiple PWM channels as IP uses
264 * same period register for multiple channels.
265 */
266 for (i = 0; i < NUM_PWM_CHANNEL; i++) {
267 if (pc->period_cycles[i] &&
268 (pc->period_cycles[i] != period_cycles)) {
269 /*
270 * Allow channel to reconfigure period if no other
271 * channels being configured.
272 */
273 if (i == pwm->hwpwm)
274 continue;
275
276 dev_err(chip->dev,
277 "period value conflicts with channel %u\n",
278 i);
279 return -EINVAL;
280 }
281 }
282
283 pc->period_cycles[pwm->hwpwm] = period_cycles;
284
285 /* Configure clock prescaler to support Low frequency PWM wave */
286 if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
287 &tb_divval)) {
288 dev_err(chip->dev, "Unsupported values\n");
289 return -EINVAL;
290 }
291
292 pm_runtime_get_sync(chip->dev);
293
294 /* Update clock prescaler values */
295 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
296
297 /* Update period & duty cycle with presacler division */
298 period_cycles = period_cycles / ps_divval;
299 duty_cycles = duty_cycles / ps_divval;
300
301 /* Configure shadow loading on Period register */
302 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
303
304 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
305
306 /* Configure ehrpwm counter for up-count mode */
307 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
308 TBCTL_CTRMODE_UP);
309
310 if (pwm->hwpwm == 1)
311 /* Channel 1 configured with compare B register */
312 cmp_reg = CMPB;
313 else
314 /* Channel 0 configured with compare A register */
315 cmp_reg = CMPA;
316
317 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
318
319 pm_runtime_put_sync(chip->dev);
320
321 return 0;
322}
323
324static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip,
325 struct pwm_device *pwm,
326 enum pwm_polarity polarity)
327{
328 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
329
330 /* Configuration of polarity in hardware delayed, do at enable */
331 pc->polarity[pwm->hwpwm] = polarity;
332
333 return 0;
334}
335
336static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
337{
338 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
339 u16 aqcsfrc_val, aqcsfrc_mask;
340 int ret;
341
342 /* Leave clock enabled on enabling PWM */
343 pm_runtime_get_sync(chip->dev);
344
345 /* Disabling Action Qualifier on PWM output */
346 if (pwm->hwpwm) {
347 aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
348 aqcsfrc_mask = AQCSFRC_CSFB_MASK;
349 } else {
350 aqcsfrc_val = AQCSFRC_CSFA_FRCDIS;
351 aqcsfrc_mask = AQCSFRC_CSFA_MASK;
352 }
353
354 /* Changes to shadow mode */
355 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
356 AQSFRC_RLDCSF_ZRO);
357
358 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
359
360 /* Channels polarity can be configured from action qualifier module */
361 configure_polarity(pc, pwm->hwpwm);
362
363 /* Enable TBCLK before enabling PWM device */
364 ret = clk_enable(pc->tbclk);
365 if (ret) {
366 dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n",
367 dev_name(pc->chip.dev), ret);
368 return ret;
369 }
370
371 /* Enable time counter for free_run */
372 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN);
373
374 return 0;
375}
376
377static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
378{
379 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
380 u16 aqcsfrc_val, aqcsfrc_mask;
381
382 /* Action Qualifier puts PWM output low forcefully */
383 if (pwm->hwpwm) {
384 aqcsfrc_val = AQCSFRC_CSFB_FRCLOW;
385 aqcsfrc_mask = AQCSFRC_CSFB_MASK;
386 } else {
387 aqcsfrc_val = AQCSFRC_CSFA_FRCLOW;
388 aqcsfrc_mask = AQCSFRC_CSFA_MASK;
389 }
390
391 /*
392 * Changes to immediate action on Action Qualifier. This puts
393 * Action Qualifier control on PWM output from next TBCLK
394 */
395 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
396 AQSFRC_RLDCSF_IMDT);
397
398 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
399
400 /* Disabling TBCLK on PWM disable */
401 clk_disable(pc->tbclk);
402
403 /* Stop Time base counter */
404 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT);
405
406 /* Disable clock on PWM disable */
407 pm_runtime_put_sync(chip->dev);
408}
409
410static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
411{
412 struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
413
414 if (pwm_is_enabled(pwm)) {
415 dev_warn(chip->dev, "Removing PWM device without disabling\n");
416 pm_runtime_put_sync(chip->dev);
417 }
418
419 /* set period value to zero on free */
420 pc->period_cycles[pwm->hwpwm] = 0;
421}
422
423static const struct pwm_ops ehrpwm_pwm_ops = {
424 .free = ehrpwm_pwm_free,
425 .config = ehrpwm_pwm_config,
426 .set_polarity = ehrpwm_pwm_set_polarity,
427 .enable = ehrpwm_pwm_enable,
428 .disable = ehrpwm_pwm_disable,
429 .owner = THIS_MODULE,
430};
431
432static const struct of_device_id ehrpwm_of_match[] = {
433 { .compatible = "ti,am3352-ehrpwm" },
434 { .compatible = "ti,am33xx-ehrpwm" },
435 {},
436};
437MODULE_DEVICE_TABLE(of, ehrpwm_of_match);
438
439static int ehrpwm_pwm_probe(struct platform_device *pdev)
440{
441 struct device_node *np = pdev->dev.of_node;
442 struct ehrpwm_pwm_chip *pc;
443 struct resource *r;
444 struct clk *clk;
445 int ret;
446
447 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
448 if (!pc)
449 return -ENOMEM;
450
451 clk = devm_clk_get(&pdev->dev, "fck");
452 if (IS_ERR(clk)) {
453 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
454 dev_warn(&pdev->dev, "Binding is obsolete.\n");
455 clk = devm_clk_get(pdev->dev.parent, "fck");
456 }
457 }
458
459 if (IS_ERR(clk)) {
460 dev_err(&pdev->dev, "failed to get clock\n");
461 return PTR_ERR(clk);
462 }
463
464 pc->clk_rate = clk_get_rate(clk);
465 if (!pc->clk_rate) {
466 dev_err(&pdev->dev, "failed to get clock rate\n");
467 return -EINVAL;
468 }
469
470 pc->chip.dev = &pdev->dev;
471 pc->chip.ops = &ehrpwm_pwm_ops;
472 pc->chip.of_xlate = of_pwm_xlate_with_flags;
473 pc->chip.of_pwm_n_cells = 3;
474 pc->chip.base = -1;
475 pc->chip.npwm = NUM_PWM_CHANNEL;
476
477 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
479 if (IS_ERR(pc->mmio_base))
480 return PTR_ERR(pc->mmio_base);
481
482 /* Acquire tbclk for Time Base EHRPWM submodule */
483 pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");
484 if (IS_ERR(pc->tbclk)) {
485 dev_err(&pdev->dev, "Failed to get tbclk\n");
486 return PTR_ERR(pc->tbclk);
487 }
488
489 ret = clk_prepare(pc->tbclk);
490 if (ret < 0) {
491 dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret);
492 return ret;
493 }
494
495 ret = pwmchip_add(&pc->chip);
496 if (ret < 0) {
497 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
498 goto err_clk_unprepare;
499 }
500
501 platform_set_drvdata(pdev, pc);
502 pm_runtime_enable(&pdev->dev);
503
504 return 0;
505
506err_clk_unprepare:
507 clk_unprepare(pc->tbclk);
508
509 return ret;
510}
511
512static int ehrpwm_pwm_remove(struct platform_device *pdev)
513{
514 struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
515
516 clk_unprepare(pc->tbclk);
517
518 pm_runtime_disable(&pdev->dev);
519
520 return pwmchip_remove(&pc->chip);
521}
522
523#ifdef CONFIG_PM_SLEEP
524static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc)
525{
526 pm_runtime_get_sync(pc->chip.dev);
527
528 pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);
529 pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);
530 pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);
531 pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);
532 pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);
533 pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);
534 pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);
535 pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);
536
537 pm_runtime_put_sync(pc->chip.dev);
538}
539
540static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc)
541{
542 ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);
543 ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);
544 ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);
545 ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);
546 ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);
547 ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);
548 ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);
549 ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);
550}
551
552static int ehrpwm_pwm_suspend(struct device *dev)
553{
554 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
555 unsigned int i;
556
557 ehrpwm_pwm_save_context(pc);
558
559 for (i = 0; i < pc->chip.npwm; i++) {
560 struct pwm_device *pwm = &pc->chip.pwms[i];
561
562 if (!pwm_is_enabled(pwm))
563 continue;
564
565 /* Disable explicitly if PWM is running */
566 pm_runtime_put_sync(dev);
567 }
568
569 return 0;
570}
571
572static int ehrpwm_pwm_resume(struct device *dev)
573{
574 struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
575 unsigned int i;
576
577 for (i = 0; i < pc->chip.npwm; i++) {
578 struct pwm_device *pwm = &pc->chip.pwms[i];
579
580 if (!pwm_is_enabled(pwm))
581 continue;
582
583 /* Enable explicitly if PWM was running */
584 pm_runtime_get_sync(dev);
585 }
586
587 ehrpwm_pwm_restore_context(pc);
588
589 return 0;
590}
591#endif
592
593static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend,
594 ehrpwm_pwm_resume);
595
596static struct platform_driver ehrpwm_pwm_driver = {
597 .driver = {
598 .name = "ehrpwm",
599 .of_match_table = ehrpwm_of_match,
600 .pm = &ehrpwm_pwm_pm_ops,
601 },
602 .probe = ehrpwm_pwm_probe,
603 .remove = ehrpwm_pwm_remove,
604};
605module_platform_driver(ehrpwm_pwm_driver);
606
607MODULE_DESCRIPTION("EHRPWM PWM driver");
608MODULE_AUTHOR("Texas Instruments");
609MODULE_LICENSE("GPL");