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1/*
2 * Ethernet driver for the WIZnet W5100 chip.
3 *
4 * Copyright (C) 2006-2008 WIZnet Co.,Ltd.
5 * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/platform_device.h>
15#include <linux/platform_data/wiznet.h>
16#include <linux/ethtool.h>
17#include <linux/skbuff.h>
18#include <linux/types.h>
19#include <linux/errno.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
28
29#include "w5100.h"
30
31#define DRV_NAME "w5100"
32#define DRV_VERSION "2012-04-04"
33
34MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION);
35MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
36MODULE_ALIAS("platform:"DRV_NAME);
37MODULE_LICENSE("GPL");
38
39/*
40 * W5100/W5200/W5500 common registers
41 */
42#define W5100_COMMON_REGS 0x0000
43#define W5100_MR 0x0000 /* Mode Register */
44#define MR_RST 0x80 /* S/W reset */
45#define MR_PB 0x10 /* Ping block */
46#define MR_AI 0x02 /* Address Auto-Increment */
47#define MR_IND 0x01 /* Indirect mode */
48#define W5100_SHAR 0x0009 /* Source MAC address */
49#define W5100_IR 0x0015 /* Interrupt Register */
50#define W5100_COMMON_REGS_LEN 0x0040
51
52#define W5100_Sn_MR 0x0000 /* Sn Mode Register */
53#define W5100_Sn_CR 0x0001 /* Sn Command Register */
54#define W5100_Sn_IR 0x0002 /* Sn Interrupt Register */
55#define W5100_Sn_SR 0x0003 /* Sn Status Register */
56#define W5100_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
57#define W5100_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
58#define W5100_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
59#define W5100_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */
60#define W5100_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */
61
62#define S0_REGS(priv) ((priv)->s0_regs)
63
64#define W5100_S0_MR(priv) (S0_REGS(priv) + W5100_Sn_MR)
65#define S0_MR_MACRAW 0x04 /* MAC RAW mode */
66#define S0_MR_MF 0x40 /* MAC Filter for W5100 and W5200 */
67#define W5500_S0_MR_MF 0x80 /* MAC Filter for W5500 */
68#define W5100_S0_CR(priv) (S0_REGS(priv) + W5100_Sn_CR)
69#define S0_CR_OPEN 0x01 /* OPEN command */
70#define S0_CR_CLOSE 0x10 /* CLOSE command */
71#define S0_CR_SEND 0x20 /* SEND command */
72#define S0_CR_RECV 0x40 /* RECV command */
73#define W5100_S0_IR(priv) (S0_REGS(priv) + W5100_Sn_IR)
74#define S0_IR_SENDOK 0x10 /* complete sending */
75#define S0_IR_RECV 0x04 /* receiving data */
76#define W5100_S0_SR(priv) (S0_REGS(priv) + W5100_Sn_SR)
77#define S0_SR_MACRAW 0x42 /* mac raw mode */
78#define W5100_S0_TX_FSR(priv) (S0_REGS(priv) + W5100_Sn_TX_FSR)
79#define W5100_S0_TX_RD(priv) (S0_REGS(priv) + W5100_Sn_TX_RD)
80#define W5100_S0_TX_WR(priv) (S0_REGS(priv) + W5100_Sn_TX_WR)
81#define W5100_S0_RX_RSR(priv) (S0_REGS(priv) + W5100_Sn_RX_RSR)
82#define W5100_S0_RX_RD(priv) (S0_REGS(priv) + W5100_Sn_RX_RD)
83
84#define W5100_S0_REGS_LEN 0x0040
85
86/*
87 * W5100 and W5200 common registers
88 */
89#define W5100_IMR 0x0016 /* Interrupt Mask Register */
90#define IR_S0 0x01 /* S0 interrupt */
91#define W5100_RTR 0x0017 /* Retry Time-value Register */
92#define RTR_DEFAULT 2000 /* =0x07d0 (2000) */
93
94/*
95 * W5100 specific register and memory
96 */
97#define W5100_RMSR 0x001a /* Receive Memory Size */
98#define W5100_TMSR 0x001b /* Transmit Memory Size */
99
100#define W5100_S0_REGS 0x0400
101
102#define W5100_TX_MEM_START 0x4000
103#define W5100_TX_MEM_SIZE 0x2000
104#define W5100_RX_MEM_START 0x6000
105#define W5100_RX_MEM_SIZE 0x2000
106
107/*
108 * W5200 specific register and memory
109 */
110#define W5200_S0_REGS 0x4000
111
112#define W5200_Sn_RXMEM_SIZE(n) (0x401e + (n) * 0x0100) /* Sn RX Memory Size */
113#define W5200_Sn_TXMEM_SIZE(n) (0x401f + (n) * 0x0100) /* Sn TX Memory Size */
114
115#define W5200_TX_MEM_START 0x8000
116#define W5200_TX_MEM_SIZE 0x4000
117#define W5200_RX_MEM_START 0xc000
118#define W5200_RX_MEM_SIZE 0x4000
119
120/*
121 * W5500 specific register and memory
122 *
123 * W5500 register and memory are organized by multiple blocks. Each one is
124 * selected by 16bits offset address and 5bits block select bits. So we
125 * encode it into 32bits address. (lower 16bits is offset address and
126 * upper 16bits is block select bits)
127 */
128#define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */
129#define W5500_RTR 0x0019 /* Retry Time-value Register */
130
131#define W5500_S0_REGS 0x10000
132
133#define W5500_Sn_RXMEM_SIZE(n) \
134 (0x1001e + (n) * 0x40000) /* Sn RX Memory Size */
135#define W5500_Sn_TXMEM_SIZE(n) \
136 (0x1001f + (n) * 0x40000) /* Sn TX Memory Size */
137
138#define W5500_TX_MEM_START 0x20000
139#define W5500_TX_MEM_SIZE 0x04000
140#define W5500_RX_MEM_START 0x30000
141#define W5500_RX_MEM_SIZE 0x04000
142
143/*
144 * Device driver private data structure
145 */
146
147struct w5100_priv {
148 const struct w5100_ops *ops;
149
150 /* Socket 0 register offset address */
151 u32 s0_regs;
152 /* Socket 0 TX buffer offset address and size */
153 u32 s0_tx_buf;
154 u16 s0_tx_buf_size;
155 /* Socket 0 RX buffer offset address and size */
156 u32 s0_rx_buf;
157 u16 s0_rx_buf_size;
158
159 int irq;
160 int link_irq;
161 int link_gpio;
162
163 struct napi_struct napi;
164 struct net_device *ndev;
165 bool promisc;
166 u32 msg_enable;
167
168 struct workqueue_struct *xfer_wq;
169 struct work_struct rx_work;
170 struct sk_buff *tx_skb;
171 struct work_struct tx_work;
172 struct work_struct setrx_work;
173 struct work_struct restart_work;
174};
175
176/************************************************************************
177 *
178 * Lowlevel I/O functions
179 *
180 ***********************************************************************/
181
182struct w5100_mmio_priv {
183 void __iomem *base;
184 /* Serialize access in indirect address mode */
185 spinlock_t reg_lock;
186};
187
188static inline struct w5100_mmio_priv *w5100_mmio_priv(struct net_device *dev)
189{
190 return w5100_ops_priv(dev);
191}
192
193static inline void __iomem *w5100_mmio(struct net_device *ndev)
194{
195 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
196
197 return mmio_priv->base;
198}
199
200/*
201 * In direct address mode host system can directly access W5100 registers
202 * after mapping to Memory-Mapped I/O space.
203 *
204 * 0x8000 bytes are required for memory space.
205 */
206static inline int w5100_read_direct(struct net_device *ndev, u32 addr)
207{
208 return ioread8(w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT));
209}
210
211static inline int __w5100_write_direct(struct net_device *ndev, u32 addr,
212 u8 data)
213{
214 iowrite8(data, w5100_mmio(ndev) + (addr << CONFIG_WIZNET_BUS_SHIFT));
215
216 return 0;
217}
218
219static inline int w5100_write_direct(struct net_device *ndev, u32 addr, u8 data)
220{
221 __w5100_write_direct(ndev, addr, data);
222 mmiowb();
223
224 return 0;
225}
226
227static int w5100_read16_direct(struct net_device *ndev, u32 addr)
228{
229 u16 data;
230 data = w5100_read_direct(ndev, addr) << 8;
231 data |= w5100_read_direct(ndev, addr + 1);
232 return data;
233}
234
235static int w5100_write16_direct(struct net_device *ndev, u32 addr, u16 data)
236{
237 __w5100_write_direct(ndev, addr, data >> 8);
238 __w5100_write_direct(ndev, addr + 1, data);
239 mmiowb();
240
241 return 0;
242}
243
244static int w5100_readbulk_direct(struct net_device *ndev, u32 addr, u8 *buf,
245 int len)
246{
247 int i;
248
249 for (i = 0; i < len; i++, addr++)
250 *buf++ = w5100_read_direct(ndev, addr);
251
252 return 0;
253}
254
255static int w5100_writebulk_direct(struct net_device *ndev, u32 addr,
256 const u8 *buf, int len)
257{
258 int i;
259
260 for (i = 0; i < len; i++, addr++)
261 __w5100_write_direct(ndev, addr, *buf++);
262
263 mmiowb();
264
265 return 0;
266}
267
268static int w5100_mmio_init(struct net_device *ndev)
269{
270 struct platform_device *pdev = to_platform_device(ndev->dev.parent);
271 struct w5100_priv *priv = netdev_priv(ndev);
272 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
273 struct resource *mem;
274
275 spin_lock_init(&mmio_priv->reg_lock);
276
277 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
278 mmio_priv->base = devm_ioremap_resource(&pdev->dev, mem);
279 if (IS_ERR(mmio_priv->base))
280 return PTR_ERR(mmio_priv->base);
281
282 netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, priv->irq);
283
284 return 0;
285}
286
287static const struct w5100_ops w5100_mmio_direct_ops = {
288 .chip_id = W5100,
289 .read = w5100_read_direct,
290 .write = w5100_write_direct,
291 .read16 = w5100_read16_direct,
292 .write16 = w5100_write16_direct,
293 .readbulk = w5100_readbulk_direct,
294 .writebulk = w5100_writebulk_direct,
295 .init = w5100_mmio_init,
296};
297
298/*
299 * In indirect address mode host system indirectly accesses registers by
300 * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
301 * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
302 * Mode Register (MR) is directly accessible.
303 *
304 * Only 0x04 bytes are required for memory space.
305 */
306#define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */
307#define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */
308
309static int w5100_read_indirect(struct net_device *ndev, u32 addr)
310{
311 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
312 unsigned long flags;
313 u8 data;
314
315 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
316 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
317 data = w5100_read_direct(ndev, W5100_IDM_DR);
318 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
319
320 return data;
321}
322
323static int w5100_write_indirect(struct net_device *ndev, u32 addr, u8 data)
324{
325 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
326 unsigned long flags;
327
328 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
329 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
330 w5100_write_direct(ndev, W5100_IDM_DR, data);
331 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
332
333 return 0;
334}
335
336static int w5100_read16_indirect(struct net_device *ndev, u32 addr)
337{
338 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
339 unsigned long flags;
340 u16 data;
341
342 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
343 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
344 data = w5100_read_direct(ndev, W5100_IDM_DR) << 8;
345 data |= w5100_read_direct(ndev, W5100_IDM_DR);
346 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
347
348 return data;
349}
350
351static int w5100_write16_indirect(struct net_device *ndev, u32 addr, u16 data)
352{
353 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
354 unsigned long flags;
355
356 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
357 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
358 __w5100_write_direct(ndev, W5100_IDM_DR, data >> 8);
359 w5100_write_direct(ndev, W5100_IDM_DR, data);
360 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
361
362 return 0;
363}
364
365static int w5100_readbulk_indirect(struct net_device *ndev, u32 addr, u8 *buf,
366 int len)
367{
368 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
369 unsigned long flags;
370 int i;
371
372 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
373 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
374
375 for (i = 0; i < len; i++)
376 *buf++ = w5100_read_direct(ndev, W5100_IDM_DR);
377
378 mmiowb();
379 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
380
381 return 0;
382}
383
384static int w5100_writebulk_indirect(struct net_device *ndev, u32 addr,
385 const u8 *buf, int len)
386{
387 struct w5100_mmio_priv *mmio_priv = w5100_mmio_priv(ndev);
388 unsigned long flags;
389 int i;
390
391 spin_lock_irqsave(&mmio_priv->reg_lock, flags);
392 w5100_write16_direct(ndev, W5100_IDM_AR, addr);
393
394 for (i = 0; i < len; i++)
395 __w5100_write_direct(ndev, W5100_IDM_DR, *buf++);
396
397 mmiowb();
398 spin_unlock_irqrestore(&mmio_priv->reg_lock, flags);
399
400 return 0;
401}
402
403static int w5100_reset_indirect(struct net_device *ndev)
404{
405 w5100_write_direct(ndev, W5100_MR, MR_RST);
406 mdelay(5);
407 w5100_write_direct(ndev, W5100_MR, MR_PB | MR_AI | MR_IND);
408
409 return 0;
410}
411
412static const struct w5100_ops w5100_mmio_indirect_ops = {
413 .chip_id = W5100,
414 .read = w5100_read_indirect,
415 .write = w5100_write_indirect,
416 .read16 = w5100_read16_indirect,
417 .write16 = w5100_write16_indirect,
418 .readbulk = w5100_readbulk_indirect,
419 .writebulk = w5100_writebulk_indirect,
420 .init = w5100_mmio_init,
421 .reset = w5100_reset_indirect,
422};
423
424#if defined(CONFIG_WIZNET_BUS_DIRECT)
425
426static int w5100_read(struct w5100_priv *priv, u32 addr)
427{
428 return w5100_read_direct(priv->ndev, addr);
429}
430
431static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
432{
433 return w5100_write_direct(priv->ndev, addr, data);
434}
435
436static int w5100_read16(struct w5100_priv *priv, u32 addr)
437{
438 return w5100_read16_direct(priv->ndev, addr);
439}
440
441static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
442{
443 return w5100_write16_direct(priv->ndev, addr, data);
444}
445
446static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
447{
448 return w5100_readbulk_direct(priv->ndev, addr, buf, len);
449}
450
451static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
452 int len)
453{
454 return w5100_writebulk_direct(priv->ndev, addr, buf, len);
455}
456
457#elif defined(CONFIG_WIZNET_BUS_INDIRECT)
458
459static int w5100_read(struct w5100_priv *priv, u32 addr)
460{
461 return w5100_read_indirect(priv->ndev, addr);
462}
463
464static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
465{
466 return w5100_write_indirect(priv->ndev, addr, data);
467}
468
469static int w5100_read16(struct w5100_priv *priv, u32 addr)
470{
471 return w5100_read16_indirect(priv->ndev, addr);
472}
473
474static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
475{
476 return w5100_write16_indirect(priv->ndev, addr, data);
477}
478
479static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
480{
481 return w5100_readbulk_indirect(priv->ndev, addr, buf, len);
482}
483
484static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
485 int len)
486{
487 return w5100_writebulk_indirect(priv->ndev, addr, buf, len);
488}
489
490#else /* CONFIG_WIZNET_BUS_ANY */
491
492static int w5100_read(struct w5100_priv *priv, u32 addr)
493{
494 return priv->ops->read(priv->ndev, addr);
495}
496
497static int w5100_write(struct w5100_priv *priv, u32 addr, u8 data)
498{
499 return priv->ops->write(priv->ndev, addr, data);
500}
501
502static int w5100_read16(struct w5100_priv *priv, u32 addr)
503{
504 return priv->ops->read16(priv->ndev, addr);
505}
506
507static int w5100_write16(struct w5100_priv *priv, u32 addr, u16 data)
508{
509 return priv->ops->write16(priv->ndev, addr, data);
510}
511
512static int w5100_readbulk(struct w5100_priv *priv, u32 addr, u8 *buf, int len)
513{
514 return priv->ops->readbulk(priv->ndev, addr, buf, len);
515}
516
517static int w5100_writebulk(struct w5100_priv *priv, u32 addr, const u8 *buf,
518 int len)
519{
520 return priv->ops->writebulk(priv->ndev, addr, buf, len);
521}
522
523#endif
524
525static int w5100_readbuf(struct w5100_priv *priv, u16 offset, u8 *buf, int len)
526{
527 u32 addr;
528 int remain = 0;
529 int ret;
530 const u32 mem_start = priv->s0_rx_buf;
531 const u16 mem_size = priv->s0_rx_buf_size;
532
533 offset %= mem_size;
534 addr = mem_start + offset;
535
536 if (offset + len > mem_size) {
537 remain = (offset + len) % mem_size;
538 len = mem_size - offset;
539 }
540
541 ret = w5100_readbulk(priv, addr, buf, len);
542 if (ret || !remain)
543 return ret;
544
545 return w5100_readbulk(priv, mem_start, buf + len, remain);
546}
547
548static int w5100_writebuf(struct w5100_priv *priv, u16 offset, const u8 *buf,
549 int len)
550{
551 u32 addr;
552 int ret;
553 int remain = 0;
554 const u32 mem_start = priv->s0_tx_buf;
555 const u16 mem_size = priv->s0_tx_buf_size;
556
557 offset %= mem_size;
558 addr = mem_start + offset;
559
560 if (offset + len > mem_size) {
561 remain = (offset + len) % mem_size;
562 len = mem_size - offset;
563 }
564
565 ret = w5100_writebulk(priv, addr, buf, len);
566 if (ret || !remain)
567 return ret;
568
569 return w5100_writebulk(priv, mem_start, buf + len, remain);
570}
571
572static int w5100_reset(struct w5100_priv *priv)
573{
574 if (priv->ops->reset)
575 return priv->ops->reset(priv->ndev);
576
577 w5100_write(priv, W5100_MR, MR_RST);
578 mdelay(5);
579 w5100_write(priv, W5100_MR, MR_PB);
580
581 return 0;
582}
583
584static int w5100_command(struct w5100_priv *priv, u16 cmd)
585{
586 unsigned long timeout;
587
588 w5100_write(priv, W5100_S0_CR(priv), cmd);
589
590 timeout = jiffies + msecs_to_jiffies(100);
591
592 while (w5100_read(priv, W5100_S0_CR(priv)) != 0) {
593 if (time_after(jiffies, timeout))
594 return -EIO;
595 cpu_relax();
596 }
597
598 return 0;
599}
600
601static void w5100_write_macaddr(struct w5100_priv *priv)
602{
603 struct net_device *ndev = priv->ndev;
604
605 w5100_writebulk(priv, W5100_SHAR, ndev->dev_addr, ETH_ALEN);
606}
607
608static void w5100_socket_intr_mask(struct w5100_priv *priv, u8 mask)
609{
610 u32 imr;
611
612 if (priv->ops->chip_id == W5500)
613 imr = W5500_SIMR;
614 else
615 imr = W5100_IMR;
616
617 w5100_write(priv, imr, mask);
618}
619
620static void w5100_enable_intr(struct w5100_priv *priv)
621{
622 w5100_socket_intr_mask(priv, IR_S0);
623}
624
625static void w5100_disable_intr(struct w5100_priv *priv)
626{
627 w5100_socket_intr_mask(priv, 0);
628}
629
630static void w5100_memory_configure(struct w5100_priv *priv)
631{
632 /* Configure 16K of internal memory
633 * as 8K RX buffer and 8K TX buffer
634 */
635 w5100_write(priv, W5100_RMSR, 0x03);
636 w5100_write(priv, W5100_TMSR, 0x03);
637}
638
639static void w5200_memory_configure(struct w5100_priv *priv)
640{
641 int i;
642
643 /* Configure internal RX memory as 16K RX buffer and
644 * internal TX memory as 16K TX buffer
645 */
646 w5100_write(priv, W5200_Sn_RXMEM_SIZE(0), 0x10);
647 w5100_write(priv, W5200_Sn_TXMEM_SIZE(0), 0x10);
648
649 for (i = 1; i < 8; i++) {
650 w5100_write(priv, W5200_Sn_RXMEM_SIZE(i), 0);
651 w5100_write(priv, W5200_Sn_TXMEM_SIZE(i), 0);
652 }
653}
654
655static void w5500_memory_configure(struct w5100_priv *priv)
656{
657 int i;
658
659 /* Configure internal RX memory as 16K RX buffer and
660 * internal TX memory as 16K TX buffer
661 */
662 w5100_write(priv, W5500_Sn_RXMEM_SIZE(0), 0x10);
663 w5100_write(priv, W5500_Sn_TXMEM_SIZE(0), 0x10);
664
665 for (i = 1; i < 8; i++) {
666 w5100_write(priv, W5500_Sn_RXMEM_SIZE(i), 0);
667 w5100_write(priv, W5500_Sn_TXMEM_SIZE(i), 0);
668 }
669}
670
671static int w5100_hw_reset(struct w5100_priv *priv)
672{
673 u32 rtr;
674
675 w5100_reset(priv);
676
677 w5100_disable_intr(priv);
678 w5100_write_macaddr(priv);
679
680 switch (priv->ops->chip_id) {
681 case W5100:
682 w5100_memory_configure(priv);
683 rtr = W5100_RTR;
684 break;
685 case W5200:
686 w5200_memory_configure(priv);
687 rtr = W5100_RTR;
688 break;
689 case W5500:
690 w5500_memory_configure(priv);
691 rtr = W5500_RTR;
692 break;
693 default:
694 return -EINVAL;
695 }
696
697 if (w5100_read16(priv, rtr) != RTR_DEFAULT)
698 return -ENODEV;
699
700 return 0;
701}
702
703static void w5100_hw_start(struct w5100_priv *priv)
704{
705 u8 mode = S0_MR_MACRAW;
706
707 if (!priv->promisc) {
708 if (priv->ops->chip_id == W5500)
709 mode |= W5500_S0_MR_MF;
710 else
711 mode |= S0_MR_MF;
712 }
713
714 w5100_write(priv, W5100_S0_MR(priv), mode);
715 w5100_command(priv, S0_CR_OPEN);
716 w5100_enable_intr(priv);
717}
718
719static void w5100_hw_close(struct w5100_priv *priv)
720{
721 w5100_disable_intr(priv);
722 w5100_command(priv, S0_CR_CLOSE);
723}
724
725/***********************************************************************
726 *
727 * Device driver functions / callbacks
728 *
729 ***********************************************************************/
730
731static void w5100_get_drvinfo(struct net_device *ndev,
732 struct ethtool_drvinfo *info)
733{
734 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
735 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
736 strlcpy(info->bus_info, dev_name(ndev->dev.parent),
737 sizeof(info->bus_info));
738}
739
740static u32 w5100_get_link(struct net_device *ndev)
741{
742 struct w5100_priv *priv = netdev_priv(ndev);
743
744 if (gpio_is_valid(priv->link_gpio))
745 return !!gpio_get_value(priv->link_gpio);
746
747 return 1;
748}
749
750static u32 w5100_get_msglevel(struct net_device *ndev)
751{
752 struct w5100_priv *priv = netdev_priv(ndev);
753
754 return priv->msg_enable;
755}
756
757static void w5100_set_msglevel(struct net_device *ndev, u32 value)
758{
759 struct w5100_priv *priv = netdev_priv(ndev);
760
761 priv->msg_enable = value;
762}
763
764static int w5100_get_regs_len(struct net_device *ndev)
765{
766 return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN;
767}
768
769static void w5100_get_regs(struct net_device *ndev,
770 struct ethtool_regs *regs, void *buf)
771{
772 struct w5100_priv *priv = netdev_priv(ndev);
773
774 regs->version = 1;
775 w5100_readbulk(priv, W5100_COMMON_REGS, buf, W5100_COMMON_REGS_LEN);
776 buf += W5100_COMMON_REGS_LEN;
777 w5100_readbulk(priv, S0_REGS(priv), buf, W5100_S0_REGS_LEN);
778}
779
780static void w5100_restart(struct net_device *ndev)
781{
782 struct w5100_priv *priv = netdev_priv(ndev);
783
784 netif_stop_queue(ndev);
785 w5100_hw_reset(priv);
786 w5100_hw_start(priv);
787 ndev->stats.tx_errors++;
788 netif_trans_update(ndev);
789 netif_wake_queue(ndev);
790}
791
792static void w5100_restart_work(struct work_struct *work)
793{
794 struct w5100_priv *priv = container_of(work, struct w5100_priv,
795 restart_work);
796
797 w5100_restart(priv->ndev);
798}
799
800static void w5100_tx_timeout(struct net_device *ndev)
801{
802 struct w5100_priv *priv = netdev_priv(ndev);
803
804 if (priv->ops->may_sleep)
805 schedule_work(&priv->restart_work);
806 else
807 w5100_restart(ndev);
808}
809
810static void w5100_tx_skb(struct net_device *ndev, struct sk_buff *skb)
811{
812 struct w5100_priv *priv = netdev_priv(ndev);
813 u16 offset;
814
815 offset = w5100_read16(priv, W5100_S0_TX_WR(priv));
816 w5100_writebuf(priv, offset, skb->data, skb->len);
817 w5100_write16(priv, W5100_S0_TX_WR(priv), offset + skb->len);
818 ndev->stats.tx_bytes += skb->len;
819 ndev->stats.tx_packets++;
820 dev_kfree_skb(skb);
821
822 w5100_command(priv, S0_CR_SEND);
823}
824
825static void w5100_tx_work(struct work_struct *work)
826{
827 struct w5100_priv *priv = container_of(work, struct w5100_priv,
828 tx_work);
829 struct sk_buff *skb = priv->tx_skb;
830
831 priv->tx_skb = NULL;
832
833 if (WARN_ON(!skb))
834 return;
835 w5100_tx_skb(priv->ndev, skb);
836}
837
838static int w5100_start_tx(struct sk_buff *skb, struct net_device *ndev)
839{
840 struct w5100_priv *priv = netdev_priv(ndev);
841
842 netif_stop_queue(ndev);
843
844 if (priv->ops->may_sleep) {
845 WARN_ON(priv->tx_skb);
846 priv->tx_skb = skb;
847 queue_work(priv->xfer_wq, &priv->tx_work);
848 } else {
849 w5100_tx_skb(ndev, skb);
850 }
851
852 return NETDEV_TX_OK;
853}
854
855static struct sk_buff *w5100_rx_skb(struct net_device *ndev)
856{
857 struct w5100_priv *priv = netdev_priv(ndev);
858 struct sk_buff *skb;
859 u16 rx_len;
860 u16 offset;
861 u8 header[2];
862 u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR(priv));
863
864 if (rx_buf_len == 0)
865 return NULL;
866
867 offset = w5100_read16(priv, W5100_S0_RX_RD(priv));
868 w5100_readbuf(priv, offset, header, 2);
869 rx_len = get_unaligned_be16(header) - 2;
870
871 skb = netdev_alloc_skb_ip_align(ndev, rx_len);
872 if (unlikely(!skb)) {
873 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + rx_buf_len);
874 w5100_command(priv, S0_CR_RECV);
875 ndev->stats.rx_dropped++;
876 return NULL;
877 }
878
879 skb_put(skb, rx_len);
880 w5100_readbuf(priv, offset + 2, skb->data, rx_len);
881 w5100_write16(priv, W5100_S0_RX_RD(priv), offset + 2 + rx_len);
882 w5100_command(priv, S0_CR_RECV);
883 skb->protocol = eth_type_trans(skb, ndev);
884
885 ndev->stats.rx_packets++;
886 ndev->stats.rx_bytes += rx_len;
887
888 return skb;
889}
890
891static void w5100_rx_work(struct work_struct *work)
892{
893 struct w5100_priv *priv = container_of(work, struct w5100_priv,
894 rx_work);
895 struct sk_buff *skb;
896
897 while ((skb = w5100_rx_skb(priv->ndev)))
898 netif_rx_ni(skb);
899
900 w5100_enable_intr(priv);
901}
902
903static int w5100_napi_poll(struct napi_struct *napi, int budget)
904{
905 struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi);
906 int rx_count;
907
908 for (rx_count = 0; rx_count < budget; rx_count++) {
909 struct sk_buff *skb = w5100_rx_skb(priv->ndev);
910
911 if (skb)
912 netif_receive_skb(skb);
913 else
914 break;
915 }
916
917 if (rx_count < budget) {
918 napi_complete_done(napi, rx_count);
919 w5100_enable_intr(priv);
920 }
921
922 return rx_count;
923}
924
925static irqreturn_t w5100_interrupt(int irq, void *ndev_instance)
926{
927 struct net_device *ndev = ndev_instance;
928 struct w5100_priv *priv = netdev_priv(ndev);
929
930 int ir = w5100_read(priv, W5100_S0_IR(priv));
931 if (!ir)
932 return IRQ_NONE;
933 w5100_write(priv, W5100_S0_IR(priv), ir);
934
935 if (ir & S0_IR_SENDOK) {
936 netif_dbg(priv, tx_done, ndev, "tx done\n");
937 netif_wake_queue(ndev);
938 }
939
940 if (ir & S0_IR_RECV) {
941 w5100_disable_intr(priv);
942
943 if (priv->ops->may_sleep)
944 queue_work(priv->xfer_wq, &priv->rx_work);
945 else if (napi_schedule_prep(&priv->napi))
946 __napi_schedule(&priv->napi);
947 }
948
949 return IRQ_HANDLED;
950}
951
952static irqreturn_t w5100_detect_link(int irq, void *ndev_instance)
953{
954 struct net_device *ndev = ndev_instance;
955 struct w5100_priv *priv = netdev_priv(ndev);
956
957 if (netif_running(ndev)) {
958 if (gpio_get_value(priv->link_gpio) != 0) {
959 netif_info(priv, link, ndev, "link is up\n");
960 netif_carrier_on(ndev);
961 } else {
962 netif_info(priv, link, ndev, "link is down\n");
963 netif_carrier_off(ndev);
964 }
965 }
966
967 return IRQ_HANDLED;
968}
969
970static void w5100_setrx_work(struct work_struct *work)
971{
972 struct w5100_priv *priv = container_of(work, struct w5100_priv,
973 setrx_work);
974
975 w5100_hw_start(priv);
976}
977
978static void w5100_set_rx_mode(struct net_device *ndev)
979{
980 struct w5100_priv *priv = netdev_priv(ndev);
981 bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
982
983 if (priv->promisc != set_promisc) {
984 priv->promisc = set_promisc;
985
986 if (priv->ops->may_sleep)
987 schedule_work(&priv->setrx_work);
988 else
989 w5100_hw_start(priv);
990 }
991}
992
993static int w5100_set_macaddr(struct net_device *ndev, void *addr)
994{
995 struct w5100_priv *priv = netdev_priv(ndev);
996 struct sockaddr *sock_addr = addr;
997
998 if (!is_valid_ether_addr(sock_addr->sa_data))
999 return -EADDRNOTAVAIL;
1000 memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
1001 w5100_write_macaddr(priv);
1002 return 0;
1003}
1004
1005static int w5100_open(struct net_device *ndev)
1006{
1007 struct w5100_priv *priv = netdev_priv(ndev);
1008
1009 netif_info(priv, ifup, ndev, "enabling\n");
1010 w5100_hw_start(priv);
1011 napi_enable(&priv->napi);
1012 netif_start_queue(ndev);
1013 if (!gpio_is_valid(priv->link_gpio) ||
1014 gpio_get_value(priv->link_gpio) != 0)
1015 netif_carrier_on(ndev);
1016 return 0;
1017}
1018
1019static int w5100_stop(struct net_device *ndev)
1020{
1021 struct w5100_priv *priv = netdev_priv(ndev);
1022
1023 netif_info(priv, ifdown, ndev, "shutting down\n");
1024 w5100_hw_close(priv);
1025 netif_carrier_off(ndev);
1026 netif_stop_queue(ndev);
1027 napi_disable(&priv->napi);
1028 return 0;
1029}
1030
1031static const struct ethtool_ops w5100_ethtool_ops = {
1032 .get_drvinfo = w5100_get_drvinfo,
1033 .get_msglevel = w5100_get_msglevel,
1034 .set_msglevel = w5100_set_msglevel,
1035 .get_link = w5100_get_link,
1036 .get_regs_len = w5100_get_regs_len,
1037 .get_regs = w5100_get_regs,
1038};
1039
1040static const struct net_device_ops w5100_netdev_ops = {
1041 .ndo_open = w5100_open,
1042 .ndo_stop = w5100_stop,
1043 .ndo_start_xmit = w5100_start_tx,
1044 .ndo_tx_timeout = w5100_tx_timeout,
1045 .ndo_set_rx_mode = w5100_set_rx_mode,
1046 .ndo_set_mac_address = w5100_set_macaddr,
1047 .ndo_validate_addr = eth_validate_addr,
1048};
1049
1050static int w5100_mmio_probe(struct platform_device *pdev)
1051{
1052 struct wiznet_platform_data *data = dev_get_platdata(&pdev->dev);
1053 const void *mac_addr = NULL;
1054 struct resource *mem;
1055 const struct w5100_ops *ops;
1056 int irq;
1057
1058 if (data && is_valid_ether_addr(data->mac_addr))
1059 mac_addr = data->mac_addr;
1060
1061 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1062 if (resource_size(mem) < W5100_BUS_DIRECT_SIZE)
1063 ops = &w5100_mmio_indirect_ops;
1064 else
1065 ops = &w5100_mmio_direct_ops;
1066
1067 irq = platform_get_irq(pdev, 0);
1068 if (irq < 0)
1069 return irq;
1070
1071 return w5100_probe(&pdev->dev, ops, sizeof(struct w5100_mmio_priv),
1072 mac_addr, irq, data ? data->link_gpio : -EINVAL);
1073}
1074
1075static int w5100_mmio_remove(struct platform_device *pdev)
1076{
1077 return w5100_remove(&pdev->dev);
1078}
1079
1080void *w5100_ops_priv(const struct net_device *ndev)
1081{
1082 return netdev_priv(ndev) +
1083 ALIGN(sizeof(struct w5100_priv), NETDEV_ALIGN);
1084}
1085EXPORT_SYMBOL_GPL(w5100_ops_priv);
1086
1087int w5100_probe(struct device *dev, const struct w5100_ops *ops,
1088 int sizeof_ops_priv, const void *mac_addr, int irq,
1089 int link_gpio)
1090{
1091 struct w5100_priv *priv;
1092 struct net_device *ndev;
1093 int err;
1094 size_t alloc_size;
1095
1096 alloc_size = sizeof(*priv);
1097 if (sizeof_ops_priv) {
1098 alloc_size = ALIGN(alloc_size, NETDEV_ALIGN);
1099 alloc_size += sizeof_ops_priv;
1100 }
1101 alloc_size += NETDEV_ALIGN - 1;
1102
1103 ndev = alloc_etherdev(alloc_size);
1104 if (!ndev)
1105 return -ENOMEM;
1106 SET_NETDEV_DEV(ndev, dev);
1107 dev_set_drvdata(dev, ndev);
1108 priv = netdev_priv(ndev);
1109
1110 switch (ops->chip_id) {
1111 case W5100:
1112 priv->s0_regs = W5100_S0_REGS;
1113 priv->s0_tx_buf = W5100_TX_MEM_START;
1114 priv->s0_tx_buf_size = W5100_TX_MEM_SIZE;
1115 priv->s0_rx_buf = W5100_RX_MEM_START;
1116 priv->s0_rx_buf_size = W5100_RX_MEM_SIZE;
1117 break;
1118 case W5200:
1119 priv->s0_regs = W5200_S0_REGS;
1120 priv->s0_tx_buf = W5200_TX_MEM_START;
1121 priv->s0_tx_buf_size = W5200_TX_MEM_SIZE;
1122 priv->s0_rx_buf = W5200_RX_MEM_START;
1123 priv->s0_rx_buf_size = W5200_RX_MEM_SIZE;
1124 break;
1125 case W5500:
1126 priv->s0_regs = W5500_S0_REGS;
1127 priv->s0_tx_buf = W5500_TX_MEM_START;
1128 priv->s0_tx_buf_size = W5500_TX_MEM_SIZE;
1129 priv->s0_rx_buf = W5500_RX_MEM_START;
1130 priv->s0_rx_buf_size = W5500_RX_MEM_SIZE;
1131 break;
1132 default:
1133 err = -EINVAL;
1134 goto err_register;
1135 }
1136
1137 priv->ndev = ndev;
1138 priv->ops = ops;
1139 priv->irq = irq;
1140 priv->link_gpio = link_gpio;
1141
1142 ndev->netdev_ops = &w5100_netdev_ops;
1143 ndev->ethtool_ops = &w5100_ethtool_ops;
1144 netif_napi_add(ndev, &priv->napi, w5100_napi_poll, 16);
1145
1146 /* This chip doesn't support VLAN packets with normal MTU,
1147 * so disable VLAN for this device.
1148 */
1149 ndev->features |= NETIF_F_VLAN_CHALLENGED;
1150
1151 err = register_netdev(ndev);
1152 if (err < 0)
1153 goto err_register;
1154
1155 priv->xfer_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0,
1156 netdev_name(ndev));
1157 if (!priv->xfer_wq) {
1158 err = -ENOMEM;
1159 goto err_wq;
1160 }
1161
1162 INIT_WORK(&priv->rx_work, w5100_rx_work);
1163 INIT_WORK(&priv->tx_work, w5100_tx_work);
1164 INIT_WORK(&priv->setrx_work, w5100_setrx_work);
1165 INIT_WORK(&priv->restart_work, w5100_restart_work);
1166
1167 if (mac_addr)
1168 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
1169 else
1170 eth_hw_addr_random(ndev);
1171
1172 if (priv->ops->init) {
1173 err = priv->ops->init(priv->ndev);
1174 if (err)
1175 goto err_hw;
1176 }
1177
1178 err = w5100_hw_reset(priv);
1179 if (err)
1180 goto err_hw;
1181
1182 if (ops->may_sleep) {
1183 err = request_threaded_irq(priv->irq, NULL, w5100_interrupt,
1184 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1185 netdev_name(ndev), ndev);
1186 } else {
1187 err = request_irq(priv->irq, w5100_interrupt,
1188 IRQF_TRIGGER_LOW, netdev_name(ndev), ndev);
1189 }
1190 if (err)
1191 goto err_hw;
1192
1193 if (gpio_is_valid(priv->link_gpio)) {
1194 char *link_name = devm_kzalloc(dev, 16, GFP_KERNEL);
1195
1196 if (!link_name) {
1197 err = -ENOMEM;
1198 goto err_gpio;
1199 }
1200 snprintf(link_name, 16, "%s-link", netdev_name(ndev));
1201 priv->link_irq = gpio_to_irq(priv->link_gpio);
1202 if (request_any_context_irq(priv->link_irq, w5100_detect_link,
1203 IRQF_TRIGGER_RISING |
1204 IRQF_TRIGGER_FALLING,
1205 link_name, priv->ndev) < 0)
1206 priv->link_gpio = -EINVAL;
1207 }
1208
1209 return 0;
1210
1211err_gpio:
1212 free_irq(priv->irq, ndev);
1213err_hw:
1214 destroy_workqueue(priv->xfer_wq);
1215err_wq:
1216 unregister_netdev(ndev);
1217err_register:
1218 free_netdev(ndev);
1219 return err;
1220}
1221EXPORT_SYMBOL_GPL(w5100_probe);
1222
1223int w5100_remove(struct device *dev)
1224{
1225 struct net_device *ndev = dev_get_drvdata(dev);
1226 struct w5100_priv *priv = netdev_priv(ndev);
1227
1228 w5100_hw_reset(priv);
1229 free_irq(priv->irq, ndev);
1230 if (gpio_is_valid(priv->link_gpio))
1231 free_irq(priv->link_irq, ndev);
1232
1233 flush_work(&priv->setrx_work);
1234 flush_work(&priv->restart_work);
1235 destroy_workqueue(priv->xfer_wq);
1236
1237 unregister_netdev(ndev);
1238 free_netdev(ndev);
1239 return 0;
1240}
1241EXPORT_SYMBOL_GPL(w5100_remove);
1242
1243#ifdef CONFIG_PM_SLEEP
1244static int w5100_suspend(struct device *dev)
1245{
1246 struct net_device *ndev = dev_get_drvdata(dev);
1247 struct w5100_priv *priv = netdev_priv(ndev);
1248
1249 if (netif_running(ndev)) {
1250 netif_carrier_off(ndev);
1251 netif_device_detach(ndev);
1252
1253 w5100_hw_close(priv);
1254 }
1255 return 0;
1256}
1257
1258static int w5100_resume(struct device *dev)
1259{
1260 struct net_device *ndev = dev_get_drvdata(dev);
1261 struct w5100_priv *priv = netdev_priv(ndev);
1262
1263 if (netif_running(ndev)) {
1264 w5100_hw_reset(priv);
1265 w5100_hw_start(priv);
1266
1267 netif_device_attach(ndev);
1268 if (!gpio_is_valid(priv->link_gpio) ||
1269 gpio_get_value(priv->link_gpio) != 0)
1270 netif_carrier_on(ndev);
1271 }
1272 return 0;
1273}
1274#endif /* CONFIG_PM_SLEEP */
1275
1276SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume);
1277EXPORT_SYMBOL_GPL(w5100_pm_ops);
1278
1279static struct platform_driver w5100_mmio_driver = {
1280 .driver = {
1281 .name = DRV_NAME,
1282 .pm = &w5100_pm_ops,
1283 },
1284 .probe = w5100_mmio_probe,
1285 .remove = w5100_mmio_remove,
1286};
1287module_platform_driver(w5100_mmio_driver);
1/*
2 * Ethernet driver for the WIZnet W5100 chip.
3 *
4 * Copyright (C) 2006-2008 WIZnet Co.,Ltd.
5 * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/kconfig.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/wiznet.h>
17#include <linux/ethtool.h>
18#include <linux/skbuff.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/io.h>
25#include <linux/ioport.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/gpio.h>
29
30#define DRV_NAME "w5100"
31#define DRV_VERSION "2012-04-04"
32
33MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION);
34MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
35MODULE_ALIAS("platform:"DRV_NAME);
36MODULE_LICENSE("GPL");
37
38/*
39 * Registers
40 */
41#define W5100_COMMON_REGS 0x0000
42#define W5100_MR 0x0000 /* Mode Register */
43#define MR_RST 0x80 /* S/W reset */
44#define MR_PB 0x10 /* Ping block */
45#define MR_AI 0x02 /* Address Auto-Increment */
46#define MR_IND 0x01 /* Indirect mode */
47#define W5100_SHAR 0x0009 /* Source MAC address */
48#define W5100_IR 0x0015 /* Interrupt Register */
49#define W5100_IMR 0x0016 /* Interrupt Mask Register */
50#define IR_S0 0x01 /* S0 interrupt */
51#define W5100_RTR 0x0017 /* Retry Time-value Register */
52#define RTR_DEFAULT 2000 /* =0x07d0 (2000) */
53#define W5100_RMSR 0x001a /* Receive Memory Size */
54#define W5100_TMSR 0x001b /* Transmit Memory Size */
55#define W5100_COMMON_REGS_LEN 0x0040
56
57#define W5100_S0_REGS 0x0400
58#define W5100_S0_MR 0x0400 /* S0 Mode Register */
59#define S0_MR_MACRAW 0x04 /* MAC RAW mode (promiscous) */
60#define S0_MR_MACRAW_MF 0x44 /* MAC RAW mode (filtered) */
61#define W5100_S0_CR 0x0401 /* S0 Command Register */
62#define S0_CR_OPEN 0x01 /* OPEN command */
63#define S0_CR_CLOSE 0x10 /* CLOSE command */
64#define S0_CR_SEND 0x20 /* SEND command */
65#define S0_CR_RECV 0x40 /* RECV command */
66#define W5100_S0_IR 0x0402 /* S0 Interrupt Register */
67#define S0_IR_SENDOK 0x10 /* complete sending */
68#define S0_IR_RECV 0x04 /* receiving data */
69#define W5100_S0_SR 0x0403 /* S0 Status Register */
70#define S0_SR_MACRAW 0x42 /* mac raw mode */
71#define W5100_S0_TX_FSR 0x0420 /* S0 Transmit free memory size */
72#define W5100_S0_TX_RD 0x0422 /* S0 Transmit memory read pointer */
73#define W5100_S0_TX_WR 0x0424 /* S0 Transmit memory write pointer */
74#define W5100_S0_RX_RSR 0x0426 /* S0 Receive free memory size */
75#define W5100_S0_RX_RD 0x0428 /* S0 Receive memory read pointer */
76#define W5100_S0_REGS_LEN 0x0040
77
78#define W5100_TX_MEM_START 0x4000
79#define W5100_TX_MEM_END 0x5fff
80#define W5100_TX_MEM_MASK 0x1fff
81#define W5100_RX_MEM_START 0x6000
82#define W5100_RX_MEM_END 0x7fff
83#define W5100_RX_MEM_MASK 0x1fff
84
85/*
86 * Device driver private data structure
87 */
88struct w5100_priv {
89 void __iomem *base;
90 spinlock_t reg_lock;
91 bool indirect;
92 u8 (*read)(struct w5100_priv *priv, u16 addr);
93 void (*write)(struct w5100_priv *priv, u16 addr, u8 data);
94 u16 (*read16)(struct w5100_priv *priv, u16 addr);
95 void (*write16)(struct w5100_priv *priv, u16 addr, u16 data);
96 void (*readbuf)(struct w5100_priv *priv, u16 addr, u8 *buf, int len);
97 void (*writebuf)(struct w5100_priv *priv, u16 addr, u8 *buf, int len);
98 int irq;
99 int link_irq;
100 int link_gpio;
101
102 struct napi_struct napi;
103 struct net_device *ndev;
104 bool promisc;
105 u32 msg_enable;
106};
107
108/************************************************************************
109 *
110 * Lowlevel I/O functions
111 *
112 ***********************************************************************/
113
114/*
115 * In direct address mode host system can directly access W5100 registers
116 * after mapping to Memory-Mapped I/O space.
117 *
118 * 0x8000 bytes are required for memory space.
119 */
120static inline u8 w5100_read_direct(struct w5100_priv *priv, u16 addr)
121{
122 return ioread8(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
123}
124
125static inline void w5100_write_direct(struct w5100_priv *priv,
126 u16 addr, u8 data)
127{
128 iowrite8(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
129}
130
131static u16 w5100_read16_direct(struct w5100_priv *priv, u16 addr)
132{
133 u16 data;
134 data = w5100_read_direct(priv, addr) << 8;
135 data |= w5100_read_direct(priv, addr + 1);
136 return data;
137}
138
139static void w5100_write16_direct(struct w5100_priv *priv, u16 addr, u16 data)
140{
141 w5100_write_direct(priv, addr, data >> 8);
142 w5100_write_direct(priv, addr + 1, data);
143}
144
145static void w5100_readbuf_direct(struct w5100_priv *priv,
146 u16 offset, u8 *buf, int len)
147{
148 u16 addr = W5100_RX_MEM_START + (offset & W5100_RX_MEM_MASK);
149 int i;
150
151 for (i = 0; i < len; i++, addr++) {
152 if (unlikely(addr > W5100_RX_MEM_END))
153 addr = W5100_RX_MEM_START;
154 *buf++ = w5100_read_direct(priv, addr);
155 }
156}
157
158static void w5100_writebuf_direct(struct w5100_priv *priv,
159 u16 offset, u8 *buf, int len)
160{
161 u16 addr = W5100_TX_MEM_START + (offset & W5100_TX_MEM_MASK);
162 int i;
163
164 for (i = 0; i < len; i++, addr++) {
165 if (unlikely(addr > W5100_TX_MEM_END))
166 addr = W5100_TX_MEM_START;
167 w5100_write_direct(priv, addr, *buf++);
168 }
169}
170
171/*
172 * In indirect address mode host system indirectly accesses registers by
173 * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
174 * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
175 * Mode Register (MR) is directly accessible.
176 *
177 * Only 0x04 bytes are required for memory space.
178 */
179#define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */
180#define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */
181
182static u8 w5100_read_indirect(struct w5100_priv *priv, u16 addr)
183{
184 unsigned long flags;
185 u8 data;
186
187 spin_lock_irqsave(&priv->reg_lock, flags);
188 w5100_write16_direct(priv, W5100_IDM_AR, addr);
189 mmiowb();
190 data = w5100_read_direct(priv, W5100_IDM_DR);
191 spin_unlock_irqrestore(&priv->reg_lock, flags);
192
193 return data;
194}
195
196static void w5100_write_indirect(struct w5100_priv *priv, u16 addr, u8 data)
197{
198 unsigned long flags;
199
200 spin_lock_irqsave(&priv->reg_lock, flags);
201 w5100_write16_direct(priv, W5100_IDM_AR, addr);
202 mmiowb();
203 w5100_write_direct(priv, W5100_IDM_DR, data);
204 mmiowb();
205 spin_unlock_irqrestore(&priv->reg_lock, flags);
206}
207
208static u16 w5100_read16_indirect(struct w5100_priv *priv, u16 addr)
209{
210 unsigned long flags;
211 u16 data;
212
213 spin_lock_irqsave(&priv->reg_lock, flags);
214 w5100_write16_direct(priv, W5100_IDM_AR, addr);
215 mmiowb();
216 data = w5100_read_direct(priv, W5100_IDM_DR) << 8;
217 data |= w5100_read_direct(priv, W5100_IDM_DR);
218 spin_unlock_irqrestore(&priv->reg_lock, flags);
219
220 return data;
221}
222
223static void w5100_write16_indirect(struct w5100_priv *priv, u16 addr, u16 data)
224{
225 unsigned long flags;
226
227 spin_lock_irqsave(&priv->reg_lock, flags);
228 w5100_write16_direct(priv, W5100_IDM_AR, addr);
229 mmiowb();
230 w5100_write_direct(priv, W5100_IDM_DR, data >> 8);
231 w5100_write_direct(priv, W5100_IDM_DR, data);
232 mmiowb();
233 spin_unlock_irqrestore(&priv->reg_lock, flags);
234}
235
236static void w5100_readbuf_indirect(struct w5100_priv *priv,
237 u16 offset, u8 *buf, int len)
238{
239 u16 addr = W5100_RX_MEM_START + (offset & W5100_RX_MEM_MASK);
240 unsigned long flags;
241 int i;
242
243 spin_lock_irqsave(&priv->reg_lock, flags);
244 w5100_write16_direct(priv, W5100_IDM_AR, addr);
245 mmiowb();
246
247 for (i = 0; i < len; i++, addr++) {
248 if (unlikely(addr > W5100_RX_MEM_END)) {
249 addr = W5100_RX_MEM_START;
250 w5100_write16_direct(priv, W5100_IDM_AR, addr);
251 mmiowb();
252 }
253 *buf++ = w5100_read_direct(priv, W5100_IDM_DR);
254 }
255 mmiowb();
256 spin_unlock_irqrestore(&priv->reg_lock, flags);
257}
258
259static void w5100_writebuf_indirect(struct w5100_priv *priv,
260 u16 offset, u8 *buf, int len)
261{
262 u16 addr = W5100_TX_MEM_START + (offset & W5100_TX_MEM_MASK);
263 unsigned long flags;
264 int i;
265
266 spin_lock_irqsave(&priv->reg_lock, flags);
267 w5100_write16_direct(priv, W5100_IDM_AR, addr);
268 mmiowb();
269
270 for (i = 0; i < len; i++, addr++) {
271 if (unlikely(addr > W5100_TX_MEM_END)) {
272 addr = W5100_TX_MEM_START;
273 w5100_write16_direct(priv, W5100_IDM_AR, addr);
274 mmiowb();
275 }
276 w5100_write_direct(priv, W5100_IDM_DR, *buf++);
277 }
278 mmiowb();
279 spin_unlock_irqrestore(&priv->reg_lock, flags);
280}
281
282#if defined(CONFIG_WIZNET_BUS_DIRECT)
283#define w5100_read w5100_read_direct
284#define w5100_write w5100_write_direct
285#define w5100_read16 w5100_read16_direct
286#define w5100_write16 w5100_write16_direct
287#define w5100_readbuf w5100_readbuf_direct
288#define w5100_writebuf w5100_writebuf_direct
289
290#elif defined(CONFIG_WIZNET_BUS_INDIRECT)
291#define w5100_read w5100_read_indirect
292#define w5100_write w5100_write_indirect
293#define w5100_read16 w5100_read16_indirect
294#define w5100_write16 w5100_write16_indirect
295#define w5100_readbuf w5100_readbuf_indirect
296#define w5100_writebuf w5100_writebuf_indirect
297
298#else /* CONFIG_WIZNET_BUS_ANY */
299#define w5100_read priv->read
300#define w5100_write priv->write
301#define w5100_read16 priv->read16
302#define w5100_write16 priv->write16
303#define w5100_readbuf priv->readbuf
304#define w5100_writebuf priv->writebuf
305#endif
306
307static int w5100_command(struct w5100_priv *priv, u16 cmd)
308{
309 unsigned long timeout = jiffies + msecs_to_jiffies(100);
310
311 w5100_write(priv, W5100_S0_CR, cmd);
312 mmiowb();
313
314 while (w5100_read(priv, W5100_S0_CR) != 0) {
315 if (time_after(jiffies, timeout))
316 return -EIO;
317 cpu_relax();
318 }
319
320 return 0;
321}
322
323static void w5100_write_macaddr(struct w5100_priv *priv)
324{
325 struct net_device *ndev = priv->ndev;
326 int i;
327
328 for (i = 0; i < ETH_ALEN; i++)
329 w5100_write(priv, W5100_SHAR + i, ndev->dev_addr[i]);
330 mmiowb();
331}
332
333static void w5100_hw_reset(struct w5100_priv *priv)
334{
335 w5100_write_direct(priv, W5100_MR, MR_RST);
336 mmiowb();
337 mdelay(5);
338 w5100_write_direct(priv, W5100_MR, priv->indirect ?
339 MR_PB | MR_AI | MR_IND :
340 MR_PB);
341 mmiowb();
342 w5100_write(priv, W5100_IMR, 0);
343 w5100_write_macaddr(priv);
344
345 /* Configure 16K of internal memory
346 * as 8K RX buffer and 8K TX buffer
347 */
348 w5100_write(priv, W5100_RMSR, 0x03);
349 w5100_write(priv, W5100_TMSR, 0x03);
350 mmiowb();
351}
352
353static void w5100_hw_start(struct w5100_priv *priv)
354{
355 w5100_write(priv, W5100_S0_MR, priv->promisc ?
356 S0_MR_MACRAW : S0_MR_MACRAW_MF);
357 mmiowb();
358 w5100_command(priv, S0_CR_OPEN);
359 w5100_write(priv, W5100_IMR, IR_S0);
360 mmiowb();
361}
362
363static void w5100_hw_close(struct w5100_priv *priv)
364{
365 w5100_write(priv, W5100_IMR, 0);
366 mmiowb();
367 w5100_command(priv, S0_CR_CLOSE);
368}
369
370/***********************************************************************
371 *
372 * Device driver functions / callbacks
373 *
374 ***********************************************************************/
375
376static void w5100_get_drvinfo(struct net_device *ndev,
377 struct ethtool_drvinfo *info)
378{
379 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
380 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
381 strlcpy(info->bus_info, dev_name(ndev->dev.parent),
382 sizeof(info->bus_info));
383}
384
385static u32 w5100_get_link(struct net_device *ndev)
386{
387 struct w5100_priv *priv = netdev_priv(ndev);
388
389 if (gpio_is_valid(priv->link_gpio))
390 return !!gpio_get_value(priv->link_gpio);
391
392 return 1;
393}
394
395static u32 w5100_get_msglevel(struct net_device *ndev)
396{
397 struct w5100_priv *priv = netdev_priv(ndev);
398
399 return priv->msg_enable;
400}
401
402static void w5100_set_msglevel(struct net_device *ndev, u32 value)
403{
404 struct w5100_priv *priv = netdev_priv(ndev);
405
406 priv->msg_enable = value;
407}
408
409static int w5100_get_regs_len(struct net_device *ndev)
410{
411 return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN;
412}
413
414static void w5100_get_regs(struct net_device *ndev,
415 struct ethtool_regs *regs, void *_buf)
416{
417 struct w5100_priv *priv = netdev_priv(ndev);
418 u8 *buf = _buf;
419 u16 i;
420
421 regs->version = 1;
422 for (i = 0; i < W5100_COMMON_REGS_LEN; i++)
423 *buf++ = w5100_read(priv, W5100_COMMON_REGS + i);
424 for (i = 0; i < W5100_S0_REGS_LEN; i++)
425 *buf++ = w5100_read(priv, W5100_S0_REGS + i);
426}
427
428static void w5100_tx_timeout(struct net_device *ndev)
429{
430 struct w5100_priv *priv = netdev_priv(ndev);
431
432 netif_stop_queue(ndev);
433 w5100_hw_reset(priv);
434 w5100_hw_start(priv);
435 ndev->stats.tx_errors++;
436 ndev->trans_start = jiffies;
437 netif_wake_queue(ndev);
438}
439
440static int w5100_start_tx(struct sk_buff *skb, struct net_device *ndev)
441{
442 struct w5100_priv *priv = netdev_priv(ndev);
443 u16 offset;
444
445 netif_stop_queue(ndev);
446
447 offset = w5100_read16(priv, W5100_S0_TX_WR);
448 w5100_writebuf(priv, offset, skb->data, skb->len);
449 w5100_write16(priv, W5100_S0_TX_WR, offset + skb->len);
450 mmiowb();
451 ndev->stats.tx_bytes += skb->len;
452 ndev->stats.tx_packets++;
453 dev_kfree_skb(skb);
454
455 w5100_command(priv, S0_CR_SEND);
456
457 return NETDEV_TX_OK;
458}
459
460static int w5100_napi_poll(struct napi_struct *napi, int budget)
461{
462 struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi);
463 struct net_device *ndev = priv->ndev;
464 struct sk_buff *skb;
465 int rx_count;
466 u16 rx_len;
467 u16 offset;
468 u8 header[2];
469
470 for (rx_count = 0; rx_count < budget; rx_count++) {
471 u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR);
472 if (rx_buf_len == 0)
473 break;
474
475 offset = w5100_read16(priv, W5100_S0_RX_RD);
476 w5100_readbuf(priv, offset, header, 2);
477 rx_len = get_unaligned_be16(header) - 2;
478
479 skb = netdev_alloc_skb_ip_align(ndev, rx_len);
480 if (unlikely(!skb)) {
481 w5100_write16(priv, W5100_S0_RX_RD,
482 offset + rx_buf_len);
483 w5100_command(priv, S0_CR_RECV);
484 ndev->stats.rx_dropped++;
485 return -ENOMEM;
486 }
487
488 skb_put(skb, rx_len);
489 w5100_readbuf(priv, offset + 2, skb->data, rx_len);
490 w5100_write16(priv, W5100_S0_RX_RD, offset + 2 + rx_len);
491 mmiowb();
492 w5100_command(priv, S0_CR_RECV);
493 skb->protocol = eth_type_trans(skb, ndev);
494
495 netif_receive_skb(skb);
496 ndev->stats.rx_packets++;
497 ndev->stats.rx_bytes += rx_len;
498 }
499
500 if (rx_count < budget) {
501 w5100_write(priv, W5100_IMR, IR_S0);
502 mmiowb();
503 napi_complete(napi);
504 }
505
506 return rx_count;
507}
508
509static irqreturn_t w5100_interrupt(int irq, void *ndev_instance)
510{
511 struct net_device *ndev = ndev_instance;
512 struct w5100_priv *priv = netdev_priv(ndev);
513
514 int ir = w5100_read(priv, W5100_S0_IR);
515 if (!ir)
516 return IRQ_NONE;
517 w5100_write(priv, W5100_S0_IR, ir);
518 mmiowb();
519
520 if (ir & S0_IR_SENDOK) {
521 netif_dbg(priv, tx_done, ndev, "tx done\n");
522 netif_wake_queue(ndev);
523 }
524
525 if (ir & S0_IR_RECV) {
526 if (napi_schedule_prep(&priv->napi)) {
527 w5100_write(priv, W5100_IMR, 0);
528 mmiowb();
529 __napi_schedule(&priv->napi);
530 }
531 }
532
533 return IRQ_HANDLED;
534}
535
536static irqreturn_t w5100_detect_link(int irq, void *ndev_instance)
537{
538 struct net_device *ndev = ndev_instance;
539 struct w5100_priv *priv = netdev_priv(ndev);
540
541 if (netif_running(ndev)) {
542 if (gpio_get_value(priv->link_gpio) != 0) {
543 netif_info(priv, link, ndev, "link is up\n");
544 netif_carrier_on(ndev);
545 } else {
546 netif_info(priv, link, ndev, "link is down\n");
547 netif_carrier_off(ndev);
548 }
549 }
550
551 return IRQ_HANDLED;
552}
553
554static void w5100_set_rx_mode(struct net_device *ndev)
555{
556 struct w5100_priv *priv = netdev_priv(ndev);
557 bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
558
559 if (priv->promisc != set_promisc) {
560 priv->promisc = set_promisc;
561 w5100_hw_start(priv);
562 }
563}
564
565static int w5100_set_macaddr(struct net_device *ndev, void *addr)
566{
567 struct w5100_priv *priv = netdev_priv(ndev);
568 struct sockaddr *sock_addr = addr;
569
570 if (!is_valid_ether_addr(sock_addr->sa_data))
571 return -EADDRNOTAVAIL;
572 memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
573 ndev->addr_assign_type &= ~NET_ADDR_RANDOM;
574 w5100_write_macaddr(priv);
575 return 0;
576}
577
578static int w5100_open(struct net_device *ndev)
579{
580 struct w5100_priv *priv = netdev_priv(ndev);
581
582 netif_info(priv, ifup, ndev, "enabling\n");
583 if (!is_valid_ether_addr(ndev->dev_addr))
584 return -EINVAL;
585 w5100_hw_start(priv);
586 napi_enable(&priv->napi);
587 netif_start_queue(ndev);
588 if (!gpio_is_valid(priv->link_gpio) ||
589 gpio_get_value(priv->link_gpio) != 0)
590 netif_carrier_on(ndev);
591 return 0;
592}
593
594static int w5100_stop(struct net_device *ndev)
595{
596 struct w5100_priv *priv = netdev_priv(ndev);
597
598 netif_info(priv, ifdown, ndev, "shutting down\n");
599 w5100_hw_close(priv);
600 netif_carrier_off(ndev);
601 netif_stop_queue(ndev);
602 napi_disable(&priv->napi);
603 return 0;
604}
605
606static const struct ethtool_ops w5100_ethtool_ops = {
607 .get_drvinfo = w5100_get_drvinfo,
608 .get_msglevel = w5100_get_msglevel,
609 .set_msglevel = w5100_set_msglevel,
610 .get_link = w5100_get_link,
611 .get_regs_len = w5100_get_regs_len,
612 .get_regs = w5100_get_regs,
613};
614
615static const struct net_device_ops w5100_netdev_ops = {
616 .ndo_open = w5100_open,
617 .ndo_stop = w5100_stop,
618 .ndo_start_xmit = w5100_start_tx,
619 .ndo_tx_timeout = w5100_tx_timeout,
620 .ndo_set_rx_mode = w5100_set_rx_mode,
621 .ndo_set_mac_address = w5100_set_macaddr,
622 .ndo_validate_addr = eth_validate_addr,
623 .ndo_change_mtu = eth_change_mtu,
624};
625
626static int __devinit w5100_hw_probe(struct platform_device *pdev)
627{
628 struct wiznet_platform_data *data = pdev->dev.platform_data;
629 struct net_device *ndev = platform_get_drvdata(pdev);
630 struct w5100_priv *priv = netdev_priv(ndev);
631 const char *name = netdev_name(ndev);
632 struct resource *mem;
633 int mem_size;
634 int irq;
635 int ret;
636
637 if (data && is_valid_ether_addr(data->mac_addr)) {
638 memcpy(ndev->dev_addr, data->mac_addr, ETH_ALEN);
639 } else {
640 random_ether_addr(ndev->dev_addr);
641 ndev->addr_assign_type |= NET_ADDR_RANDOM;
642 }
643
644 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
645 if (!mem)
646 return -ENXIO;
647 mem_size = resource_size(mem);
648 if (!devm_request_mem_region(&pdev->dev, mem->start, mem_size, name))
649 return -EBUSY;
650 priv->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
651 if (!priv->base)
652 return -EBUSY;
653
654 spin_lock_init(&priv->reg_lock);
655 priv->indirect = mem_size < W5100_BUS_DIRECT_SIZE;
656 if (priv->indirect) {
657 priv->read = w5100_read_indirect;
658 priv->write = w5100_write_indirect;
659 priv->read16 = w5100_read16_indirect;
660 priv->write16 = w5100_write16_indirect;
661 priv->readbuf = w5100_readbuf_indirect;
662 priv->writebuf = w5100_writebuf_indirect;
663 } else {
664 priv->read = w5100_read_direct;
665 priv->write = w5100_write_direct;
666 priv->read16 = w5100_read16_direct;
667 priv->write16 = w5100_write16_direct;
668 priv->readbuf = w5100_readbuf_direct;
669 priv->writebuf = w5100_writebuf_direct;
670 }
671
672 w5100_hw_reset(priv);
673 if (w5100_read16(priv, W5100_RTR) != RTR_DEFAULT)
674 return -ENODEV;
675
676 irq = platform_get_irq(pdev, 0);
677 if (irq < 0)
678 return irq;
679 ret = request_irq(irq, w5100_interrupt,
680 IRQ_TYPE_LEVEL_LOW, name, ndev);
681 if (ret < 0)
682 return ret;
683 priv->irq = irq;
684
685 priv->link_gpio = data ? data->link_gpio : -EINVAL;
686 if (gpio_is_valid(priv->link_gpio)) {
687 char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
688 if (!link_name)
689 return -ENOMEM;
690 snprintf(link_name, 16, "%s-link", name);
691 priv->link_irq = gpio_to_irq(priv->link_gpio);
692 if (request_any_context_irq(priv->link_irq, w5100_detect_link,
693 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
694 link_name, priv->ndev) < 0)
695 priv->link_gpio = -EINVAL;
696 }
697
698 netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq);
699 return 0;
700}
701
702static int __devinit w5100_probe(struct platform_device *pdev)
703{
704 struct w5100_priv *priv;
705 struct net_device *ndev;
706 int err;
707
708 ndev = alloc_etherdev(sizeof(*priv));
709 if (!ndev)
710 return -ENOMEM;
711 SET_NETDEV_DEV(ndev, &pdev->dev);
712 platform_set_drvdata(pdev, ndev);
713 priv = netdev_priv(ndev);
714 priv->ndev = ndev;
715
716 ether_setup(ndev);
717 ndev->netdev_ops = &w5100_netdev_ops;
718 ndev->ethtool_ops = &w5100_ethtool_ops;
719 ndev->watchdog_timeo = HZ;
720 netif_napi_add(ndev, &priv->napi, w5100_napi_poll, 16);
721
722 /* This chip doesn't support VLAN packets with normal MTU,
723 * so disable VLAN for this device.
724 */
725 ndev->features |= NETIF_F_VLAN_CHALLENGED;
726
727 err = register_netdev(ndev);
728 if (err < 0)
729 goto err_register;
730
731 err = w5100_hw_probe(pdev);
732 if (err < 0)
733 goto err_hw_probe;
734
735 return 0;
736
737err_hw_probe:
738 unregister_netdev(ndev);
739err_register:
740 free_netdev(ndev);
741 platform_set_drvdata(pdev, NULL);
742 return err;
743}
744
745static int __devexit w5100_remove(struct platform_device *pdev)
746{
747 struct net_device *ndev = platform_get_drvdata(pdev);
748 struct w5100_priv *priv = netdev_priv(ndev);
749
750 w5100_hw_reset(priv);
751 free_irq(priv->irq, ndev);
752 if (gpio_is_valid(priv->link_gpio))
753 free_irq(priv->link_irq, ndev);
754
755 unregister_netdev(ndev);
756 free_netdev(ndev);
757 platform_set_drvdata(pdev, NULL);
758 return 0;
759}
760
761#ifdef CONFIG_PM
762static int w5100_suspend(struct device *dev)
763{
764 struct platform_device *pdev = to_platform_device(dev);
765 struct net_device *ndev = platform_get_drvdata(pdev);
766 struct w5100_priv *priv = netdev_priv(ndev);
767
768 if (netif_running(ndev)) {
769 netif_carrier_off(ndev);
770 netif_device_detach(ndev);
771
772 w5100_hw_close(priv);
773 }
774 return 0;
775}
776
777static int w5100_resume(struct device *dev)
778{
779 struct platform_device *pdev = to_platform_device(dev);
780 struct net_device *ndev = platform_get_drvdata(pdev);
781 struct w5100_priv *priv = netdev_priv(ndev);
782
783 if (netif_running(ndev)) {
784 w5100_hw_reset(priv);
785 w5100_hw_start(priv);
786
787 netif_device_attach(ndev);
788 if (!gpio_is_valid(priv->link_gpio) ||
789 gpio_get_value(priv->link_gpio) != 0)
790 netif_carrier_on(ndev);
791 }
792 return 0;
793}
794#endif /* CONFIG_PM */
795
796static SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume);
797
798static struct platform_driver w5100_driver = {
799 .driver = {
800 .name = DRV_NAME,
801 .owner = THIS_MODULE,
802 .pm = &w5100_pm_ops,
803 },
804 .probe = w5100_probe,
805 .remove = __devexit_p(w5100_remove),
806};
807
808module_platform_driver(w5100_driver);