1// SPDX-License-Identifier: GPL-2.0
  2/*******************************************************************************
  3 *
  4 * Intel Ethernet Controller XL710 Family Linux Driver
  5 * Copyright(c) 2013 - 2014 Intel Corporation.
  6 *
  7 * This program is free software; you can redistribute it and/or modify it
  8 * under the terms and conditions of the GNU General Public License,
  9 * version 2, as published by the Free Software Foundation.
 10 *
 11 * This program is distributed in the hope it will be useful, but WITHOUT
 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14 * more details.
 15 *
 16 * You should have received a copy of the GNU General Public License along
 17 * with this program.  If not, see <http://www.gnu.org/licenses/>.
 18 *
 19 * The full GNU General Public License is included in this distribution in
 20 * the file called "COPYING".
 21 *
 22 * Contact Information:
 23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 25 *
 26 ******************************************************************************/
 27
 28#include "i40e_diag.h"
 29#include "i40e_prototype.h"
 30
 31/**
 32 * i40e_diag_reg_pattern_test
 33 * @hw: pointer to the hw struct
 34 * @reg: reg to be tested
 35 * @mask: bits to be touched
 36 **/
 37static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
 38							u32 reg, u32 mask)
 39{
 40	static const u32 patterns[] = {
 41		0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
 42	};
 43	u32 pat, val, orig_val;
 44	int i;
 45
 46	orig_val = rd32(hw, reg);
 47	for (i = 0; i < ARRAY_SIZE(patterns); i++) {
 48		pat = patterns[i];
 49		wr32(hw, reg, (pat & mask));
 50		val = rd32(hw, reg);
 51		if ((val & mask) != (pat & mask)) {
 52			i40e_debug(hw, I40E_DEBUG_DIAG,
 53				   "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
 54				   __func__, reg, pat, val);
 55			return I40E_ERR_DIAG_TEST_FAILED;
 56		}
 57	}
 58
 59	wr32(hw, reg, orig_val);
 60	val = rd32(hw, reg);
 61	if (val != orig_val) {
 62		i40e_debug(hw, I40E_DEBUG_DIAG,
 63			   "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n",
 64			   __func__, reg, orig_val, val);
 65		return I40E_ERR_DIAG_TEST_FAILED;
 66	}
 67
 68	return 0;
 69}
 70
 71struct i40e_diag_reg_test_info i40e_reg_list[] = {
 72	/* offset               mask         elements   stride */
 73	{I40E_QTX_CTL(0),       0x0000FFBF, 1,
 74		I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
 75	{I40E_PFINT_ITR0(0),    0x00000FFF, 3,
 76		I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
 77	{I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1,
 78		I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
 79	{I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1,
 80		I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
 81	{I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1,
 82		I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
 83	{I40E_PFINT_STAT_CTL0,  0x0000000C, 1, 0},
 84	{I40E_PFINT_LNKLST0,    0x00001FFF, 1, 0},
 85	{I40E_PFINT_LNKLSTN(0), 0x000007FF, 1,
 86		I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
 87	{I40E_QINT_TQCTL(0),    0x000000FF, 1,
 88		I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
 89	{I40E_QINT_RQCTL(0),    0x000000FF, 1,
 90		I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
 91	{I40E_PFINT_ICR0_ENA,   0xF7F20000, 1, 0},
 92	{ 0 }
 93};
 94
 95/**
 96 * i40e_diag_reg_test
 97 * @hw: pointer to the hw struct
 98 *
 99 * Perform registers diagnostic test
100 **/
101i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
102{
103	i40e_status ret_code = 0;
104	u32 reg, mask;
105	u32 i, j;
106
107	for (i = 0; i40e_reg_list[i].offset != 0 &&
108					     !ret_code; i++) {
109
110		/* set actual reg range for dynamically allocated resources */
111		if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
112		    hw->func_caps.num_tx_qp != 0)
113			i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
114		if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
115		     i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
116		     i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
117		     i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
118		     i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
119		    hw->func_caps.num_msix_vectors != 0)
120			i40e_reg_list[i].elements =
121				hw->func_caps.num_msix_vectors - 1;
122
123		/* test register access */
124		mask = i40e_reg_list[i].mask;
125		for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) {
126			reg = i40e_reg_list[i].offset +
127			      (j * i40e_reg_list[i].stride);
128			ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
129		}
130	}
131
132	return ret_code;
133}
134
135/**
136 * i40e_diag_eeprom_test
137 * @hw: pointer to the hw struct
138 *
139 * Perform EEPROM diagnostic test
140 **/
141i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)
142{
143	i40e_status ret_code;
144	u16 reg_val;
145
146	/* read NVM control word and if NVM valid, validate EEPROM checksum*/
147	ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);
148	if (!ret_code &&
149	    ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
150	     BIT(I40E_SR_CONTROL_WORD_1_SHIFT)))
151		return i40e_validate_nvm_checksum(hw, NULL);
152	else
153		return I40E_ERR_DIAG_TEST_FAILED;
154}