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1/*
2 * linux/arch/arm/mach-omap1/pm.c
3 *
4 * OMAP Power Management Routines
5 *
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
14 *
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/suspend.h>
39#include <linux/sched.h>
40#include <linux/debugfs.h>
41#include <linux/seq_file.h>
42#include <linux/interrupt.h>
43#include <linux/sysfs.h>
44#include <linux/module.h>
45#include <linux/io.h>
46#include <linux/atomic.h>
47#include <linux/cpu.h>
48
49#include <asm/fncpy.h>
50#include <asm/system_misc.h>
51#include <asm/irq.h>
52#include <asm/mach/time.h>
53#include <asm/mach/irq.h>
54
55#include <mach/tc.h>
56#include <mach/mux.h>
57#include <linux/omap-dma.h>
58#include <clocksource/timer-ti-dm.h>
59
60#include <mach/irqs.h>
61
62#include "iomap.h"
63#include "clock.h"
64#include "pm.h"
65#include "soc.h"
66#include "sram.h"
67
68static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
69static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
70static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
71static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
72static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
73static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
74
75static unsigned short enable_dyn_sleep;
76
77static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
78 char *buf)
79{
80 return sprintf(buf, "%hu\n", enable_dyn_sleep);
81}
82
83static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
84 const char * buf, size_t n)
85{
86 unsigned short value;
87 if (sscanf(buf, "%hu", &value) != 1 ||
88 (value != 0 && value != 1) ||
89 (value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) {
90 pr_err("idle_sleep_store: Invalid value\n");
91 return -EINVAL;
92 }
93 enable_dyn_sleep = value;
94 return n;
95}
96
97static struct kobj_attribute sleep_while_idle_attr =
98 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
99
100
101static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
102
103/*
104 * Let's power down on idle, but only if we are really
105 * idle, because once we start down the path of
106 * going idle we continue to do idle even if we get
107 * a clock tick interrupt . .
108 */
109void omap1_pm_idle(void)
110{
111 extern __u32 arm_idlect1_mask;
112 __u32 use_idlect1 = arm_idlect1_mask;
113
114 local_fiq_disable();
115
116#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
117 use_idlect1 = use_idlect1 & ~(1 << 9);
118#endif
119
120#ifdef CONFIG_OMAP_DM_TIMER
121 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
122#endif
123
124 if (omap_dma_running())
125 use_idlect1 &= ~(1 << 6);
126
127 /*
128 * We should be able to remove the do_sleep variable and multiple
129 * tests above as soon as drivers, timer and DMA code have been fixed.
130 * Even the sleep block count should become obsolete.
131 */
132 if ((use_idlect1 != ~0) || !enable_dyn_sleep) {
133
134 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
135 if (cpu_is_omap15xx())
136 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
137 else
138 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
139 omap_writel(use_idlect1, ARM_IDLECT1);
140 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
141 omap_writel(saved_idlect1, ARM_IDLECT1);
142
143 local_fiq_enable();
144 return;
145 }
146 omap_sram_suspend(omap_readl(ARM_IDLECT1),
147 omap_readl(ARM_IDLECT2));
148
149 local_fiq_enable();
150}
151
152/*
153 * Configuration of the wakeup event is board specific. For the
154 * moment we put it into this helper function. Later it may move
155 * to board specific files.
156 */
157static void omap_pm_wakeup_setup(void)
158{
159 u32 level1_wake = 0;
160 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
161
162 /*
163 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
164 * and the L2 wakeup interrupts: keypad and UART2. Note that the
165 * drivers must still separately call omap_set_gpio_wakeup() to
166 * wake up to a GPIO interrupt.
167 */
168 if (cpu_is_omap7xx())
169 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
170 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
171 else if (cpu_is_omap15xx())
172 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
173 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
174 else if (cpu_is_omap16xx())
175 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
176 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
177
178 omap_writel(~level1_wake, OMAP_IH1_MIR);
179
180 if (cpu_is_omap7xx()) {
181 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
182 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
183 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
184 OMAP_IH2_1_MIR);
185 } else if (cpu_is_omap15xx()) {
186 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
187 omap_writel(~level2_wake, OMAP_IH2_MIR);
188 } else if (cpu_is_omap16xx()) {
189 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
190 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
191
192 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
193 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
194 OMAP_IH2_1_MIR);
195 omap_writel(~0x0, OMAP_IH2_2_MIR);
196 omap_writel(~0x0, OMAP_IH2_3_MIR);
197 }
198
199 /* New IRQ agreement, recalculate in cascade order */
200 omap_writel(1, OMAP_IH2_CONTROL);
201 omap_writel(1, OMAP_IH1_CONTROL);
202}
203
204#define EN_DSPCK 13 /* ARM_CKCTL */
205#define EN_APICK 6 /* ARM_IDLECT2 */
206#define DSP_EN 1 /* ARM_RSTCT1 */
207
208void omap1_pm_suspend(void)
209{
210 unsigned long arg0 = 0, arg1 = 0;
211
212 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
213 omap_rev());
214
215 omap_serial_wake_trigger(1);
216
217 if (!cpu_is_omap15xx())
218 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
219
220 /*
221 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
222 */
223
224 local_irq_disable();
225 local_fiq_disable();
226
227 /*
228 * Step 2: save registers
229 *
230 * The omap is a strange/beautiful device. The caches, memory
231 * and register state are preserved across power saves.
232 * We have to save and restore very little register state to
233 * idle the omap.
234 *
235 * Save interrupt, MPUI, ARM and UPLD control registers.
236 */
237
238 if (cpu_is_omap7xx()) {
239 MPUI7XX_SAVE(OMAP_IH1_MIR);
240 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
241 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
242 MPUI7XX_SAVE(MPUI_CTRL);
243 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
244 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
245 MPUI7XX_SAVE(EMIFS_CONFIG);
246 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
247
248 } else if (cpu_is_omap15xx()) {
249 MPUI1510_SAVE(OMAP_IH1_MIR);
250 MPUI1510_SAVE(OMAP_IH2_MIR);
251 MPUI1510_SAVE(MPUI_CTRL);
252 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
253 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
254 MPUI1510_SAVE(EMIFS_CONFIG);
255 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
256 } else if (cpu_is_omap16xx()) {
257 MPUI1610_SAVE(OMAP_IH1_MIR);
258 MPUI1610_SAVE(OMAP_IH2_0_MIR);
259 MPUI1610_SAVE(OMAP_IH2_1_MIR);
260 MPUI1610_SAVE(OMAP_IH2_2_MIR);
261 MPUI1610_SAVE(OMAP_IH2_3_MIR);
262 MPUI1610_SAVE(MPUI_CTRL);
263 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
264 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
265 MPUI1610_SAVE(EMIFS_CONFIG);
266 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
267 }
268
269 ARM_SAVE(ARM_CKCTL);
270 ARM_SAVE(ARM_IDLECT1);
271 ARM_SAVE(ARM_IDLECT2);
272 if (!(cpu_is_omap15xx()))
273 ARM_SAVE(ARM_IDLECT3);
274 ARM_SAVE(ARM_EWUPCT);
275 ARM_SAVE(ARM_RSTCT1);
276 ARM_SAVE(ARM_RSTCT2);
277 ARM_SAVE(ARM_SYSST);
278 ULPD_SAVE(ULPD_CLOCK_CTRL);
279 ULPD_SAVE(ULPD_STATUS_REQ);
280
281 /* (Step 3 removed - we now allow deep sleep by default) */
282
283 /*
284 * Step 4: OMAP DSP Shutdown
285 */
286
287 /* stop DSP */
288 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
289
290 /* shut down dsp_ck */
291 if (!cpu_is_omap7xx())
292 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
293
294 /* temporarily enabling api_ck to access DSP registers */
295 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
296
297 /* save DSP registers */
298 DSP_SAVE(DSP_IDLECT2);
299
300 /* Stop all DSP domain clocks */
301 __raw_writew(0, DSP_IDLECT2);
302
303 /*
304 * Step 5: Wakeup Event Setup
305 */
306
307 omap_pm_wakeup_setup();
308
309 /*
310 * Step 6: ARM and Traffic controller shutdown
311 */
312
313 /* disable ARM watchdog */
314 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
315 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
316
317 /*
318 * Step 6b: ARM and Traffic controller shutdown
319 *
320 * Step 6 continues here. Prepare jump to power management
321 * assembly code in internal SRAM.
322 *
323 * Since the omap_cpu_suspend routine has been copied to
324 * SRAM, we'll do an indirect procedure call to it and pass the
325 * contents of arm_idlect1 and arm_idlect2 so it can restore
326 * them when it wakes up and it will return.
327 */
328
329 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
330 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
331
332 /*
333 * Step 6c: ARM and Traffic controller shutdown
334 *
335 * Jump to assembly code. The processor will stay there
336 * until wake up.
337 */
338 omap_sram_suspend(arg0, arg1);
339
340 /*
341 * If we are here, processor is woken up!
342 */
343
344 /*
345 * Restore DSP clocks
346 */
347
348 /* again temporarily enabling api_ck to access DSP registers */
349 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
350
351 /* Restore DSP domain clocks */
352 DSP_RESTORE(DSP_IDLECT2);
353
354 /*
355 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
356 */
357
358 if (!(cpu_is_omap15xx()))
359 ARM_RESTORE(ARM_IDLECT3);
360 ARM_RESTORE(ARM_CKCTL);
361 ARM_RESTORE(ARM_EWUPCT);
362 ARM_RESTORE(ARM_RSTCT1);
363 ARM_RESTORE(ARM_RSTCT2);
364 ARM_RESTORE(ARM_SYSST);
365 ULPD_RESTORE(ULPD_CLOCK_CTRL);
366 ULPD_RESTORE(ULPD_STATUS_REQ);
367
368 if (cpu_is_omap7xx()) {
369 MPUI7XX_RESTORE(EMIFS_CONFIG);
370 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
371 MPUI7XX_RESTORE(OMAP_IH1_MIR);
372 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
373 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
374 } else if (cpu_is_omap15xx()) {
375 MPUI1510_RESTORE(MPUI_CTRL);
376 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
377 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
378 MPUI1510_RESTORE(EMIFS_CONFIG);
379 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
380 MPUI1510_RESTORE(OMAP_IH1_MIR);
381 MPUI1510_RESTORE(OMAP_IH2_MIR);
382 } else if (cpu_is_omap16xx()) {
383 MPUI1610_RESTORE(MPUI_CTRL);
384 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
385 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
386 MPUI1610_RESTORE(EMIFS_CONFIG);
387 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
388
389 MPUI1610_RESTORE(OMAP_IH1_MIR);
390 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
391 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
392 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
393 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
394 }
395
396 if (!cpu_is_omap15xx())
397 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
398
399 /*
400 * Re-enable interrupts
401 */
402
403 local_irq_enable();
404 local_fiq_enable();
405
406 omap_serial_wake_trigger(0);
407
408 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
409 omap_rev());
410}
411
412#ifdef CONFIG_DEBUG_FS
413/*
414 * Read system PM registers for debugging
415 */
416static int omap_pm_debug_show(struct seq_file *m, void *v)
417{
418 ARM_SAVE(ARM_CKCTL);
419 ARM_SAVE(ARM_IDLECT1);
420 ARM_SAVE(ARM_IDLECT2);
421 if (!(cpu_is_omap15xx()))
422 ARM_SAVE(ARM_IDLECT3);
423 ARM_SAVE(ARM_EWUPCT);
424 ARM_SAVE(ARM_RSTCT1);
425 ARM_SAVE(ARM_RSTCT2);
426 ARM_SAVE(ARM_SYSST);
427
428 ULPD_SAVE(ULPD_IT_STATUS);
429 ULPD_SAVE(ULPD_CLOCK_CTRL);
430 ULPD_SAVE(ULPD_SOFT_REQ);
431 ULPD_SAVE(ULPD_STATUS_REQ);
432 ULPD_SAVE(ULPD_DPLL_CTRL);
433 ULPD_SAVE(ULPD_POWER_CTRL);
434
435 if (cpu_is_omap7xx()) {
436 MPUI7XX_SAVE(MPUI_CTRL);
437 MPUI7XX_SAVE(MPUI_DSP_STATUS);
438 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
439 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
440 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
441 MPUI7XX_SAVE(EMIFS_CONFIG);
442 } else if (cpu_is_omap15xx()) {
443 MPUI1510_SAVE(MPUI_CTRL);
444 MPUI1510_SAVE(MPUI_DSP_STATUS);
445 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
446 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
447 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
448 MPUI1510_SAVE(EMIFS_CONFIG);
449 } else if (cpu_is_omap16xx()) {
450 MPUI1610_SAVE(MPUI_CTRL);
451 MPUI1610_SAVE(MPUI_DSP_STATUS);
452 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
453 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
454 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
455 MPUI1610_SAVE(EMIFS_CONFIG);
456 }
457
458 seq_printf(m,
459 "ARM_CKCTL_REG: 0x%-8x \n"
460 "ARM_IDLECT1_REG: 0x%-8x \n"
461 "ARM_IDLECT2_REG: 0x%-8x \n"
462 "ARM_IDLECT3_REG: 0x%-8x \n"
463 "ARM_EWUPCT_REG: 0x%-8x \n"
464 "ARM_RSTCT1_REG: 0x%-8x \n"
465 "ARM_RSTCT2_REG: 0x%-8x \n"
466 "ARM_SYSST_REG: 0x%-8x \n"
467 "ULPD_IT_STATUS_REG: 0x%-4x \n"
468 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
469 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
470 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
471 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
472 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
473 ARM_SHOW(ARM_CKCTL),
474 ARM_SHOW(ARM_IDLECT1),
475 ARM_SHOW(ARM_IDLECT2),
476 ARM_SHOW(ARM_IDLECT3),
477 ARM_SHOW(ARM_EWUPCT),
478 ARM_SHOW(ARM_RSTCT1),
479 ARM_SHOW(ARM_RSTCT2),
480 ARM_SHOW(ARM_SYSST),
481 ULPD_SHOW(ULPD_IT_STATUS),
482 ULPD_SHOW(ULPD_CLOCK_CTRL),
483 ULPD_SHOW(ULPD_SOFT_REQ),
484 ULPD_SHOW(ULPD_DPLL_CTRL),
485 ULPD_SHOW(ULPD_STATUS_REQ),
486 ULPD_SHOW(ULPD_POWER_CTRL));
487
488 if (cpu_is_omap7xx()) {
489 seq_printf(m,
490 "MPUI7XX_CTRL_REG 0x%-8x \n"
491 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
492 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
493 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
494 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
495 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
496 MPUI7XX_SHOW(MPUI_CTRL),
497 MPUI7XX_SHOW(MPUI_DSP_STATUS),
498 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
499 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
500 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
501 MPUI7XX_SHOW(EMIFS_CONFIG));
502 } else if (cpu_is_omap15xx()) {
503 seq_printf(m,
504 "MPUI1510_CTRL_REG 0x%-8x \n"
505 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
506 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
507 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
508 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
509 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
510 MPUI1510_SHOW(MPUI_CTRL),
511 MPUI1510_SHOW(MPUI_DSP_STATUS),
512 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
513 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
514 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
515 MPUI1510_SHOW(EMIFS_CONFIG));
516 } else if (cpu_is_omap16xx()) {
517 seq_printf(m,
518 "MPUI1610_CTRL_REG 0x%-8x \n"
519 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
520 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
521 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
522 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
523 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
524 MPUI1610_SHOW(MPUI_CTRL),
525 MPUI1610_SHOW(MPUI_DSP_STATUS),
526 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
527 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
528 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
529 MPUI1610_SHOW(EMIFS_CONFIG));
530 }
531
532 return 0;
533}
534
535static int omap_pm_debug_open(struct inode *inode, struct file *file)
536{
537 return single_open(file, omap_pm_debug_show,
538 &inode->i_private);
539}
540
541static const struct file_operations omap_pm_debug_fops = {
542 .open = omap_pm_debug_open,
543 .read = seq_read,
544 .llseek = seq_lseek,
545 .release = single_release,
546};
547
548static void omap_pm_init_debugfs(void)
549{
550 struct dentry *d;
551
552 d = debugfs_create_dir("pm_debug", NULL);
553 if (!d)
554 return;
555
556 (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
557 d, NULL, &omap_pm_debug_fops);
558}
559
560#endif /* CONFIG_DEBUG_FS */
561
562/*
563 * omap_pm_prepare - Do preliminary suspend work.
564 *
565 */
566static int omap_pm_prepare(void)
567{
568 /* We cannot sleep in idle until we have resumed */
569 cpu_idle_poll_ctrl(true);
570 return 0;
571}
572
573
574/*
575 * omap_pm_enter - Actually enter a sleep state.
576 * @state: State we're entering.
577 *
578 */
579
580static int omap_pm_enter(suspend_state_t state)
581{
582 switch (state)
583 {
584 case PM_SUSPEND_MEM:
585 omap1_pm_suspend();
586 break;
587 default:
588 return -EINVAL;
589 }
590
591 return 0;
592}
593
594
595/**
596 * omap_pm_finish - Finish up suspend sequence.
597 *
598 * This is called after we wake back up (or if entering the sleep state
599 * failed).
600 */
601
602static void omap_pm_finish(void)
603{
604 cpu_idle_poll_ctrl(false);
605}
606
607
608static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
609{
610 return IRQ_HANDLED;
611}
612
613static struct irqaction omap_wakeup_irq = {
614 .name = "peripheral wakeup",
615 .handler = omap_wakeup_interrupt
616};
617
618
619
620static const struct platform_suspend_ops omap_pm_ops = {
621 .prepare = omap_pm_prepare,
622 .enter = omap_pm_enter,
623 .finish = omap_pm_finish,
624 .valid = suspend_valid_only_mem,
625};
626
627static int __init omap_pm_init(void)
628{
629 int error = 0;
630
631 if (!cpu_class_is_omap1())
632 return -ENODEV;
633
634 pr_info("Power Management for TI OMAP.\n");
635
636 if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER))
637 pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n");
638
639 if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER))
640 pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n");
641
642 if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) &&
643 IS_ENABLED(CONFIG_OMAP_DM_TIMER)) {
644 /* OMAP16xx only */
645 pr_info("OMAP1 PM: sleep states in idle enabled\n");
646 enable_dyn_sleep = 1;
647 }
648
649 /*
650 * We copy the assembler sleep/wakeup routines to SRAM.
651 * These routines need to be in SRAM as that's the only
652 * memory the MPU can see when it wakes up.
653 */
654 if (cpu_is_omap7xx()) {
655 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
656 omap7xx_cpu_suspend_sz);
657 } else if (cpu_is_omap15xx()) {
658 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
659 omap1510_cpu_suspend_sz);
660 } else if (cpu_is_omap16xx()) {
661 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
662 omap1610_cpu_suspend_sz);
663 }
664
665 if (omap_sram_suspend == NULL) {
666 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
667 return -ENODEV;
668 }
669
670 arm_pm_idle = omap1_pm_idle;
671
672 if (cpu_is_omap7xx())
673 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
674 else if (cpu_is_omap16xx())
675 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
676
677 /* Program new power ramp-up time
678 * (0 for most boards since we don't lower voltage when in deep sleep)
679 */
680 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
681
682 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
683 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
684
685 /* Configure IDLECT3 */
686 if (cpu_is_omap7xx())
687 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
688 else if (cpu_is_omap16xx())
689 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
690
691 suspend_set_ops(&omap_pm_ops);
692
693#ifdef CONFIG_DEBUG_FS
694 omap_pm_init_debugfs();
695#endif
696
697 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
698 if (error)
699 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
700
701 if (cpu_is_omap16xx()) {
702 /* configure LOW_PWR pin */
703 omap_cfg_reg(T20_1610_LOW_PWR);
704 }
705
706 return error;
707}
708__initcall(omap_pm_init);
1/*
2 * linux/arch/arm/mach-omap1/pm.c
3 *
4 * OMAP Power Management Routines
5 *
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
14 *
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/suspend.h>
39#include <linux/sched.h>
40#include <linux/proc_fs.h>
41#include <linux/interrupt.h>
42#include <linux/sysfs.h>
43#include <linux/module.h>
44#include <linux/io.h>
45#include <linux/atomic.h>
46
47#include <asm/system_misc.h>
48#include <asm/irq.h>
49#include <asm/mach/time.h>
50#include <asm/mach/irq.h>
51
52#include <plat/cpu.h>
53#include <plat/clock.h>
54#include <plat/sram.h>
55#include <plat/tc.h>
56#include <plat/mux.h>
57#include <plat/dma.h>
58#include <plat/dmtimer.h>
59
60#include <mach/irqs.h>
61
62#include "iomap.h"
63#include "pm.h"
64
65static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
66static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
67static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
68static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
69static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
70static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
71
72#ifdef CONFIG_OMAP_32K_TIMER
73
74static unsigned short enable_dyn_sleep = 1;
75
76static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
77 char *buf)
78{
79 return sprintf(buf, "%hu\n", enable_dyn_sleep);
80}
81
82static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
83 const char * buf, size_t n)
84{
85 unsigned short value;
86 if (sscanf(buf, "%hu", &value) != 1 ||
87 (value != 0 && value != 1)) {
88 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
89 return -EINVAL;
90 }
91 enable_dyn_sleep = value;
92 return n;
93}
94
95static struct kobj_attribute sleep_while_idle_attr =
96 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
97
98#endif
99
100static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
101
102/*
103 * Let's power down on idle, but only if we are really
104 * idle, because once we start down the path of
105 * going idle we continue to do idle even if we get
106 * a clock tick interrupt . .
107 */
108void omap1_pm_idle(void)
109{
110 extern __u32 arm_idlect1_mask;
111 __u32 use_idlect1 = arm_idlect1_mask;
112 int do_sleep = 0;
113
114 local_fiq_disable();
115
116#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
117#warning Enable 32kHz OS timer in order to allow sleep states in idle
118 use_idlect1 = use_idlect1 & ~(1 << 9);
119#else
120
121 while (enable_dyn_sleep) {
122
123#ifdef CONFIG_CBUS_TAHVO_USB
124 extern int vbus_active;
125 /* Clock requirements? */
126 if (vbus_active)
127 break;
128#endif
129 do_sleep = 1;
130 break;
131 }
132
133#endif
134
135#ifdef CONFIG_OMAP_DM_TIMER
136 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
137#endif
138
139 if (omap_dma_running())
140 use_idlect1 &= ~(1 << 6);
141
142 /* We should be able to remove the do_sleep variable and multiple
143 * tests above as soon as drivers, timer and DMA code have been fixed.
144 * Even the sleep block count should become obsolete. */
145 if ((use_idlect1 != ~0) || !do_sleep) {
146
147 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
148 if (cpu_is_omap15xx())
149 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
150 else
151 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
152 omap_writel(use_idlect1, ARM_IDLECT1);
153 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
154 omap_writel(saved_idlect1, ARM_IDLECT1);
155
156 local_fiq_enable();
157 return;
158 }
159 omap_sram_suspend(omap_readl(ARM_IDLECT1),
160 omap_readl(ARM_IDLECT2));
161
162 local_fiq_enable();
163}
164
165/*
166 * Configuration of the wakeup event is board specific. For the
167 * moment we put it into this helper function. Later it may move
168 * to board specific files.
169 */
170static void omap_pm_wakeup_setup(void)
171{
172 u32 level1_wake = 0;
173 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
174
175 /*
176 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
177 * and the L2 wakeup interrupts: keypad and UART2. Note that the
178 * drivers must still separately call omap_set_gpio_wakeup() to
179 * wake up to a GPIO interrupt.
180 */
181 if (cpu_is_omap7xx())
182 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
183 OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
184 else if (cpu_is_omap15xx())
185 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
186 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
187 else if (cpu_is_omap16xx())
188 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
189 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
190
191 omap_writel(~level1_wake, OMAP_IH1_MIR);
192
193 if (cpu_is_omap7xx()) {
194 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
195 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
196 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
197 OMAP_IH2_1_MIR);
198 } else if (cpu_is_omap15xx()) {
199 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
200 omap_writel(~level2_wake, OMAP_IH2_MIR);
201 } else if (cpu_is_omap16xx()) {
202 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
203 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
204
205 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
206 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
207 OMAP_IH2_1_MIR);
208 omap_writel(~0x0, OMAP_IH2_2_MIR);
209 omap_writel(~0x0, OMAP_IH2_3_MIR);
210 }
211
212 /* New IRQ agreement, recalculate in cascade order */
213 omap_writel(1, OMAP_IH2_CONTROL);
214 omap_writel(1, OMAP_IH1_CONTROL);
215}
216
217#define EN_DSPCK 13 /* ARM_CKCTL */
218#define EN_APICK 6 /* ARM_IDLECT2 */
219#define DSP_EN 1 /* ARM_RSTCT1 */
220
221void omap1_pm_suspend(void)
222{
223 unsigned long arg0 = 0, arg1 = 0;
224
225 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
226 omap_rev());
227
228 omap_serial_wake_trigger(1);
229
230 if (!cpu_is_omap15xx())
231 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
232
233 /*
234 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
235 */
236
237 local_irq_disable();
238 local_fiq_disable();
239
240 /*
241 * Step 2: save registers
242 *
243 * The omap is a strange/beautiful device. The caches, memory
244 * and register state are preserved across power saves.
245 * We have to save and restore very little register state to
246 * idle the omap.
247 *
248 * Save interrupt, MPUI, ARM and UPLD control registers.
249 */
250
251 if (cpu_is_omap7xx()) {
252 MPUI7XX_SAVE(OMAP_IH1_MIR);
253 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
254 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
255 MPUI7XX_SAVE(MPUI_CTRL);
256 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
257 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
258 MPUI7XX_SAVE(EMIFS_CONFIG);
259 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
260
261 } else if (cpu_is_omap15xx()) {
262 MPUI1510_SAVE(OMAP_IH1_MIR);
263 MPUI1510_SAVE(OMAP_IH2_MIR);
264 MPUI1510_SAVE(MPUI_CTRL);
265 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
266 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
267 MPUI1510_SAVE(EMIFS_CONFIG);
268 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
269 } else if (cpu_is_omap16xx()) {
270 MPUI1610_SAVE(OMAP_IH1_MIR);
271 MPUI1610_SAVE(OMAP_IH2_0_MIR);
272 MPUI1610_SAVE(OMAP_IH2_1_MIR);
273 MPUI1610_SAVE(OMAP_IH2_2_MIR);
274 MPUI1610_SAVE(OMAP_IH2_3_MIR);
275 MPUI1610_SAVE(MPUI_CTRL);
276 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
277 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
278 MPUI1610_SAVE(EMIFS_CONFIG);
279 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
280 }
281
282 ARM_SAVE(ARM_CKCTL);
283 ARM_SAVE(ARM_IDLECT1);
284 ARM_SAVE(ARM_IDLECT2);
285 if (!(cpu_is_omap15xx()))
286 ARM_SAVE(ARM_IDLECT3);
287 ARM_SAVE(ARM_EWUPCT);
288 ARM_SAVE(ARM_RSTCT1);
289 ARM_SAVE(ARM_RSTCT2);
290 ARM_SAVE(ARM_SYSST);
291 ULPD_SAVE(ULPD_CLOCK_CTRL);
292 ULPD_SAVE(ULPD_STATUS_REQ);
293
294 /* (Step 3 removed - we now allow deep sleep by default) */
295
296 /*
297 * Step 4: OMAP DSP Shutdown
298 */
299
300 /* stop DSP */
301 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
302
303 /* shut down dsp_ck */
304 if (!cpu_is_omap7xx())
305 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
306
307 /* temporarily enabling api_ck to access DSP registers */
308 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
309
310 /* save DSP registers */
311 DSP_SAVE(DSP_IDLECT2);
312
313 /* Stop all DSP domain clocks */
314 __raw_writew(0, DSP_IDLECT2);
315
316 /*
317 * Step 5: Wakeup Event Setup
318 */
319
320 omap_pm_wakeup_setup();
321
322 /*
323 * Step 6: ARM and Traffic controller shutdown
324 */
325
326 /* disable ARM watchdog */
327 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
328 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
329
330 /*
331 * Step 6b: ARM and Traffic controller shutdown
332 *
333 * Step 6 continues here. Prepare jump to power management
334 * assembly code in internal SRAM.
335 *
336 * Since the omap_cpu_suspend routine has been copied to
337 * SRAM, we'll do an indirect procedure call to it and pass the
338 * contents of arm_idlect1 and arm_idlect2 so it can restore
339 * them when it wakes up and it will return.
340 */
341
342 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
343 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
344
345 /*
346 * Step 6c: ARM and Traffic controller shutdown
347 *
348 * Jump to assembly code. The processor will stay there
349 * until wake up.
350 */
351 omap_sram_suspend(arg0, arg1);
352
353 /*
354 * If we are here, processor is woken up!
355 */
356
357 /*
358 * Restore DSP clocks
359 */
360
361 /* again temporarily enabling api_ck to access DSP registers */
362 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
363
364 /* Restore DSP domain clocks */
365 DSP_RESTORE(DSP_IDLECT2);
366
367 /*
368 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
369 */
370
371 if (!(cpu_is_omap15xx()))
372 ARM_RESTORE(ARM_IDLECT3);
373 ARM_RESTORE(ARM_CKCTL);
374 ARM_RESTORE(ARM_EWUPCT);
375 ARM_RESTORE(ARM_RSTCT1);
376 ARM_RESTORE(ARM_RSTCT2);
377 ARM_RESTORE(ARM_SYSST);
378 ULPD_RESTORE(ULPD_CLOCK_CTRL);
379 ULPD_RESTORE(ULPD_STATUS_REQ);
380
381 if (cpu_is_omap7xx()) {
382 MPUI7XX_RESTORE(EMIFS_CONFIG);
383 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
384 MPUI7XX_RESTORE(OMAP_IH1_MIR);
385 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
386 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
387 } else if (cpu_is_omap15xx()) {
388 MPUI1510_RESTORE(MPUI_CTRL);
389 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
390 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
391 MPUI1510_RESTORE(EMIFS_CONFIG);
392 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
393 MPUI1510_RESTORE(OMAP_IH1_MIR);
394 MPUI1510_RESTORE(OMAP_IH2_MIR);
395 } else if (cpu_is_omap16xx()) {
396 MPUI1610_RESTORE(MPUI_CTRL);
397 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
398 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
399 MPUI1610_RESTORE(EMIFS_CONFIG);
400 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
401
402 MPUI1610_RESTORE(OMAP_IH1_MIR);
403 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
404 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
405 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
406 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
407 }
408
409 if (!cpu_is_omap15xx())
410 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
411
412 /*
413 * Re-enable interrupts
414 */
415
416 local_irq_enable();
417 local_fiq_enable();
418
419 omap_serial_wake_trigger(0);
420
421 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
422 omap_rev());
423}
424
425#if defined(DEBUG) && defined(CONFIG_PROC_FS)
426static int g_read_completed;
427
428/*
429 * Read system PM registers for debugging
430 */
431static int omap_pm_read_proc(
432 char *page_buffer,
433 char **my_first_byte,
434 off_t virtual_start,
435 int length,
436 int *eof,
437 void *data)
438{
439 int my_buffer_offset = 0;
440 char * const my_base = page_buffer;
441
442 ARM_SAVE(ARM_CKCTL);
443 ARM_SAVE(ARM_IDLECT1);
444 ARM_SAVE(ARM_IDLECT2);
445 if (!(cpu_is_omap15xx()))
446 ARM_SAVE(ARM_IDLECT3);
447 ARM_SAVE(ARM_EWUPCT);
448 ARM_SAVE(ARM_RSTCT1);
449 ARM_SAVE(ARM_RSTCT2);
450 ARM_SAVE(ARM_SYSST);
451
452 ULPD_SAVE(ULPD_IT_STATUS);
453 ULPD_SAVE(ULPD_CLOCK_CTRL);
454 ULPD_SAVE(ULPD_SOFT_REQ);
455 ULPD_SAVE(ULPD_STATUS_REQ);
456 ULPD_SAVE(ULPD_DPLL_CTRL);
457 ULPD_SAVE(ULPD_POWER_CTRL);
458
459 if (cpu_is_omap7xx()) {
460 MPUI7XX_SAVE(MPUI_CTRL);
461 MPUI7XX_SAVE(MPUI_DSP_STATUS);
462 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
463 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
464 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
465 MPUI7XX_SAVE(EMIFS_CONFIG);
466 } else if (cpu_is_omap15xx()) {
467 MPUI1510_SAVE(MPUI_CTRL);
468 MPUI1510_SAVE(MPUI_DSP_STATUS);
469 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
470 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
471 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
472 MPUI1510_SAVE(EMIFS_CONFIG);
473 } else if (cpu_is_omap16xx()) {
474 MPUI1610_SAVE(MPUI_CTRL);
475 MPUI1610_SAVE(MPUI_DSP_STATUS);
476 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
477 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
478 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
479 MPUI1610_SAVE(EMIFS_CONFIG);
480 }
481
482 if (virtual_start == 0) {
483 g_read_completed = 0;
484
485 my_buffer_offset += sprintf(my_base + my_buffer_offset,
486 "ARM_CKCTL_REG: 0x%-8x \n"
487 "ARM_IDLECT1_REG: 0x%-8x \n"
488 "ARM_IDLECT2_REG: 0x%-8x \n"
489 "ARM_IDLECT3_REG: 0x%-8x \n"
490 "ARM_EWUPCT_REG: 0x%-8x \n"
491 "ARM_RSTCT1_REG: 0x%-8x \n"
492 "ARM_RSTCT2_REG: 0x%-8x \n"
493 "ARM_SYSST_REG: 0x%-8x \n"
494 "ULPD_IT_STATUS_REG: 0x%-4x \n"
495 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
496 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
497 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
498 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
499 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
500 ARM_SHOW(ARM_CKCTL),
501 ARM_SHOW(ARM_IDLECT1),
502 ARM_SHOW(ARM_IDLECT2),
503 ARM_SHOW(ARM_IDLECT3),
504 ARM_SHOW(ARM_EWUPCT),
505 ARM_SHOW(ARM_RSTCT1),
506 ARM_SHOW(ARM_RSTCT2),
507 ARM_SHOW(ARM_SYSST),
508 ULPD_SHOW(ULPD_IT_STATUS),
509 ULPD_SHOW(ULPD_CLOCK_CTRL),
510 ULPD_SHOW(ULPD_SOFT_REQ),
511 ULPD_SHOW(ULPD_DPLL_CTRL),
512 ULPD_SHOW(ULPD_STATUS_REQ),
513 ULPD_SHOW(ULPD_POWER_CTRL));
514
515 if (cpu_is_omap7xx()) {
516 my_buffer_offset += sprintf(my_base + my_buffer_offset,
517 "MPUI7XX_CTRL_REG 0x%-8x \n"
518 "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
519 "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
520 "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
521 "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
522 "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
523 MPUI7XX_SHOW(MPUI_CTRL),
524 MPUI7XX_SHOW(MPUI_DSP_STATUS),
525 MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
526 MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
527 MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
528 MPUI7XX_SHOW(EMIFS_CONFIG));
529 } else if (cpu_is_omap15xx()) {
530 my_buffer_offset += sprintf(my_base + my_buffer_offset,
531 "MPUI1510_CTRL_REG 0x%-8x \n"
532 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
533 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
534 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
535 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
536 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
537 MPUI1510_SHOW(MPUI_CTRL),
538 MPUI1510_SHOW(MPUI_DSP_STATUS),
539 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
540 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
541 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
542 MPUI1510_SHOW(EMIFS_CONFIG));
543 } else if (cpu_is_omap16xx()) {
544 my_buffer_offset += sprintf(my_base + my_buffer_offset,
545 "MPUI1610_CTRL_REG 0x%-8x \n"
546 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
547 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
548 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
549 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
550 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
551 MPUI1610_SHOW(MPUI_CTRL),
552 MPUI1610_SHOW(MPUI_DSP_STATUS),
553 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
554 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
555 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
556 MPUI1610_SHOW(EMIFS_CONFIG));
557 }
558
559 g_read_completed++;
560 } else if (g_read_completed >= 1) {
561 *eof = 1;
562 return 0;
563 }
564 g_read_completed++;
565
566 *my_first_byte = page_buffer;
567 return my_buffer_offset;
568}
569
570static void omap_pm_init_proc(void)
571{
572 /* XXX Appears to leak memory */
573 create_proc_read_entry("driver/omap_pm",
574 S_IWUSR | S_IRUGO, NULL,
575 omap_pm_read_proc, NULL);
576}
577
578#endif /* DEBUG && CONFIG_PROC_FS */
579
580/*
581 * omap_pm_prepare - Do preliminary suspend work.
582 *
583 */
584static int omap_pm_prepare(void)
585{
586 /* We cannot sleep in idle until we have resumed */
587 disable_hlt();
588
589 return 0;
590}
591
592
593/*
594 * omap_pm_enter - Actually enter a sleep state.
595 * @state: State we're entering.
596 *
597 */
598
599static int omap_pm_enter(suspend_state_t state)
600{
601 switch (state)
602 {
603 case PM_SUSPEND_STANDBY:
604 case PM_SUSPEND_MEM:
605 omap1_pm_suspend();
606 break;
607 default:
608 return -EINVAL;
609 }
610
611 return 0;
612}
613
614
615/**
616 * omap_pm_finish - Finish up suspend sequence.
617 *
618 * This is called after we wake back up (or if entering the sleep state
619 * failed).
620 */
621
622static void omap_pm_finish(void)
623{
624 enable_hlt();
625}
626
627
628static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
629{
630 return IRQ_HANDLED;
631}
632
633static struct irqaction omap_wakeup_irq = {
634 .name = "peripheral wakeup",
635 .flags = IRQF_DISABLED,
636 .handler = omap_wakeup_interrupt
637};
638
639
640
641static const struct platform_suspend_ops omap_pm_ops = {
642 .prepare = omap_pm_prepare,
643 .enter = omap_pm_enter,
644 .finish = omap_pm_finish,
645 .valid = suspend_valid_only_mem,
646};
647
648static int __init omap_pm_init(void)
649{
650
651#ifdef CONFIG_OMAP_32K_TIMER
652 int error;
653#endif
654
655 if (!cpu_class_is_omap1())
656 return -ENODEV;
657
658 printk("Power Management for TI OMAP.\n");
659
660 /*
661 * We copy the assembler sleep/wakeup routines to SRAM.
662 * These routines need to be in SRAM as that's the only
663 * memory the MPU can see when it wakes up.
664 */
665 if (cpu_is_omap7xx()) {
666 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
667 omap7xx_cpu_suspend_sz);
668 } else if (cpu_is_omap15xx()) {
669 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
670 omap1510_cpu_suspend_sz);
671 } else if (cpu_is_omap16xx()) {
672 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
673 omap1610_cpu_suspend_sz);
674 }
675
676 if (omap_sram_suspend == NULL) {
677 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
678 return -ENODEV;
679 }
680
681 arm_pm_idle = omap1_pm_idle;
682
683 if (cpu_is_omap7xx())
684 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
685 else if (cpu_is_omap16xx())
686 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
687
688 /* Program new power ramp-up time
689 * (0 for most boards since we don't lower voltage when in deep sleep)
690 */
691 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
692
693 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
694 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
695
696 /* Configure IDLECT3 */
697 if (cpu_is_omap7xx())
698 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
699 else if (cpu_is_omap16xx())
700 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
701
702 suspend_set_ops(&omap_pm_ops);
703
704#if defined(DEBUG) && defined(CONFIG_PROC_FS)
705 omap_pm_init_proc();
706#endif
707
708#ifdef CONFIG_OMAP_32K_TIMER
709 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
710 if (error)
711 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
712#endif
713
714 if (cpu_is_omap16xx()) {
715 /* configure LOW_PWR pin */
716 omap_cfg_reg(T20_1610_LOW_PWR);
717 }
718
719 return 0;
720}
721__initcall(omap_pm_init);