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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * CoreTile Express A5x2
6 * Cortex-A5 MPCore (V2P-CA5s)
7 *
8 * HBI-0225B
9 */
10
11/dts-v1/;
12
13/ {
14 model = "V2P-CA5s";
15 arm,hbi = <0x225>;
16 arm,vexpress,site = <0xf>;
17 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 chosen { };
23
24 aliases {
25 serial0 = &v2m_serial0;
26 serial1 = &v2m_serial1;
27 serial2 = &v2m_serial2;
28 serial3 = &v2m_serial3;
29 i2c0 = &v2m_i2c_dvi;
30 i2c1 = &v2m_i2c_pcie;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a5";
40 reg = <0>;
41 next-level-cache = <&L2>;
42 };
43
44 cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a5";
47 reg = <1>;
48 next-level-cache = <&L2>;
49 };
50 };
51
52 memory@80000000 {
53 device_type = "memory";
54 reg = <0x80000000 0x40000000>;
55 };
56
57 hdlcd@2a110000 {
58 compatible = "arm,hdlcd";
59 reg = <0x2a110000 0x1000>;
60 interrupts = <0 85 4>;
61 clocks = <&hdlcd_clk>;
62 clock-names = "pxlclk";
63 };
64
65 memory-controller@2a150000 {
66 compatible = "arm,pl341", "arm,primecell";
67 reg = <0x2a150000 0x1000>;
68 clocks = <&axi_clk>;
69 clock-names = "apb_pclk";
70 };
71
72 memory-controller@2a190000 {
73 compatible = "arm,pl354", "arm,primecell";
74 reg = <0x2a190000 0x1000>;
75 interrupts = <0 86 4>,
76 <0 87 4>;
77 clocks = <&axi_clk>;
78 clock-names = "apb_pclk";
79 };
80
81 scu@2c000000 {
82 compatible = "arm,cortex-a5-scu";
83 reg = <0x2c000000 0x58>;
84 };
85
86 timer@2c000600 {
87 compatible = "arm,cortex-a5-twd-timer";
88 reg = <0x2c000600 0x20>;
89 interrupts = <1 13 0x304>;
90 };
91
92 timer@2c000200 {
93 compatible = "arm,cortex-a5-global-timer",
94 "arm,cortex-a9-global-timer";
95 reg = <0x2c000200 0x20>;
96 interrupts = <1 11 0x304>;
97 clocks = <&cpu_clk>;
98 };
99
100 watchdog@2c000620 {
101 compatible = "arm,cortex-a5-twd-wdt";
102 reg = <0x2c000620 0x20>;
103 interrupts = <1 14 0x304>;
104 };
105
106 gic: interrupt-controller@2c001000 {
107 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
108 #interrupt-cells = <3>;
109 #address-cells = <0>;
110 interrupt-controller;
111 reg = <0x2c001000 0x1000>,
112 <0x2c000100 0x100>;
113 };
114
115 L2: cache-controller@2c0f0000 {
116 compatible = "arm,pl310-cache";
117 reg = <0x2c0f0000 0x1000>;
118 interrupts = <0 84 4>;
119 cache-level = <2>;
120 };
121
122 pmu {
123 compatible = "arm,cortex-a5-pmu";
124 interrupts = <0 68 4>,
125 <0 69 4>;
126 };
127
128 dcc {
129 compatible = "arm,vexpress,config-bus";
130 arm,vexpress,config-bridge = <&v2m_sysreg>;
131
132 cpu_clk: oscclk0 {
133 /* CPU and internal AXI reference clock */
134 compatible = "arm,vexpress-osc";
135 arm,vexpress-sysreg,func = <1 0>;
136 freq-range = <50000000 100000000>;
137 #clock-cells = <0>;
138 clock-output-names = "oscclk0";
139 };
140
141 axi_clk: oscclk1 {
142 /* Multiplexed AXI master clock */
143 compatible = "arm,vexpress-osc";
144 arm,vexpress-sysreg,func = <1 1>;
145 freq-range = <5000000 50000000>;
146 #clock-cells = <0>;
147 clock-output-names = "oscclk1";
148 };
149
150 oscclk2 {
151 /* DDR2 */
152 compatible = "arm,vexpress-osc";
153 arm,vexpress-sysreg,func = <1 2>;
154 freq-range = <80000000 120000000>;
155 #clock-cells = <0>;
156 clock-output-names = "oscclk2";
157 };
158
159 hdlcd_clk: oscclk3 {
160 /* HDLCD */
161 compatible = "arm,vexpress-osc";
162 arm,vexpress-sysreg,func = <1 3>;
163 freq-range = <23750000 165000000>;
164 #clock-cells = <0>;
165 clock-output-names = "oscclk3";
166 };
167
168 oscclk4 {
169 /* Test chip gate configuration */
170 compatible = "arm,vexpress-osc";
171 arm,vexpress-sysreg,func = <1 4>;
172 freq-range = <80000000 80000000>;
173 #clock-cells = <0>;
174 clock-output-names = "oscclk4";
175 };
176
177 smbclk: oscclk5 {
178 /* SMB clock */
179 compatible = "arm,vexpress-osc";
180 arm,vexpress-sysreg,func = <1 5>;
181 freq-range = <25000000 60000000>;
182 #clock-cells = <0>;
183 clock-output-names = "oscclk5";
184 };
185
186 temp-dcc {
187 /* DCC internal operating temperature */
188 compatible = "arm,vexpress-temp";
189 arm,vexpress-sysreg,func = <4 0>;
190 label = "DCC";
191 };
192 };
193
194 smb@8000000 {
195 compatible = "simple-bus";
196
197 #address-cells = <2>;
198 #size-cells = <1>;
199 ranges = <0 0 0x08000000 0x04000000>,
200 <1 0 0x14000000 0x04000000>,
201 <2 0 0x18000000 0x04000000>,
202 <3 0 0x1c000000 0x04000000>,
203 <4 0 0x0c000000 0x04000000>,
204 <5 0 0x10000000 0x04000000>;
205
206 #interrupt-cells = <1>;
207 interrupt-map-mask = <0 0 63>;
208 interrupt-map = <0 0 0 &gic 0 0 4>,
209 <0 0 1 &gic 0 1 4>,
210 <0 0 2 &gic 0 2 4>,
211 <0 0 3 &gic 0 3 4>,
212 <0 0 4 &gic 0 4 4>,
213 <0 0 5 &gic 0 5 4>,
214 <0 0 6 &gic 0 6 4>,
215 <0 0 7 &gic 0 7 4>,
216 <0 0 8 &gic 0 8 4>,
217 <0 0 9 &gic 0 9 4>,
218 <0 0 10 &gic 0 10 4>,
219 <0 0 11 &gic 0 11 4>,
220 <0 0 12 &gic 0 12 4>,
221 <0 0 13 &gic 0 13 4>,
222 <0 0 14 &gic 0 14 4>,
223 <0 0 15 &gic 0 15 4>,
224 <0 0 16 &gic 0 16 4>,
225 <0 0 17 &gic 0 17 4>,
226 <0 0 18 &gic 0 18 4>,
227 <0 0 19 &gic 0 19 4>,
228 <0 0 20 &gic 0 20 4>,
229 <0 0 21 &gic 0 21 4>,
230 <0 0 22 &gic 0 22 4>,
231 <0 0 23 &gic 0 23 4>,
232 <0 0 24 &gic 0 24 4>,
233 <0 0 25 &gic 0 25 4>,
234 <0 0 26 &gic 0 26 4>,
235 <0 0 27 &gic 0 27 4>,
236 <0 0 28 &gic 0 28 4>,
237 <0 0 29 &gic 0 29 4>,
238 <0 0 30 &gic 0 30 4>,
239 <0 0 31 &gic 0 31 4>,
240 <0 0 32 &gic 0 32 4>,
241 <0 0 33 &gic 0 33 4>,
242 <0 0 34 &gic 0 34 4>,
243 <0 0 35 &gic 0 35 4>,
244 <0 0 36 &gic 0 36 4>,
245 <0 0 37 &gic 0 37 4>,
246 <0 0 38 &gic 0 38 4>,
247 <0 0 39 &gic 0 39 4>,
248 <0 0 40 &gic 0 40 4>,
249 <0 0 41 &gic 0 41 4>,
250 <0 0 42 &gic 0 42 4>;
251
252 /include/ "vexpress-v2m-rs1.dtsi"
253 };
254
255 site2: hsb@40000000 {
256 compatible = "simple-bus";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 ranges = <0 0x40000000 0x40000000>;
260 #interrupt-cells = <1>;
261 interrupt-map-mask = <0 3>;
262 interrupt-map = <0 0 &gic 0 36 4>,
263 <0 1 &gic 0 37 4>,
264 <0 2 &gic 0 38 4>,
265 <0 3 &gic 0 39 4>;
266 };
267};
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A5x2
5 * Cortex-A5 MPCore (V2P-CA5s)
6 *
7 * HBI-0225B
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA5s";
14 arm,hbi = <0x225>;
15 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 chosen { };
21
22 aliases {
23 serial0 = &v2m_serial0;
24 serial1 = &v2m_serial1;
25 serial2 = &v2m_serial2;
26 serial3 = &v2m_serial3;
27 i2c0 = &v2m_i2c_dvi;
28 i2c1 = &v2m_i2c_pcie;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a5";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a5";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory@80000000 {
51 device_type = "memory";
52 reg = <0x80000000 0x40000000>;
53 };
54
55 hdlcd@2a110000 {
56 compatible = "arm,hdlcd";
57 reg = <0x2a110000 0x1000>;
58 interrupts = <0 85 4>;
59 };
60
61 memory-controller@2a150000 {
62 compatible = "arm,pl341", "arm,primecell";
63 reg = <0x2a150000 0x1000>;
64 };
65
66 memory-controller@2a190000 {
67 compatible = "arm,pl354", "arm,primecell";
68 reg = <0x2a190000 0x1000>;
69 interrupts = <0 86 4>,
70 <0 87 4>;
71 };
72
73 scu@2c000000 {
74 compatible = "arm,cortex-a5-scu";
75 reg = <0x2c000000 0x58>;
76 };
77
78 timer@2c000600 {
79 compatible = "arm,cortex-a5-twd-timer";
80 reg = <0x2c000600 0x20>;
81 interrupts = <1 13 0x304>;
82 };
83
84 watchdog@2c000620 {
85 compatible = "arm,cortex-a5-twd-wdt";
86 reg = <0x2c000620 0x20>;
87 interrupts = <1 14 0x304>;
88 };
89
90 gic: interrupt-controller@2c001000 {
91 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
94 interrupt-controller;
95 reg = <0x2c001000 0x1000>,
96 <0x2c000100 0x100>;
97 };
98
99 L2: cache-controller@2c0f0000 {
100 compatible = "arm,pl310-cache";
101 reg = <0x2c0f0000 0x1000>;
102 interrupts = <0 84 4>;
103 cache-level = <2>;
104 };
105
106 pmu {
107 compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
108 interrupts = <0 68 4>,
109 <0 69 4>;
110 };
111
112 motherboard {
113 ranges = <0 0 0x08000000 0x04000000>,
114 <1 0 0x14000000 0x04000000>,
115 <2 0 0x18000000 0x04000000>,
116 <3 0 0x1c000000 0x04000000>,
117 <4 0 0x0c000000 0x04000000>,
118 <5 0 0x10000000 0x04000000>;
119
120 interrupt-map-mask = <0 0 63>;
121 interrupt-map = <0 0 0 &gic 0 0 4>,
122 <0 0 1 &gic 0 1 4>,
123 <0 0 2 &gic 0 2 4>,
124 <0 0 3 &gic 0 3 4>,
125 <0 0 4 &gic 0 4 4>,
126 <0 0 5 &gic 0 5 4>,
127 <0 0 6 &gic 0 6 4>,
128 <0 0 7 &gic 0 7 4>,
129 <0 0 8 &gic 0 8 4>,
130 <0 0 9 &gic 0 9 4>,
131 <0 0 10 &gic 0 10 4>,
132 <0 0 11 &gic 0 11 4>,
133 <0 0 12 &gic 0 12 4>,
134 <0 0 13 &gic 0 13 4>,
135 <0 0 14 &gic 0 14 4>,
136 <0 0 15 &gic 0 15 4>,
137 <0 0 16 &gic 0 16 4>,
138 <0 0 17 &gic 0 17 4>,
139 <0 0 18 &gic 0 18 4>,
140 <0 0 19 &gic 0 19 4>,
141 <0 0 20 &gic 0 20 4>,
142 <0 0 21 &gic 0 21 4>,
143 <0 0 22 &gic 0 22 4>,
144 <0 0 23 &gic 0 23 4>,
145 <0 0 24 &gic 0 24 4>,
146 <0 0 25 &gic 0 25 4>,
147 <0 0 26 &gic 0 26 4>,
148 <0 0 27 &gic 0 27 4>,
149 <0 0 28 &gic 0 28 4>,
150 <0 0 29 &gic 0 29 4>,
151 <0 0 30 &gic 0 30 4>,
152 <0 0 31 &gic 0 31 4>,
153 <0 0 32 &gic 0 32 4>,
154 <0 0 33 &gic 0 33 4>,
155 <0 0 34 &gic 0 34 4>,
156 <0 0 35 &gic 0 35 4>,
157 <0 0 36 &gic 0 36 4>,
158 <0 0 37 &gic 0 37 4>,
159 <0 0 38 &gic 0 38 4>,
160 <0 0 39 &gic 0 39 4>,
161 <0 0 40 &gic 0 40 4>,
162 <0 0 41 &gic 0 41 4>,
163 <0 0 42 &gic 0 42 4>;
164 };
165};
166
167/include/ "vexpress-v2m-rs1.dtsi"