1/*
  2 * Copyright (C) 2014 STMicroelectronics Limited.
  3 * Author: Peter Griffin <peter.griffin@linaro.org>
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 as
  7 * publishhed by the Free Software Foundation.
  8 */
  9#include "stih418-clock.dtsi"
 10#include "stih407-family.dtsi"
 11#include "stih410-pinctrl.dtsi"
 12/ {
 13	cpus {
 14		#address-cells = <1>;
 15		#size-cells = <0>;
 16		cpu@2 {
 17			device_type = "cpu";
 18			compatible = "arm,cortex-a9";
 19			reg = <2>;
 20			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
 21			cpu-release-addr = <0x94100A4>;
 22		};
 23		cpu@3 {
 24			device_type = "cpu";
 25			compatible = "arm,cortex-a9";
 26			reg = <3>;
 27			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
 28			cpu-release-addr = <0x94100A4>;
 29		};
 30	};
 31
 32	soc {
 33		usb2_picophy1: phy2@0 {
 34			compatible = "st,stih407-usb2-phy";
 35			reg = <0 0>;
 36			#phy-cells = <0>;
 37			st,syscfg = <&syscfg_core 0xf8 0xf4>;
 38			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 39				 <&picophyreset STIH407_PICOPHY0_RESET>;
 40			reset-names = "global", "port";
 41		};
 42
 43		usb2_picophy2: phy3@0 {
 44			compatible = "st,stih407-usb2-phy";
 45			reg = <0 0>;
 46			#phy-cells = <0>;
 47			st,syscfg = <&syscfg_core 0xfc 0xf4>;
 48			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
 49				 <&picophyreset STIH407_PICOPHY1_RESET>;
 50			reset-names = "global", "port";
 51		};
 52
 53		ohci0: usb@9a03c00 {
 54			compatible = "st,st-ohci-300x";
 55			reg = <0x9a03c00 0x100>;
 56			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
 57			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
 58			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
 59				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
 60			reset-names = "power", "softreset";
 61			phys = <&usb2_picophy1>;
 62			phy-names = "usb";
 63		};
 64
 65		ehci0: usb@9a03e00 {
 66			compatible = "st,st-ehci-300x";
 67			reg = <0x9a03e00 0x100>;
 68			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 69			pinctrl-names = "default";
 70			pinctrl-0 = <&pinctrl_usb0>;
 71			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
 72			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
 73				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
 74			reset-names = "power", "softreset";
 75			phys = <&usb2_picophy1>;
 76			phy-names = "usb";
 77		};
 78
 79		ohci1: usb@9a83c00 {
 80			compatible = "st,st-ohci-300x";
 81			reg = <0x9a83c00 0x100>;
 82			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
 83			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
 84			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
 85				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
 86			reset-names = "power", "softreset";
 87			phys = <&usb2_picophy2>;
 88			phy-names = "usb";
 89		};
 90
 91		ehci1: usb@9a83e00 {
 92			compatible = "st,st-ehci-300x";
 93			reg = <0x9a83e00 0x100>;
 94			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
 95			pinctrl-names = "default";
 96			pinctrl-0 = <&pinctrl_usb1>;
 97			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
 98			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
 99				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
100			reset-names = "power", "softreset";
101			phys = <&usb2_picophy2>;
102			phy-names = "usb";
103		};
104
105		mmc0: sdhci@9060000 {
106			assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
107			assigned-clock-parents = <&clk_s_c0_pll1 0>;
108			assigned-clock-rates = <200000000>;
109		};
110	};
111};