1/*
  2 * Actions Semi S500 SoC
  3 *
  4 * Copyright (c) 2016-2017 Andreas Färber
  5 *
  6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  7 */
  8
  9#include <dt-bindings/interrupt-controller/arm-gic.h>
 10#include <dt-bindings/power/owl-s500-powergate.h>
 11
 12/ {
 13	compatible = "actions,s500";
 14	interrupt-parent = <&gic>;
 15	#address-cells = <1>;
 16	#size-cells = <1>;
 17
 18	aliases {
 19	};
 20
 21	chosen {
 22	};
 23
 24	cpus {
 25		#address-cells = <1>;
 26		#size-cells = <0>;
 27
 28		cpu0: cpu@0 {
 29			device_type = "cpu";
 30			compatible = "arm,cortex-a9";
 31			reg = <0x0>;
 32			enable-method = "actions,s500-smp";
 33		};
 34
 35		cpu1: cpu@1 {
 36			device_type = "cpu";
 37			compatible = "arm,cortex-a9";
 38			reg = <0x1>;
 39			enable-method = "actions,s500-smp";
 40		};
 41
 42		cpu2: cpu@2 {
 43			device_type = "cpu";
 44			compatible = "arm,cortex-a9";
 45			reg = <0x2>;
 46			enable-method = "actions,s500-smp";
 47			power-domains = <&sps S500_PD_CPU2>;
 48		};
 49
 50		cpu3: cpu@3 {
 51			device_type = "cpu";
 52			compatible = "arm,cortex-a9";
 53			reg = <0x3>;
 54			enable-method = "actions,s500-smp";
 55			power-domains = <&sps S500_PD_CPU3>;
 56		};
 57	};
 58
 59	arm-pmu {
 60		compatible = "arm,cortex-a9-pmu";
 61		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 62		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 63		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 64		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 65		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 66	};
 67
 68	hosc: hosc {
 69		compatible = "fixed-clock";
 70		clock-frequency = <24000000>;
 71		#clock-cells = <0>;
 72	};
 73
 74	soc {
 75		compatible = "simple-bus";
 76		#address-cells = <1>;
 77		#size-cells = <1>;
 78		ranges;
 79
 80		scu: scu@b0020000 {
 81			compatible = "arm,cortex-a9-scu";
 82			reg = <0xb0020000 0x100>;
 83		};
 84
 85		global_timer: timer@b0020200 {
 86			compatible = "arm,cortex-a9-global-timer";
 87			reg = <0xb0020200 0x100>;
 88			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 89			status = "disabled";
 90		};
 91
 92		twd_timer: timer@b0020600 {
 93			compatible = "arm,cortex-a9-twd-timer";
 94			reg = <0xb0020600 0x20>;
 95			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 96			status = "disabled";
 97		};
 98
 99		twd_wdt: wdt@b0020620 {
100			compatible = "arm,cortex-a9-twd-wdt";
101			reg = <0xb0020620 0xe0>;
102			interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
103			status = "disabled";
104		};
105
106		gic: interrupt-controller@b0021000 {
107			compatible = "arm,cortex-a9-gic";
108			reg = <0xb0021000 0x1000>,
109			      <0xb0020100 0x0100>;
110			interrupt-controller;
111			#interrupt-cells = <3>;
112		};
113
114		l2: cache-controller@b0022000 {
115			compatible = "arm,pl310-cache";
116			reg = <0xb0022000 0x1000>;
117			cache-unified;
118			cache-level = <2>;
119			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
120			arm,tag-latency = <3 3 2>;
121			arm,data-latency = <5 3 3>;
122		};
123
124		uart0: serial@b0120000 {
125			compatible = "actions,s500-uart", "actions,owl-uart";
126			reg = <0xb0120000 0x2000>;
127			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
128			status = "disabled";
129		};
130
131		uart1: serial@b0122000 {
132			compatible = "actions,s500-uart", "actions,owl-uart";
133			reg = <0xb0122000 0x2000>;
134			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
135			status = "disabled";
136		};
137
138		uart2: serial@b0124000 {
139			compatible = "actions,s500-uart", "actions,owl-uart";
140			reg = <0xb0124000 0x2000>;
141			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
142			status = "disabled";
143		};
144
145		uart3: serial@b0126000 {
146			compatible = "actions,s500-uart", "actions,owl-uart";
147			reg = <0xb0126000 0x2000>;
148			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
149			status = "disabled";
150		};
151
152		uart4: serial@b0128000 {
153			compatible = "actions,s500-uart", "actions,owl-uart";
154			reg = <0xb0128000 0x2000>;
155			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
156			status = "disabled";
157		};
158
159		uart5: serial@b012a000 {
160			compatible = "actions,s500-uart", "actions,owl-uart";
161			reg = <0xb012a000 0x2000>;
162			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
163			status = "disabled";
164		};
165
166		uart6: serial@b012c000 {
167			compatible = "actions,s500-uart", "actions,owl-uart";
168			reg = <0xb012c000 0x2000>;
169			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
170			status = "disabled";
171		};
172
173		timer: timer@b0168000 {
174			compatible = "actions,s500-timer";
175			reg = <0xb0168000 0x8000>;
176			interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
177			             <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
178			             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
179			             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
180			interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
181		};
182
183		sps: power-controller@b01b0100 {
184			compatible = "actions,s500-sps";
185			reg = <0xb01b0100 0x100>;
186			#power-domain-cells = <1>;
187		};
188	};
189};