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1/*
2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
3 *
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/clk-provider.h>
19#include <linux/delay.h>
20#include <linux/extcon-provider.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/gpio/consumer.h>
24#include <linux/jiffies.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/mutex.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_platform.h>
32#include <linux/phy/phy.h>
33#include <linux/platform_device.h>
34#include <linux/power_supply.h>
35#include <linux/regmap.h>
36#include <linux/mfd/syscon.h>
37#include <linux/usb/of.h>
38#include <linux/usb/otg.h>
39
40#define BIT_WRITEABLE_SHIFT 16
41#define SCHEDULE_DELAY (60 * HZ)
42#define OTG_SCHEDULE_DELAY (2 * HZ)
43
44enum rockchip_usb2phy_port_id {
45 USB2PHY_PORT_OTG,
46 USB2PHY_PORT_HOST,
47 USB2PHY_NUM_PORTS,
48};
49
50enum rockchip_usb2phy_host_state {
51 PHY_STATE_HS_ONLINE = 0,
52 PHY_STATE_DISCONNECT = 1,
53 PHY_STATE_CONNECT = 2,
54 PHY_STATE_FS_LS_ONLINE = 4,
55};
56
57/**
58 * Different states involved in USB charger detection.
59 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
60 * process is not yet started.
61 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
62 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
63 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
64 * between SDP and DCP/CDP).
65 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
66 * between DCP and CDP).
67 * USB_CHG_STATE_DETECTED USB charger type is determined.
68 */
69enum usb_chg_state {
70 USB_CHG_STATE_UNDEFINED = 0,
71 USB_CHG_STATE_WAIT_FOR_DCD,
72 USB_CHG_STATE_DCD_DONE,
73 USB_CHG_STATE_PRIMARY_DONE,
74 USB_CHG_STATE_SECONDARY_DONE,
75 USB_CHG_STATE_DETECTED,
76};
77
78static const unsigned int rockchip_usb2phy_extcon_cable[] = {
79 EXTCON_USB,
80 EXTCON_USB_HOST,
81 EXTCON_CHG_USB_SDP,
82 EXTCON_CHG_USB_CDP,
83 EXTCON_CHG_USB_DCP,
84 EXTCON_CHG_USB_SLOW,
85 EXTCON_NONE,
86};
87
88struct usb2phy_reg {
89 unsigned int offset;
90 unsigned int bitend;
91 unsigned int bitstart;
92 unsigned int disable;
93 unsigned int enable;
94};
95
96/**
97 * struct rockchip_chg_det_reg: usb charger detect registers
98 * @cp_det: charging port detected successfully.
99 * @dcp_det: dedicated charging port detected successfully.
100 * @dp_det: assert data pin connect successfully.
101 * @idm_sink_en: open dm sink curren.
102 * @idp_sink_en: open dp sink current.
103 * @idp_src_en: open dm source current.
104 * @rdm_pdwn_en: open dm pull down resistor.
105 * @vdm_src_en: open dm voltage source.
106 * @vdp_src_en: open dp voltage source.
107 * @opmode: utmi operational mode.
108 */
109struct rockchip_chg_det_reg {
110 struct usb2phy_reg cp_det;
111 struct usb2phy_reg dcp_det;
112 struct usb2phy_reg dp_det;
113 struct usb2phy_reg idm_sink_en;
114 struct usb2phy_reg idp_sink_en;
115 struct usb2phy_reg idp_src_en;
116 struct usb2phy_reg rdm_pdwn_en;
117 struct usb2phy_reg vdm_src_en;
118 struct usb2phy_reg vdp_src_en;
119 struct usb2phy_reg opmode;
120};
121
122/**
123 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
124 * @phy_sus: phy suspend register.
125 * @bvalid_det_en: vbus valid rise detection enable register.
126 * @bvalid_det_st: vbus valid rise detection status register.
127 * @bvalid_det_clr: vbus valid rise detection clear register.
128 * @ls_det_en: linestate detection enable register.
129 * @ls_det_st: linestate detection state register.
130 * @ls_det_clr: linestate detection clear register.
131 * @utmi_avalid: utmi vbus avalid status register.
132 * @utmi_bvalid: utmi vbus bvalid status register.
133 * @utmi_ls: utmi linestate state register.
134 * @utmi_hstdet: utmi host disconnect register.
135 */
136struct rockchip_usb2phy_port_cfg {
137 struct usb2phy_reg phy_sus;
138 struct usb2phy_reg bvalid_det_en;
139 struct usb2phy_reg bvalid_det_st;
140 struct usb2phy_reg bvalid_det_clr;
141 struct usb2phy_reg ls_det_en;
142 struct usb2phy_reg ls_det_st;
143 struct usb2phy_reg ls_det_clr;
144 struct usb2phy_reg utmi_avalid;
145 struct usb2phy_reg utmi_bvalid;
146 struct usb2phy_reg utmi_ls;
147 struct usb2phy_reg utmi_hstdet;
148};
149
150/**
151 * struct rockchip_usb2phy_cfg: usb-phy configuration.
152 * @reg: the address offset of grf for usb-phy config.
153 * @num_ports: specify how many ports that the phy has.
154 * @clkout_ctl: keep on/turn off output clk of phy.
155 * @chg_det: charger detection registers.
156 */
157struct rockchip_usb2phy_cfg {
158 unsigned int reg;
159 unsigned int num_ports;
160 struct usb2phy_reg clkout_ctl;
161 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
162 const struct rockchip_chg_det_reg chg_det;
163};
164
165/**
166 * struct rockchip_usb2phy_port: usb-phy port data.
167 * @port_id: flag for otg port or host port.
168 * @suspended: phy suspended flag.
169 * @utmi_avalid: utmi avalid status usage flag.
170 * true - use avalid to get vbus status
171 * flase - use bvalid to get vbus status
172 * @vbus_attached: otg device vbus status.
173 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
174 * @ls_irq: IRQ number assigned for linestate detection.
175 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
176 * irqs to one irq in otg-port.
177 * @mutex: for register updating in sm_work.
178 * @chg_work: charge detect work.
179 * @otg_sm_work: OTG state machine work.
180 * @sm_work: HOST state machine work.
181 * @phy_cfg: port register configuration, assigned by driver data.
182 * @event_nb: hold event notification callback.
183 * @state: define OTG enumeration states before device reset.
184 * @mode: the dr_mode of the controller.
185 */
186struct rockchip_usb2phy_port {
187 struct phy *phy;
188 unsigned int port_id;
189 bool suspended;
190 bool utmi_avalid;
191 bool vbus_attached;
192 int bvalid_irq;
193 int ls_irq;
194 int otg_mux_irq;
195 struct mutex mutex;
196 struct delayed_work chg_work;
197 struct delayed_work otg_sm_work;
198 struct delayed_work sm_work;
199 const struct rockchip_usb2phy_port_cfg *port_cfg;
200 struct notifier_block event_nb;
201 enum usb_otg_state state;
202 enum usb_dr_mode mode;
203};
204
205/**
206 * struct rockchip_usb2phy: usb2.0 phy driver data.
207 * @grf: General Register Files regmap.
208 * @usbgrf: USB General Register Files regmap.
209 * @clk: clock struct of phy input clk.
210 * @clk480m: clock struct of phy output clk.
211 * @clk_hw: clock struct of phy output clk management.
212 * @chg_state: states involved in USB charger detection.
213 * @chg_type: USB charger types.
214 * @dcd_retries: The retry count used to track Data contact
215 * detection process.
216 * @edev: extcon device for notification registration
217 * @phy_cfg: phy register configuration, assigned by driver data.
218 * @ports: phy port instance.
219 */
220struct rockchip_usb2phy {
221 struct device *dev;
222 struct regmap *grf;
223 struct regmap *usbgrf;
224 struct clk *clk;
225 struct clk *clk480m;
226 struct clk_hw clk480m_hw;
227 enum usb_chg_state chg_state;
228 enum power_supply_type chg_type;
229 u8 dcd_retries;
230 struct extcon_dev *edev;
231 const struct rockchip_usb2phy_cfg *phy_cfg;
232 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
233};
234
235static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
236{
237 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
238}
239
240static inline int property_enable(struct regmap *base,
241 const struct usb2phy_reg *reg, bool en)
242{
243 unsigned int val, mask, tmp;
244
245 tmp = en ? reg->enable : reg->disable;
246 mask = GENMASK(reg->bitend, reg->bitstart);
247 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
248
249 return regmap_write(base, reg->offset, val);
250}
251
252static inline bool property_enabled(struct regmap *base,
253 const struct usb2phy_reg *reg)
254{
255 int ret;
256 unsigned int tmp, orig;
257 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
258
259 ret = regmap_read(base, reg->offset, &orig);
260 if (ret)
261 return false;
262
263 tmp = (orig & mask) >> reg->bitstart;
264 return tmp == reg->enable;
265}
266
267static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
268{
269 struct rockchip_usb2phy *rphy =
270 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
271 struct regmap *base = get_reg_base(rphy);
272 int ret;
273
274 /* turn on 480m clk output if it is off */
275 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
276 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
277 if (ret)
278 return ret;
279
280 /* waiting for the clk become stable */
281 usleep_range(1200, 1300);
282 }
283
284 return 0;
285}
286
287static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
288{
289 struct rockchip_usb2phy *rphy =
290 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
291 struct regmap *base = get_reg_base(rphy);
292
293 /* turn off 480m clk output */
294 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
295}
296
297static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
298{
299 struct rockchip_usb2phy *rphy =
300 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
301 struct regmap *base = get_reg_base(rphy);
302
303 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
304}
305
306static unsigned long
307rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
308 unsigned long parent_rate)
309{
310 return 480000000;
311}
312
313static const struct clk_ops rockchip_usb2phy_clkout_ops = {
314 .prepare = rockchip_usb2phy_clk480m_prepare,
315 .unprepare = rockchip_usb2phy_clk480m_unprepare,
316 .is_prepared = rockchip_usb2phy_clk480m_prepared,
317 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
318};
319
320static void rockchip_usb2phy_clk480m_unregister(void *data)
321{
322 struct rockchip_usb2phy *rphy = data;
323
324 of_clk_del_provider(rphy->dev->of_node);
325 clk_unregister(rphy->clk480m);
326}
327
328static int
329rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
330{
331 struct device_node *node = rphy->dev->of_node;
332 struct clk_init_data init;
333 const char *clk_name;
334 int ret;
335
336 init.flags = 0;
337 init.name = "clk_usbphy_480m";
338 init.ops = &rockchip_usb2phy_clkout_ops;
339
340 /* optional override of the clockname */
341 of_property_read_string(node, "clock-output-names", &init.name);
342
343 if (rphy->clk) {
344 clk_name = __clk_get_name(rphy->clk);
345 init.parent_names = &clk_name;
346 init.num_parents = 1;
347 } else {
348 init.parent_names = NULL;
349 init.num_parents = 0;
350 }
351
352 rphy->clk480m_hw.init = &init;
353
354 /* register the clock */
355 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
356 if (IS_ERR(rphy->clk480m)) {
357 ret = PTR_ERR(rphy->clk480m);
358 goto err_ret;
359 }
360
361 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
362 if (ret < 0)
363 goto err_clk_provider;
364
365 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
366 rphy);
367 if (ret < 0)
368 goto err_unreg_action;
369
370 return 0;
371
372err_unreg_action:
373 of_clk_del_provider(node);
374err_clk_provider:
375 clk_unregister(rphy->clk480m);
376err_ret:
377 return ret;
378}
379
380static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
381{
382 int ret;
383 struct device_node *node = rphy->dev->of_node;
384 struct extcon_dev *edev;
385
386 if (of_property_read_bool(node, "extcon")) {
387 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
388 if (IS_ERR(edev)) {
389 if (PTR_ERR(edev) != -EPROBE_DEFER)
390 dev_err(rphy->dev, "Invalid or missing extcon\n");
391 return PTR_ERR(edev);
392 }
393 } else {
394 /* Initialize extcon device */
395 edev = devm_extcon_dev_allocate(rphy->dev,
396 rockchip_usb2phy_extcon_cable);
397
398 if (IS_ERR(edev))
399 return -ENOMEM;
400
401 ret = devm_extcon_dev_register(rphy->dev, edev);
402 if (ret) {
403 dev_err(rphy->dev, "failed to register extcon device\n");
404 return ret;
405 }
406 }
407
408 rphy->edev = edev;
409
410 return 0;
411}
412
413static int rockchip_usb2phy_init(struct phy *phy)
414{
415 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
416 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
417 int ret = 0;
418
419 mutex_lock(&rport->mutex);
420
421 if (rport->port_id == USB2PHY_PORT_OTG) {
422 if (rport->mode != USB_DR_MODE_HOST &&
423 rport->mode != USB_DR_MODE_UNKNOWN) {
424 /* clear bvalid status and enable bvalid detect irq */
425 ret = property_enable(rphy->grf,
426 &rport->port_cfg->bvalid_det_clr,
427 true);
428 if (ret)
429 goto out;
430
431 ret = property_enable(rphy->grf,
432 &rport->port_cfg->bvalid_det_en,
433 true);
434 if (ret)
435 goto out;
436
437 schedule_delayed_work(&rport->otg_sm_work,
438 OTG_SCHEDULE_DELAY * 3);
439 } else {
440 /* If OTG works in host only mode, do nothing. */
441 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
442 }
443 } else if (rport->port_id == USB2PHY_PORT_HOST) {
444 /* clear linestate and enable linestate detect irq */
445 ret = property_enable(rphy->grf,
446 &rport->port_cfg->ls_det_clr, true);
447 if (ret)
448 goto out;
449
450 ret = property_enable(rphy->grf,
451 &rport->port_cfg->ls_det_en, true);
452 if (ret)
453 goto out;
454
455 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
456 }
457
458out:
459 mutex_unlock(&rport->mutex);
460 return ret;
461}
462
463static int rockchip_usb2phy_power_on(struct phy *phy)
464{
465 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
466 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
467 struct regmap *base = get_reg_base(rphy);
468 int ret;
469
470 dev_dbg(&rport->phy->dev, "port power on\n");
471
472 if (!rport->suspended)
473 return 0;
474
475 ret = clk_prepare_enable(rphy->clk480m);
476 if (ret)
477 return ret;
478
479 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
480 if (ret)
481 return ret;
482
483 /* waiting for the utmi_clk to become stable */
484 usleep_range(1500, 2000);
485
486 rport->suspended = false;
487 return 0;
488}
489
490static int rockchip_usb2phy_power_off(struct phy *phy)
491{
492 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
493 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
494 struct regmap *base = get_reg_base(rphy);
495 int ret;
496
497 dev_dbg(&rport->phy->dev, "port power off\n");
498
499 if (rport->suspended)
500 return 0;
501
502 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
503 if (ret)
504 return ret;
505
506 rport->suspended = true;
507 clk_disable_unprepare(rphy->clk480m);
508
509 return 0;
510}
511
512static int rockchip_usb2phy_exit(struct phy *phy)
513{
514 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
515
516 if (rport->port_id == USB2PHY_PORT_OTG &&
517 rport->mode != USB_DR_MODE_HOST &&
518 rport->mode != USB_DR_MODE_UNKNOWN) {
519 cancel_delayed_work_sync(&rport->otg_sm_work);
520 cancel_delayed_work_sync(&rport->chg_work);
521 } else if (rport->port_id == USB2PHY_PORT_HOST)
522 cancel_delayed_work_sync(&rport->sm_work);
523
524 return 0;
525}
526
527static const struct phy_ops rockchip_usb2phy_ops = {
528 .init = rockchip_usb2phy_init,
529 .exit = rockchip_usb2phy_exit,
530 .power_on = rockchip_usb2phy_power_on,
531 .power_off = rockchip_usb2phy_power_off,
532 .owner = THIS_MODULE,
533};
534
535static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
536{
537 struct rockchip_usb2phy_port *rport =
538 container_of(work, struct rockchip_usb2phy_port,
539 otg_sm_work.work);
540 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
541 static unsigned int cable;
542 unsigned long delay;
543 bool vbus_attach, sch_work, notify_charger;
544
545 if (rport->utmi_avalid)
546 vbus_attach = property_enabled(rphy->grf,
547 &rport->port_cfg->utmi_avalid);
548 else
549 vbus_attach = property_enabled(rphy->grf,
550 &rport->port_cfg->utmi_bvalid);
551
552 sch_work = false;
553 notify_charger = false;
554 delay = OTG_SCHEDULE_DELAY;
555 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
556 usb_otg_state_string(rport->state));
557
558 switch (rport->state) {
559 case OTG_STATE_UNDEFINED:
560 rport->state = OTG_STATE_B_IDLE;
561 if (!vbus_attach)
562 rockchip_usb2phy_power_off(rport->phy);
563 /* fall through */
564 case OTG_STATE_B_IDLE:
565 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
566 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
567 rport->state = OTG_STATE_A_HOST;
568 rockchip_usb2phy_power_on(rport->phy);
569 return;
570 } else if (vbus_attach) {
571 dev_dbg(&rport->phy->dev, "vbus_attach\n");
572 switch (rphy->chg_state) {
573 case USB_CHG_STATE_UNDEFINED:
574 schedule_delayed_work(&rport->chg_work, 0);
575 return;
576 case USB_CHG_STATE_DETECTED:
577 switch (rphy->chg_type) {
578 case POWER_SUPPLY_TYPE_USB:
579 dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
580 rockchip_usb2phy_power_on(rport->phy);
581 rport->state = OTG_STATE_B_PERIPHERAL;
582 notify_charger = true;
583 sch_work = true;
584 cable = EXTCON_CHG_USB_SDP;
585 break;
586 case POWER_SUPPLY_TYPE_USB_DCP:
587 dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
588 rockchip_usb2phy_power_off(rport->phy);
589 notify_charger = true;
590 sch_work = true;
591 cable = EXTCON_CHG_USB_DCP;
592 break;
593 case POWER_SUPPLY_TYPE_USB_CDP:
594 dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
595 rockchip_usb2phy_power_on(rport->phy);
596 rport->state = OTG_STATE_B_PERIPHERAL;
597 notify_charger = true;
598 sch_work = true;
599 cable = EXTCON_CHG_USB_CDP;
600 break;
601 default:
602 break;
603 }
604 break;
605 default:
606 break;
607 }
608 } else {
609 notify_charger = true;
610 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
611 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
612 }
613
614 if (rport->vbus_attached != vbus_attach) {
615 rport->vbus_attached = vbus_attach;
616
617 if (notify_charger && rphy->edev) {
618 extcon_set_state_sync(rphy->edev,
619 cable, vbus_attach);
620 if (cable == EXTCON_CHG_USB_SDP)
621 extcon_set_state_sync(rphy->edev,
622 EXTCON_USB,
623 vbus_attach);
624 }
625 }
626 break;
627 case OTG_STATE_B_PERIPHERAL:
628 if (!vbus_attach) {
629 dev_dbg(&rport->phy->dev, "usb disconnect\n");
630 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
631 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
632 rport->state = OTG_STATE_B_IDLE;
633 delay = 0;
634 rockchip_usb2phy_power_off(rport->phy);
635 }
636 sch_work = true;
637 break;
638 case OTG_STATE_A_HOST:
639 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
640 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
641 rport->state = OTG_STATE_B_IDLE;
642 rockchip_usb2phy_power_off(rport->phy);
643 }
644 break;
645 default:
646 break;
647 }
648
649 if (sch_work)
650 schedule_delayed_work(&rport->otg_sm_work, delay);
651}
652
653static const char *chg_to_string(enum power_supply_type chg_type)
654{
655 switch (chg_type) {
656 case POWER_SUPPLY_TYPE_USB:
657 return "USB_SDP_CHARGER";
658 case POWER_SUPPLY_TYPE_USB_DCP:
659 return "USB_DCP_CHARGER";
660 case POWER_SUPPLY_TYPE_USB_CDP:
661 return "USB_CDP_CHARGER";
662 default:
663 return "INVALID_CHARGER";
664 }
665}
666
667static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
668 bool en)
669{
670 struct regmap *base = get_reg_base(rphy);
671
672 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
673 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
674}
675
676static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
677 bool en)
678{
679 struct regmap *base = get_reg_base(rphy);
680
681 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
682 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
683}
684
685static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
686 bool en)
687{
688 struct regmap *base = get_reg_base(rphy);
689
690 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
691 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
692}
693
694#define CHG_DCD_POLL_TIME (100 * HZ / 1000)
695#define CHG_DCD_MAX_RETRIES 6
696#define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
697#define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
698static void rockchip_chg_detect_work(struct work_struct *work)
699{
700 struct rockchip_usb2phy_port *rport =
701 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
702 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
703 struct regmap *base = get_reg_base(rphy);
704 bool is_dcd, tmout, vout;
705 unsigned long delay;
706
707 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
708 rphy->chg_state);
709 switch (rphy->chg_state) {
710 case USB_CHG_STATE_UNDEFINED:
711 if (!rport->suspended)
712 rockchip_usb2phy_power_off(rport->phy);
713 /* put the controller in non-driving mode */
714 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
715 /* Start DCD processing stage 1 */
716 rockchip_chg_enable_dcd(rphy, true);
717 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
718 rphy->dcd_retries = 0;
719 delay = CHG_DCD_POLL_TIME;
720 break;
721 case USB_CHG_STATE_WAIT_FOR_DCD:
722 /* get data contact detection status */
723 is_dcd = property_enabled(rphy->grf,
724 &rphy->phy_cfg->chg_det.dp_det);
725 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
726 /* stage 2 */
727 if (is_dcd || tmout) {
728 /* stage 4 */
729 /* Turn off DCD circuitry */
730 rockchip_chg_enable_dcd(rphy, false);
731 /* Voltage Source on DP, Probe on DM */
732 rockchip_chg_enable_primary_det(rphy, true);
733 delay = CHG_PRIMARY_DET_TIME;
734 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
735 } else {
736 /* stage 3 */
737 delay = CHG_DCD_POLL_TIME;
738 }
739 break;
740 case USB_CHG_STATE_DCD_DONE:
741 vout = property_enabled(rphy->grf,
742 &rphy->phy_cfg->chg_det.cp_det);
743 rockchip_chg_enable_primary_det(rphy, false);
744 if (vout) {
745 /* Voltage Source on DM, Probe on DP */
746 rockchip_chg_enable_secondary_det(rphy, true);
747 delay = CHG_SECONDARY_DET_TIME;
748 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
749 } else {
750 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
751 /* floating charger found */
752 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
753 rphy->chg_state = USB_CHG_STATE_DETECTED;
754 delay = 0;
755 } else {
756 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
757 rphy->chg_state = USB_CHG_STATE_DETECTED;
758 delay = 0;
759 }
760 }
761 break;
762 case USB_CHG_STATE_PRIMARY_DONE:
763 vout = property_enabled(rphy->grf,
764 &rphy->phy_cfg->chg_det.dcp_det);
765 /* Turn off voltage source */
766 rockchip_chg_enable_secondary_det(rphy, false);
767 if (vout)
768 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
769 else
770 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
771 /* fall through */
772 case USB_CHG_STATE_SECONDARY_DONE:
773 rphy->chg_state = USB_CHG_STATE_DETECTED;
774 delay = 0;
775 /* fall through */
776 case USB_CHG_STATE_DETECTED:
777 /* put the controller in normal mode */
778 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
779 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
780 dev_info(&rport->phy->dev, "charger = %s\n",
781 chg_to_string(rphy->chg_type));
782 return;
783 default:
784 return;
785 }
786
787 schedule_delayed_work(&rport->chg_work, delay);
788}
789
790/*
791 * The function manage host-phy port state and suspend/resume phy port
792 * to save power.
793 *
794 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
795 * devices is disconnect or not. Besides, we do not need care it is FS/LS
796 * disconnected or HS disconnected, actually, we just only need get the
797 * device is disconnected at last through rearm the delayed work,
798 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
799 *
800 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
801 * some clk related APIs, so do not invoke it from interrupt context directly.
802 */
803static void rockchip_usb2phy_sm_work(struct work_struct *work)
804{
805 struct rockchip_usb2phy_port *rport =
806 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
807 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
808 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
809 rport->port_cfg->utmi_hstdet.bitstart + 1;
810 unsigned int ul, uhd, state;
811 unsigned int ul_mask, uhd_mask;
812 int ret;
813
814 mutex_lock(&rport->mutex);
815
816 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
817 if (ret < 0)
818 goto next_schedule;
819
820 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
821 if (ret < 0)
822 goto next_schedule;
823
824 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
825 rport->port_cfg->utmi_hstdet.bitstart);
826 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
827 rport->port_cfg->utmi_ls.bitstart);
828
829 /* stitch on utmi_ls and utmi_hstdet as phy state */
830 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
831 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
832
833 switch (state) {
834 case PHY_STATE_HS_ONLINE:
835 dev_dbg(&rport->phy->dev, "HS online\n");
836 break;
837 case PHY_STATE_FS_LS_ONLINE:
838 /*
839 * For FS/LS device, the online state share with connect state
840 * from utmi_ls and utmi_hstdet register, so we distinguish
841 * them via suspended flag.
842 *
843 * Plus, there are two cases, one is D- Line pull-up, and D+
844 * line pull-down, the state is 4; another is D+ line pull-up,
845 * and D- line pull-down, the state is 2.
846 */
847 if (!rport->suspended) {
848 /* D- line pull-up, D+ line pull-down */
849 dev_dbg(&rport->phy->dev, "FS/LS online\n");
850 break;
851 }
852 /* fall through */
853 case PHY_STATE_CONNECT:
854 if (rport->suspended) {
855 dev_dbg(&rport->phy->dev, "Connected\n");
856 rockchip_usb2phy_power_on(rport->phy);
857 rport->suspended = false;
858 } else {
859 /* D+ line pull-up, D- line pull-down */
860 dev_dbg(&rport->phy->dev, "FS/LS online\n");
861 }
862 break;
863 case PHY_STATE_DISCONNECT:
864 if (!rport->suspended) {
865 dev_dbg(&rport->phy->dev, "Disconnected\n");
866 rockchip_usb2phy_power_off(rport->phy);
867 rport->suspended = true;
868 }
869
870 /*
871 * activate the linestate detection to get the next device
872 * plug-in irq.
873 */
874 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
875 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
876
877 /*
878 * we don't need to rearm the delayed work when the phy port
879 * is suspended.
880 */
881 mutex_unlock(&rport->mutex);
882 return;
883 default:
884 dev_dbg(&rport->phy->dev, "unknown phy state\n");
885 break;
886 }
887
888next_schedule:
889 mutex_unlock(&rport->mutex);
890 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
891}
892
893static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
894{
895 struct rockchip_usb2phy_port *rport = data;
896 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
897
898 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
899 return IRQ_NONE;
900
901 mutex_lock(&rport->mutex);
902
903 /* disable linestate detect irq and clear its status */
904 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
905 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
906
907 mutex_unlock(&rport->mutex);
908
909 /*
910 * In this case for host phy port, a new device is plugged in,
911 * meanwhile, if the phy port is suspended, we need rearm the work to
912 * resume it and mange its states; otherwise, we do nothing about that.
913 */
914 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
915 rockchip_usb2phy_sm_work(&rport->sm_work.work);
916
917 return IRQ_HANDLED;
918}
919
920static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
921{
922 struct rockchip_usb2phy_port *rport = data;
923 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
924
925 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
926 return IRQ_NONE;
927
928 mutex_lock(&rport->mutex);
929
930 /* clear bvalid detect irq pending status */
931 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
932
933 mutex_unlock(&rport->mutex);
934
935 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
936
937 return IRQ_HANDLED;
938}
939
940static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
941{
942 struct rockchip_usb2phy_port *rport = data;
943 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
944
945 if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
946 return rockchip_usb2phy_bvalid_irq(irq, data);
947 else
948 return IRQ_NONE;
949}
950
951static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
952 struct rockchip_usb2phy_port *rport,
953 struct device_node *child_np)
954{
955 int ret;
956
957 rport->port_id = USB2PHY_PORT_HOST;
958 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
959 rport->suspended = true;
960
961 mutex_init(&rport->mutex);
962 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
963
964 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
965 if (rport->ls_irq < 0) {
966 dev_err(rphy->dev, "no linestate irq provided\n");
967 return rport->ls_irq;
968 }
969
970 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
971 rockchip_usb2phy_linestate_irq,
972 IRQF_ONESHOT,
973 "rockchip_usb2phy", rport);
974 if (ret) {
975 dev_err(rphy->dev, "failed to request linestate irq handle\n");
976 return ret;
977 }
978
979 return 0;
980}
981
982static int rockchip_otg_event(struct notifier_block *nb,
983 unsigned long event, void *ptr)
984{
985 struct rockchip_usb2phy_port *rport =
986 container_of(nb, struct rockchip_usb2phy_port, event_nb);
987
988 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
989
990 return NOTIFY_DONE;
991}
992
993static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
994 struct rockchip_usb2phy_port *rport,
995 struct device_node *child_np)
996{
997 int ret;
998
999 rport->port_id = USB2PHY_PORT_OTG;
1000 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1001 rport->state = OTG_STATE_UNDEFINED;
1002
1003 /*
1004 * set suspended flag to true, but actually don't
1005 * put phy in suspend mode, it aims to enable usb
1006 * phy and clock in power_on() called by usb controller
1007 * driver during probe.
1008 */
1009 rport->suspended = true;
1010 rport->vbus_attached = false;
1011
1012 mutex_init(&rport->mutex);
1013
1014 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1015 if (rport->mode == USB_DR_MODE_HOST ||
1016 rport->mode == USB_DR_MODE_UNKNOWN) {
1017 ret = 0;
1018 goto out;
1019 }
1020
1021 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1022 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1023
1024 rport->utmi_avalid =
1025 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1026
1027 /*
1028 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1029 * interrupts muxed together, so probe the otg-mux interrupt first,
1030 * if not found, then look for the regular interrupts one by one.
1031 */
1032 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1033 if (rport->otg_mux_irq > 0) {
1034 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1035 NULL,
1036 rockchip_usb2phy_otg_mux_irq,
1037 IRQF_ONESHOT,
1038 "rockchip_usb2phy_otg",
1039 rport);
1040 if (ret) {
1041 dev_err(rphy->dev,
1042 "failed to request otg-mux irq handle\n");
1043 goto out;
1044 }
1045 } else {
1046 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1047 if (rport->bvalid_irq < 0) {
1048 dev_err(rphy->dev, "no vbus valid irq provided\n");
1049 ret = rport->bvalid_irq;
1050 goto out;
1051 }
1052
1053 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1054 NULL,
1055 rockchip_usb2phy_bvalid_irq,
1056 IRQF_ONESHOT,
1057 "rockchip_usb2phy_bvalid",
1058 rport);
1059 if (ret) {
1060 dev_err(rphy->dev,
1061 "failed to request otg-bvalid irq handle\n");
1062 goto out;
1063 }
1064 }
1065
1066 if (!IS_ERR(rphy->edev)) {
1067 rport->event_nb.notifier_call = rockchip_otg_event;
1068
1069 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1070 EXTCON_USB_HOST, &rport->event_nb);
1071 if (ret)
1072 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1073 }
1074
1075out:
1076 return ret;
1077}
1078
1079static int rockchip_usb2phy_probe(struct platform_device *pdev)
1080{
1081 struct device *dev = &pdev->dev;
1082 struct device_node *np = dev->of_node;
1083 struct device_node *child_np;
1084 struct phy_provider *provider;
1085 struct rockchip_usb2phy *rphy;
1086 const struct rockchip_usb2phy_cfg *phy_cfgs;
1087 const struct of_device_id *match;
1088 unsigned int reg;
1089 int index, ret;
1090
1091 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1092 if (!rphy)
1093 return -ENOMEM;
1094
1095 match = of_match_device(dev->driver->of_match_table, dev);
1096 if (!match || !match->data) {
1097 dev_err(dev, "phy configs are not assigned!\n");
1098 return -EINVAL;
1099 }
1100
1101 if (!dev->parent || !dev->parent->of_node)
1102 return -EINVAL;
1103
1104 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1105 if (IS_ERR(rphy->grf))
1106 return PTR_ERR(rphy->grf);
1107
1108 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1109 rphy->usbgrf =
1110 syscon_regmap_lookup_by_phandle(dev->of_node,
1111 "rockchip,usbgrf");
1112 if (IS_ERR(rphy->usbgrf))
1113 return PTR_ERR(rphy->usbgrf);
1114 } else {
1115 rphy->usbgrf = NULL;
1116 }
1117
1118 if (of_property_read_u32(np, "reg", ®)) {
1119 dev_err(dev, "the reg property is not assigned in %s node\n",
1120 np->name);
1121 return -EINVAL;
1122 }
1123
1124 rphy->dev = dev;
1125 phy_cfgs = match->data;
1126 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1127 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1128 platform_set_drvdata(pdev, rphy);
1129
1130 ret = rockchip_usb2phy_extcon_register(rphy);
1131 if (ret)
1132 return ret;
1133
1134 /* find out a proper config which can be matched with dt. */
1135 index = 0;
1136 while (phy_cfgs[index].reg) {
1137 if (phy_cfgs[index].reg == reg) {
1138 rphy->phy_cfg = &phy_cfgs[index];
1139 break;
1140 }
1141
1142 ++index;
1143 }
1144
1145 if (!rphy->phy_cfg) {
1146 dev_err(dev, "no phy-config can be matched with %s node\n",
1147 np->name);
1148 return -EINVAL;
1149 }
1150
1151 rphy->clk = of_clk_get_by_name(np, "phyclk");
1152 if (!IS_ERR(rphy->clk)) {
1153 clk_prepare_enable(rphy->clk);
1154 } else {
1155 dev_info(&pdev->dev, "no phyclk specified\n");
1156 rphy->clk = NULL;
1157 }
1158
1159 ret = rockchip_usb2phy_clk480m_register(rphy);
1160 if (ret) {
1161 dev_err(dev, "failed to register 480m output clock\n");
1162 goto disable_clks;
1163 }
1164
1165 index = 0;
1166 for_each_available_child_of_node(np, child_np) {
1167 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1168 struct phy *phy;
1169
1170 /* This driver aims to support both otg-port and host-port */
1171 if (of_node_cmp(child_np->name, "host-port") &&
1172 of_node_cmp(child_np->name, "otg-port"))
1173 goto next_child;
1174
1175 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1176 if (IS_ERR(phy)) {
1177 dev_err(dev, "failed to create phy\n");
1178 ret = PTR_ERR(phy);
1179 goto put_child;
1180 }
1181
1182 rport->phy = phy;
1183 phy_set_drvdata(rport->phy, rport);
1184
1185 /* initialize otg/host port separately */
1186 if (!of_node_cmp(child_np->name, "host-port")) {
1187 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1188 child_np);
1189 if (ret)
1190 goto put_child;
1191 } else {
1192 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1193 child_np);
1194 if (ret)
1195 goto put_child;
1196 }
1197
1198next_child:
1199 /* to prevent out of boundary */
1200 if (++index >= rphy->phy_cfg->num_ports)
1201 break;
1202 }
1203
1204 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1205 return PTR_ERR_OR_ZERO(provider);
1206
1207put_child:
1208 of_node_put(child_np);
1209disable_clks:
1210 if (rphy->clk) {
1211 clk_disable_unprepare(rphy->clk);
1212 clk_put(rphy->clk);
1213 }
1214 return ret;
1215}
1216
1217static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1218 {
1219 .reg = 0x760,
1220 .num_ports = 2,
1221 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1222 .port_cfgs = {
1223 [USB2PHY_PORT_OTG] = {
1224 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
1225 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1226 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1227 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1228 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1229 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1230 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1231 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1232 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1233 },
1234 [USB2PHY_PORT_HOST] = {
1235 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
1236 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1237 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1238 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1239 }
1240 },
1241 .chg_det = {
1242 .opmode = { 0x0760, 3, 0, 5, 1 },
1243 .cp_det = { 0x0884, 4, 4, 0, 1 },
1244 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1245 .dp_det = { 0x0884, 5, 5, 0, 1 },
1246 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1247 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1248 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1249 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1250 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1251 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1252 },
1253 },
1254 {
1255 .reg = 0x800,
1256 .num_ports = 2,
1257 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1258 .port_cfgs = {
1259 [USB2PHY_PORT_OTG] = {
1260 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
1261 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1262 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1263 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1264 },
1265 [USB2PHY_PORT_HOST] = {
1266 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
1267 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1268 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1269 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1270 }
1271 },
1272 },
1273 { /* sentinel */ }
1274};
1275
1276static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1277 {
1278 .reg = 0x100,
1279 .num_ports = 2,
1280 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1281 .port_cfgs = {
1282 [USB2PHY_PORT_OTG] = {
1283 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1284 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1285 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1286 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1287 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1288 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1289 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1290 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1291 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1292 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1293 },
1294 [USB2PHY_PORT_HOST] = {
1295 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
1296 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1297 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1298 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1299 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1300 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1301 }
1302 },
1303 .chg_det = {
1304 .opmode = { 0x0100, 3, 0, 5, 1 },
1305 .cp_det = { 0x0120, 24, 24, 0, 1 },
1306 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1307 .dp_det = { 0x0120, 25, 25, 0, 1 },
1308 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1309 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1310 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1311 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1312 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1313 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1314 },
1315 },
1316 { /* sentinel */ }
1317};
1318
1319static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1320 {
1321 .reg = 0x700,
1322 .num_ports = 2,
1323 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1324 .port_cfgs = {
1325 [USB2PHY_PORT_HOST] = {
1326 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1327 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1328 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1329 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1330 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1331 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1332 }
1333 },
1334 },
1335 { /* sentinel */ }
1336};
1337
1338static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1339 {
1340 .reg = 0xe450,
1341 .num_ports = 2,
1342 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1343 .port_cfgs = {
1344 [USB2PHY_PORT_OTG] = {
1345 .phy_sus = { 0xe454, 1, 0, 2, 1 },
1346 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1347 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1348 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1349 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1350 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1351 },
1352 [USB2PHY_PORT_HOST] = {
1353 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1354 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1355 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1356 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1357 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1358 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1359 }
1360 },
1361 .chg_det = {
1362 .opmode = { 0xe454, 3, 0, 5, 1 },
1363 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1364 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1365 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1366 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1367 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1368 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1369 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1370 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1371 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1372 },
1373 },
1374 {
1375 .reg = 0xe460,
1376 .num_ports = 2,
1377 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1378 .port_cfgs = {
1379 [USB2PHY_PORT_OTG] = {
1380 .phy_sus = { 0xe464, 1, 0, 2, 1 },
1381 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1382 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1383 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1384 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1385 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1386 },
1387 [USB2PHY_PORT_HOST] = {
1388 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1389 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1390 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1391 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1392 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1393 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1394 }
1395 },
1396 },
1397 { /* sentinel */ }
1398};
1399
1400static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1401 {
1402 .reg = 0x100,
1403 .num_ports = 2,
1404 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1405 .port_cfgs = {
1406 [USB2PHY_PORT_OTG] = {
1407 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1408 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1409 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1410 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1411 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1412 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1413 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1414 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
1415 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
1416 },
1417 [USB2PHY_PORT_HOST] = {
1418 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 },
1419 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1420 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1421 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1422 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
1423 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
1424 }
1425 },
1426 .chg_det = {
1427 .opmode = { 0x0100, 3, 0, 5, 1 },
1428 .cp_det = { 0x0804, 1, 1, 0, 1 },
1429 .dcp_det = { 0x0804, 0, 0, 0, 1 },
1430 .dp_det = { 0x0804, 2, 2, 0, 1 },
1431 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1432 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1433 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1434 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1435 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1436 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1437 },
1438 },
1439 { /* sentinel */ }
1440};
1441
1442static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1443 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1444 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1445 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1446 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1447 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
1448 {}
1449};
1450MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1451
1452static struct platform_driver rockchip_usb2phy_driver = {
1453 .probe = rockchip_usb2phy_probe,
1454 .driver = {
1455 .name = "rockchip-usb2phy",
1456 .of_match_table = rockchip_usb2phy_dt_match,
1457 },
1458};
1459module_platform_driver(rockchip_usb2phy_driver);
1460
1461MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1462MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1463MODULE_LICENSE("GPL v2");