Loading...
Note: File does not exist in v3.15.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm PCIe root complex driver
4 *
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
7 *
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
9 */
10
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/gpio.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/of_device.h>
20#include <linux/of_gpio.h>
21#include <linux/pci.h>
22#include <linux/platform_device.h>
23#include <linux/phy/phy.h>
24#include <linux/regulator/consumer.h>
25#include <linux/reset.h>
26#include <linux/slab.h>
27#include <linux/types.h>
28
29#include "pcie-designware.h"
30
31#define PCIE20_PARF_SYS_CTRL 0x00
32#define MST_WAKEUP_EN BIT(13)
33#define SLV_WAKEUP_EN BIT(12)
34#define MSTR_ACLK_CGC_DIS BIT(10)
35#define SLV_ACLK_CGC_DIS BIT(9)
36#define CORE_CLK_CGC_DIS BIT(6)
37#define AUX_PWR_DET BIT(4)
38#define L23_CLK_RMV_DIS BIT(2)
39#define L1_CLK_RMV_DIS BIT(1)
40
41#define PCIE20_COMMAND_STATUS 0x04
42#define CMD_BME_VAL 0x4
43#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
44#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
45
46#define PCIE20_PARF_PHY_CTRL 0x40
47#define PCIE20_PARF_PHY_REFCLK 0x4C
48#define PCIE20_PARF_DBI_BASE_ADDR 0x168
49#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
50#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
51#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
52#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
53#define PCIE20_PARF_LTSSM 0x1B0
54#define PCIE20_PARF_SID_OFFSET 0x234
55#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
56
57#define PCIE20_ELBI_SYS_CTRL 0x04
58#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
59
60#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
61#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
62#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
63#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
64#define CFG_BRIDGE_SB_INIT BIT(0)
65
66#define PCIE20_CAP 0x70
67#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
68#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
69#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
70#define PCIE_CAP_LINK1_VAL 0x2FD7F
71
72#define PCIE20_PARF_Q2A_FLUSH 0x1AC
73
74#define PCIE20_MISC_CONTROL_1_REG 0x8BC
75#define DBI_RO_WR_EN 1
76
77#define PERST_DELAY_US 1000
78
79#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
80#define SLV_ADDR_SPACE_SZ 0x10000000
81
82#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
83struct qcom_pcie_resources_2_1_0 {
84 struct clk *iface_clk;
85 struct clk *core_clk;
86 struct clk *phy_clk;
87 struct reset_control *pci_reset;
88 struct reset_control *axi_reset;
89 struct reset_control *ahb_reset;
90 struct reset_control *por_reset;
91 struct reset_control *phy_reset;
92 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
93};
94
95struct qcom_pcie_resources_1_0_0 {
96 struct clk *iface;
97 struct clk *aux;
98 struct clk *master_bus;
99 struct clk *slave_bus;
100 struct reset_control *core;
101 struct regulator *vdda;
102};
103
104#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
105struct qcom_pcie_resources_2_3_2 {
106 struct clk *aux_clk;
107 struct clk *master_clk;
108 struct clk *slave_clk;
109 struct clk *cfg_clk;
110 struct clk *pipe_clk;
111 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
112};
113
114struct qcom_pcie_resources_2_4_0 {
115 struct clk *aux_clk;
116 struct clk *master_clk;
117 struct clk *slave_clk;
118 struct reset_control *axi_m_reset;
119 struct reset_control *axi_s_reset;
120 struct reset_control *pipe_reset;
121 struct reset_control *axi_m_vmid_reset;
122 struct reset_control *axi_s_xpu_reset;
123 struct reset_control *parf_reset;
124 struct reset_control *phy_reset;
125 struct reset_control *axi_m_sticky_reset;
126 struct reset_control *pipe_sticky_reset;
127 struct reset_control *pwr_reset;
128 struct reset_control *ahb_reset;
129 struct reset_control *phy_ahb_reset;
130};
131
132struct qcom_pcie_resources_2_3_3 {
133 struct clk *iface;
134 struct clk *axi_m_clk;
135 struct clk *axi_s_clk;
136 struct clk *ahb_clk;
137 struct clk *aux_clk;
138 struct reset_control *rst[7];
139};
140
141union qcom_pcie_resources {
142 struct qcom_pcie_resources_1_0_0 v1_0_0;
143 struct qcom_pcie_resources_2_1_0 v2_1_0;
144 struct qcom_pcie_resources_2_3_2 v2_3_2;
145 struct qcom_pcie_resources_2_3_3 v2_3_3;
146 struct qcom_pcie_resources_2_4_0 v2_4_0;
147};
148
149struct qcom_pcie;
150
151struct qcom_pcie_ops {
152 int (*get_resources)(struct qcom_pcie *pcie);
153 int (*init)(struct qcom_pcie *pcie);
154 int (*post_init)(struct qcom_pcie *pcie);
155 void (*deinit)(struct qcom_pcie *pcie);
156 void (*post_deinit)(struct qcom_pcie *pcie);
157 void (*ltssm_enable)(struct qcom_pcie *pcie);
158};
159
160struct qcom_pcie {
161 struct dw_pcie *pci;
162 void __iomem *parf; /* DT parf */
163 void __iomem *elbi; /* DT elbi */
164 union qcom_pcie_resources res;
165 struct phy *phy;
166 struct gpio_desc *reset;
167 const struct qcom_pcie_ops *ops;
168};
169
170#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
171
172static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
173{
174 gpiod_set_value_cansleep(pcie->reset, 1);
175 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
176}
177
178static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
179{
180 gpiod_set_value_cansleep(pcie->reset, 0);
181 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
182}
183
184static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
185{
186 struct dw_pcie *pci = pcie->pci;
187
188 if (dw_pcie_link_up(pci))
189 return 0;
190
191 /* Enable Link Training state machine */
192 if (pcie->ops->ltssm_enable)
193 pcie->ops->ltssm_enable(pcie);
194
195 return dw_pcie_wait_for_link(pci);
196}
197
198static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
199{
200 u32 val;
201
202 /* enable link training */
203 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
204 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
205 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
206}
207
208static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
209{
210 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
211 struct dw_pcie *pci = pcie->pci;
212 struct device *dev = pci->dev;
213 int ret;
214
215 res->supplies[0].supply = "vdda";
216 res->supplies[1].supply = "vdda_phy";
217 res->supplies[2].supply = "vdda_refclk";
218 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
219 res->supplies);
220 if (ret)
221 return ret;
222
223 res->iface_clk = devm_clk_get(dev, "iface");
224 if (IS_ERR(res->iface_clk))
225 return PTR_ERR(res->iface_clk);
226
227 res->core_clk = devm_clk_get(dev, "core");
228 if (IS_ERR(res->core_clk))
229 return PTR_ERR(res->core_clk);
230
231 res->phy_clk = devm_clk_get(dev, "phy");
232 if (IS_ERR(res->phy_clk))
233 return PTR_ERR(res->phy_clk);
234
235 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
236 if (IS_ERR(res->pci_reset))
237 return PTR_ERR(res->pci_reset);
238
239 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
240 if (IS_ERR(res->axi_reset))
241 return PTR_ERR(res->axi_reset);
242
243 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
244 if (IS_ERR(res->ahb_reset))
245 return PTR_ERR(res->ahb_reset);
246
247 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
248 if (IS_ERR(res->por_reset))
249 return PTR_ERR(res->por_reset);
250
251 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
252 return PTR_ERR_OR_ZERO(res->phy_reset);
253}
254
255static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
256{
257 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
258
259 reset_control_assert(res->pci_reset);
260 reset_control_assert(res->axi_reset);
261 reset_control_assert(res->ahb_reset);
262 reset_control_assert(res->por_reset);
263 reset_control_assert(res->pci_reset);
264 clk_disable_unprepare(res->iface_clk);
265 clk_disable_unprepare(res->core_clk);
266 clk_disable_unprepare(res->phy_clk);
267 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
268}
269
270static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
271{
272 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
273 struct dw_pcie *pci = pcie->pci;
274 struct device *dev = pci->dev;
275 u32 val;
276 int ret;
277
278 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
279 if (ret < 0) {
280 dev_err(dev, "cannot enable regulators\n");
281 return ret;
282 }
283
284 ret = reset_control_assert(res->ahb_reset);
285 if (ret) {
286 dev_err(dev, "cannot assert ahb reset\n");
287 goto err_assert_ahb;
288 }
289
290 ret = clk_prepare_enable(res->iface_clk);
291 if (ret) {
292 dev_err(dev, "cannot prepare/enable iface clock\n");
293 goto err_assert_ahb;
294 }
295
296 ret = clk_prepare_enable(res->phy_clk);
297 if (ret) {
298 dev_err(dev, "cannot prepare/enable phy clock\n");
299 goto err_clk_phy;
300 }
301
302 ret = clk_prepare_enable(res->core_clk);
303 if (ret) {
304 dev_err(dev, "cannot prepare/enable core clock\n");
305 goto err_clk_core;
306 }
307
308 ret = reset_control_deassert(res->ahb_reset);
309 if (ret) {
310 dev_err(dev, "cannot deassert ahb reset\n");
311 goto err_deassert_ahb;
312 }
313
314 /* enable PCIe clocks and resets */
315 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
316 val &= ~BIT(0);
317 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
318
319 /* enable external reference clock */
320 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
321 val |= BIT(16);
322 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
323
324 ret = reset_control_deassert(res->phy_reset);
325 if (ret) {
326 dev_err(dev, "cannot deassert phy reset\n");
327 return ret;
328 }
329
330 ret = reset_control_deassert(res->pci_reset);
331 if (ret) {
332 dev_err(dev, "cannot deassert pci reset\n");
333 return ret;
334 }
335
336 ret = reset_control_deassert(res->por_reset);
337 if (ret) {
338 dev_err(dev, "cannot deassert por reset\n");
339 return ret;
340 }
341
342 ret = reset_control_deassert(res->axi_reset);
343 if (ret) {
344 dev_err(dev, "cannot deassert axi reset\n");
345 return ret;
346 }
347
348 /* wait for clock acquisition */
349 usleep_range(1000, 1500);
350
351
352 /* Set the Max TLP size to 2K, instead of using default of 4K */
353 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
354 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
355 writel(CFG_BRIDGE_SB_INIT,
356 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
357
358 return 0;
359
360err_deassert_ahb:
361 clk_disable_unprepare(res->core_clk);
362err_clk_core:
363 clk_disable_unprepare(res->phy_clk);
364err_clk_phy:
365 clk_disable_unprepare(res->iface_clk);
366err_assert_ahb:
367 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
368
369 return ret;
370}
371
372static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
373{
374 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
375 struct dw_pcie *pci = pcie->pci;
376 struct device *dev = pci->dev;
377
378 res->vdda = devm_regulator_get(dev, "vdda");
379 if (IS_ERR(res->vdda))
380 return PTR_ERR(res->vdda);
381
382 res->iface = devm_clk_get(dev, "iface");
383 if (IS_ERR(res->iface))
384 return PTR_ERR(res->iface);
385
386 res->aux = devm_clk_get(dev, "aux");
387 if (IS_ERR(res->aux))
388 return PTR_ERR(res->aux);
389
390 res->master_bus = devm_clk_get(dev, "master_bus");
391 if (IS_ERR(res->master_bus))
392 return PTR_ERR(res->master_bus);
393
394 res->slave_bus = devm_clk_get(dev, "slave_bus");
395 if (IS_ERR(res->slave_bus))
396 return PTR_ERR(res->slave_bus);
397
398 res->core = devm_reset_control_get_exclusive(dev, "core");
399 return PTR_ERR_OR_ZERO(res->core);
400}
401
402static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
403{
404 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
405
406 reset_control_assert(res->core);
407 clk_disable_unprepare(res->slave_bus);
408 clk_disable_unprepare(res->master_bus);
409 clk_disable_unprepare(res->iface);
410 clk_disable_unprepare(res->aux);
411 regulator_disable(res->vdda);
412}
413
414static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
415{
416 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
417 struct dw_pcie *pci = pcie->pci;
418 struct device *dev = pci->dev;
419 int ret;
420
421 ret = reset_control_deassert(res->core);
422 if (ret) {
423 dev_err(dev, "cannot deassert core reset\n");
424 return ret;
425 }
426
427 ret = clk_prepare_enable(res->aux);
428 if (ret) {
429 dev_err(dev, "cannot prepare/enable aux clock\n");
430 goto err_res;
431 }
432
433 ret = clk_prepare_enable(res->iface);
434 if (ret) {
435 dev_err(dev, "cannot prepare/enable iface clock\n");
436 goto err_aux;
437 }
438
439 ret = clk_prepare_enable(res->master_bus);
440 if (ret) {
441 dev_err(dev, "cannot prepare/enable master_bus clock\n");
442 goto err_iface;
443 }
444
445 ret = clk_prepare_enable(res->slave_bus);
446 if (ret) {
447 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
448 goto err_master;
449 }
450
451 ret = regulator_enable(res->vdda);
452 if (ret) {
453 dev_err(dev, "cannot enable vdda regulator\n");
454 goto err_slave;
455 }
456
457 /* change DBI base address */
458 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
459
460 if (IS_ENABLED(CONFIG_PCI_MSI)) {
461 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
462
463 val |= BIT(31);
464 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
465 }
466
467 return 0;
468err_slave:
469 clk_disable_unprepare(res->slave_bus);
470err_master:
471 clk_disable_unprepare(res->master_bus);
472err_iface:
473 clk_disable_unprepare(res->iface);
474err_aux:
475 clk_disable_unprepare(res->aux);
476err_res:
477 reset_control_assert(res->core);
478
479 return ret;
480}
481
482static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
483{
484 u32 val;
485
486 /* enable link training */
487 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
488 val |= BIT(8);
489 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
490}
491
492static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
493{
494 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
495 struct dw_pcie *pci = pcie->pci;
496 struct device *dev = pci->dev;
497 int ret;
498
499 res->supplies[0].supply = "vdda";
500 res->supplies[1].supply = "vddpe-3v3";
501 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
502 res->supplies);
503 if (ret)
504 return ret;
505
506 res->aux_clk = devm_clk_get(dev, "aux");
507 if (IS_ERR(res->aux_clk))
508 return PTR_ERR(res->aux_clk);
509
510 res->cfg_clk = devm_clk_get(dev, "cfg");
511 if (IS_ERR(res->cfg_clk))
512 return PTR_ERR(res->cfg_clk);
513
514 res->master_clk = devm_clk_get(dev, "bus_master");
515 if (IS_ERR(res->master_clk))
516 return PTR_ERR(res->master_clk);
517
518 res->slave_clk = devm_clk_get(dev, "bus_slave");
519 if (IS_ERR(res->slave_clk))
520 return PTR_ERR(res->slave_clk);
521
522 res->pipe_clk = devm_clk_get(dev, "pipe");
523 return PTR_ERR_OR_ZERO(res->pipe_clk);
524}
525
526static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
527{
528 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
529
530 clk_disable_unprepare(res->slave_clk);
531 clk_disable_unprepare(res->master_clk);
532 clk_disable_unprepare(res->cfg_clk);
533 clk_disable_unprepare(res->aux_clk);
534
535 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
536}
537
538static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
539{
540 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
541
542 clk_disable_unprepare(res->pipe_clk);
543}
544
545static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
546{
547 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
548 struct dw_pcie *pci = pcie->pci;
549 struct device *dev = pci->dev;
550 u32 val;
551 int ret;
552
553 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
554 if (ret < 0) {
555 dev_err(dev, "cannot enable regulators\n");
556 return ret;
557 }
558
559 ret = clk_prepare_enable(res->aux_clk);
560 if (ret) {
561 dev_err(dev, "cannot prepare/enable aux clock\n");
562 goto err_aux_clk;
563 }
564
565 ret = clk_prepare_enable(res->cfg_clk);
566 if (ret) {
567 dev_err(dev, "cannot prepare/enable cfg clock\n");
568 goto err_cfg_clk;
569 }
570
571 ret = clk_prepare_enable(res->master_clk);
572 if (ret) {
573 dev_err(dev, "cannot prepare/enable master clock\n");
574 goto err_master_clk;
575 }
576
577 ret = clk_prepare_enable(res->slave_clk);
578 if (ret) {
579 dev_err(dev, "cannot prepare/enable slave clock\n");
580 goto err_slave_clk;
581 }
582
583 /* enable PCIe clocks and resets */
584 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
585 val &= ~BIT(0);
586 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
587
588 /* change DBI base address */
589 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
590
591 /* MAC PHY_POWERDOWN MUX DISABLE */
592 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
593 val &= ~BIT(29);
594 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
595
596 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
597 val |= BIT(4);
598 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
599
600 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
601 val |= BIT(31);
602 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
603
604 return 0;
605
606err_slave_clk:
607 clk_disable_unprepare(res->master_clk);
608err_master_clk:
609 clk_disable_unprepare(res->cfg_clk);
610err_cfg_clk:
611 clk_disable_unprepare(res->aux_clk);
612
613err_aux_clk:
614 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
615
616 return ret;
617}
618
619static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
620{
621 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
622 struct dw_pcie *pci = pcie->pci;
623 struct device *dev = pci->dev;
624 int ret;
625
626 ret = clk_prepare_enable(res->pipe_clk);
627 if (ret) {
628 dev_err(dev, "cannot prepare/enable pipe clock\n");
629 return ret;
630 }
631
632 return 0;
633}
634
635static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
636{
637 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
638 struct dw_pcie *pci = pcie->pci;
639 struct device *dev = pci->dev;
640
641 res->aux_clk = devm_clk_get(dev, "aux");
642 if (IS_ERR(res->aux_clk))
643 return PTR_ERR(res->aux_clk);
644
645 res->master_clk = devm_clk_get(dev, "master_bus");
646 if (IS_ERR(res->master_clk))
647 return PTR_ERR(res->master_clk);
648
649 res->slave_clk = devm_clk_get(dev, "slave_bus");
650 if (IS_ERR(res->slave_clk))
651 return PTR_ERR(res->slave_clk);
652
653 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
654 if (IS_ERR(res->axi_m_reset))
655 return PTR_ERR(res->axi_m_reset);
656
657 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
658 if (IS_ERR(res->axi_s_reset))
659 return PTR_ERR(res->axi_s_reset);
660
661 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
662 if (IS_ERR(res->pipe_reset))
663 return PTR_ERR(res->pipe_reset);
664
665 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
666 "axi_m_vmid");
667 if (IS_ERR(res->axi_m_vmid_reset))
668 return PTR_ERR(res->axi_m_vmid_reset);
669
670 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
671 "axi_s_xpu");
672 if (IS_ERR(res->axi_s_xpu_reset))
673 return PTR_ERR(res->axi_s_xpu_reset);
674
675 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
676 if (IS_ERR(res->parf_reset))
677 return PTR_ERR(res->parf_reset);
678
679 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
680 if (IS_ERR(res->phy_reset))
681 return PTR_ERR(res->phy_reset);
682
683 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
684 "axi_m_sticky");
685 if (IS_ERR(res->axi_m_sticky_reset))
686 return PTR_ERR(res->axi_m_sticky_reset);
687
688 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
689 "pipe_sticky");
690 if (IS_ERR(res->pipe_sticky_reset))
691 return PTR_ERR(res->pipe_sticky_reset);
692
693 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
694 if (IS_ERR(res->pwr_reset))
695 return PTR_ERR(res->pwr_reset);
696
697 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
698 if (IS_ERR(res->ahb_reset))
699 return PTR_ERR(res->ahb_reset);
700
701 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
702 if (IS_ERR(res->phy_ahb_reset))
703 return PTR_ERR(res->phy_ahb_reset);
704
705 return 0;
706}
707
708static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
709{
710 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
711
712 reset_control_assert(res->axi_m_reset);
713 reset_control_assert(res->axi_s_reset);
714 reset_control_assert(res->pipe_reset);
715 reset_control_assert(res->pipe_sticky_reset);
716 reset_control_assert(res->phy_reset);
717 reset_control_assert(res->phy_ahb_reset);
718 reset_control_assert(res->axi_m_sticky_reset);
719 reset_control_assert(res->pwr_reset);
720 reset_control_assert(res->ahb_reset);
721 clk_disable_unprepare(res->aux_clk);
722 clk_disable_unprepare(res->master_clk);
723 clk_disable_unprepare(res->slave_clk);
724}
725
726static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
727{
728 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
729 struct dw_pcie *pci = pcie->pci;
730 struct device *dev = pci->dev;
731 u32 val;
732 int ret;
733
734 ret = reset_control_assert(res->axi_m_reset);
735 if (ret) {
736 dev_err(dev, "cannot assert axi master reset\n");
737 return ret;
738 }
739
740 ret = reset_control_assert(res->axi_s_reset);
741 if (ret) {
742 dev_err(dev, "cannot assert axi slave reset\n");
743 return ret;
744 }
745
746 usleep_range(10000, 12000);
747
748 ret = reset_control_assert(res->pipe_reset);
749 if (ret) {
750 dev_err(dev, "cannot assert pipe reset\n");
751 return ret;
752 }
753
754 ret = reset_control_assert(res->pipe_sticky_reset);
755 if (ret) {
756 dev_err(dev, "cannot assert pipe sticky reset\n");
757 return ret;
758 }
759
760 ret = reset_control_assert(res->phy_reset);
761 if (ret) {
762 dev_err(dev, "cannot assert phy reset\n");
763 return ret;
764 }
765
766 ret = reset_control_assert(res->phy_ahb_reset);
767 if (ret) {
768 dev_err(dev, "cannot assert phy ahb reset\n");
769 return ret;
770 }
771
772 usleep_range(10000, 12000);
773
774 ret = reset_control_assert(res->axi_m_sticky_reset);
775 if (ret) {
776 dev_err(dev, "cannot assert axi master sticky reset\n");
777 return ret;
778 }
779
780 ret = reset_control_assert(res->pwr_reset);
781 if (ret) {
782 dev_err(dev, "cannot assert power reset\n");
783 return ret;
784 }
785
786 ret = reset_control_assert(res->ahb_reset);
787 if (ret) {
788 dev_err(dev, "cannot assert ahb reset\n");
789 return ret;
790 }
791
792 usleep_range(10000, 12000);
793
794 ret = reset_control_deassert(res->phy_ahb_reset);
795 if (ret) {
796 dev_err(dev, "cannot deassert phy ahb reset\n");
797 return ret;
798 }
799
800 ret = reset_control_deassert(res->phy_reset);
801 if (ret) {
802 dev_err(dev, "cannot deassert phy reset\n");
803 goto err_rst_phy;
804 }
805
806 ret = reset_control_deassert(res->pipe_reset);
807 if (ret) {
808 dev_err(dev, "cannot deassert pipe reset\n");
809 goto err_rst_pipe;
810 }
811
812 ret = reset_control_deassert(res->pipe_sticky_reset);
813 if (ret) {
814 dev_err(dev, "cannot deassert pipe sticky reset\n");
815 goto err_rst_pipe_sticky;
816 }
817
818 usleep_range(10000, 12000);
819
820 ret = reset_control_deassert(res->axi_m_reset);
821 if (ret) {
822 dev_err(dev, "cannot deassert axi master reset\n");
823 goto err_rst_axi_m;
824 }
825
826 ret = reset_control_deassert(res->axi_m_sticky_reset);
827 if (ret) {
828 dev_err(dev, "cannot deassert axi master sticky reset\n");
829 goto err_rst_axi_m_sticky;
830 }
831
832 ret = reset_control_deassert(res->axi_s_reset);
833 if (ret) {
834 dev_err(dev, "cannot deassert axi slave reset\n");
835 goto err_rst_axi_s;
836 }
837
838 ret = reset_control_deassert(res->pwr_reset);
839 if (ret) {
840 dev_err(dev, "cannot deassert power reset\n");
841 goto err_rst_pwr;
842 }
843
844 ret = reset_control_deassert(res->ahb_reset);
845 if (ret) {
846 dev_err(dev, "cannot deassert ahb reset\n");
847 goto err_rst_ahb;
848 }
849
850 usleep_range(10000, 12000);
851
852 ret = clk_prepare_enable(res->aux_clk);
853 if (ret) {
854 dev_err(dev, "cannot prepare/enable iface clock\n");
855 goto err_clk_aux;
856 }
857
858 ret = clk_prepare_enable(res->master_clk);
859 if (ret) {
860 dev_err(dev, "cannot prepare/enable core clock\n");
861 goto err_clk_axi_m;
862 }
863
864 ret = clk_prepare_enable(res->slave_clk);
865 if (ret) {
866 dev_err(dev, "cannot prepare/enable phy clock\n");
867 goto err_clk_axi_s;
868 }
869
870 /* enable PCIe clocks and resets */
871 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
872 val &= !BIT(0);
873 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
874
875 /* change DBI base address */
876 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
877
878 /* MAC PHY_POWERDOWN MUX DISABLE */
879 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
880 val &= ~BIT(29);
881 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
882
883 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
884 val |= BIT(4);
885 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
886
887 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
888 val |= BIT(31);
889 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
890
891 return 0;
892
893err_clk_axi_s:
894 clk_disable_unprepare(res->master_clk);
895err_clk_axi_m:
896 clk_disable_unprepare(res->aux_clk);
897err_clk_aux:
898 reset_control_assert(res->ahb_reset);
899err_rst_ahb:
900 reset_control_assert(res->pwr_reset);
901err_rst_pwr:
902 reset_control_assert(res->axi_s_reset);
903err_rst_axi_s:
904 reset_control_assert(res->axi_m_sticky_reset);
905err_rst_axi_m_sticky:
906 reset_control_assert(res->axi_m_reset);
907err_rst_axi_m:
908 reset_control_assert(res->pipe_sticky_reset);
909err_rst_pipe_sticky:
910 reset_control_assert(res->pipe_reset);
911err_rst_pipe:
912 reset_control_assert(res->phy_reset);
913err_rst_phy:
914 reset_control_assert(res->phy_ahb_reset);
915 return ret;
916}
917
918static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
919{
920 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
921 struct dw_pcie *pci = pcie->pci;
922 struct device *dev = pci->dev;
923 int i;
924 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
925 "axi_m_sticky", "sticky",
926 "ahb", "sleep", };
927
928 res->iface = devm_clk_get(dev, "iface");
929 if (IS_ERR(res->iface))
930 return PTR_ERR(res->iface);
931
932 res->axi_m_clk = devm_clk_get(dev, "axi_m");
933 if (IS_ERR(res->axi_m_clk))
934 return PTR_ERR(res->axi_m_clk);
935
936 res->axi_s_clk = devm_clk_get(dev, "axi_s");
937 if (IS_ERR(res->axi_s_clk))
938 return PTR_ERR(res->axi_s_clk);
939
940 res->ahb_clk = devm_clk_get(dev, "ahb");
941 if (IS_ERR(res->ahb_clk))
942 return PTR_ERR(res->ahb_clk);
943
944 res->aux_clk = devm_clk_get(dev, "aux");
945 if (IS_ERR(res->aux_clk))
946 return PTR_ERR(res->aux_clk);
947
948 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
949 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
950 if (IS_ERR(res->rst[i]))
951 return PTR_ERR(res->rst[i]);
952 }
953
954 return 0;
955}
956
957static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
958{
959 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
960
961 clk_disable_unprepare(res->iface);
962 clk_disable_unprepare(res->axi_m_clk);
963 clk_disable_unprepare(res->axi_s_clk);
964 clk_disable_unprepare(res->ahb_clk);
965 clk_disable_unprepare(res->aux_clk);
966}
967
968static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
969{
970 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
971 struct dw_pcie *pci = pcie->pci;
972 struct device *dev = pci->dev;
973 int i, ret;
974 u32 val;
975
976 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
977 ret = reset_control_assert(res->rst[i]);
978 if (ret) {
979 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
980 return ret;
981 }
982 }
983
984 usleep_range(2000, 2500);
985
986 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
987 ret = reset_control_deassert(res->rst[i]);
988 if (ret) {
989 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
990 ret);
991 return ret;
992 }
993 }
994
995 /*
996 * Don't have a way to see if the reset has completed.
997 * Wait for some time.
998 */
999 usleep_range(2000, 2500);
1000
1001 ret = clk_prepare_enable(res->iface);
1002 if (ret) {
1003 dev_err(dev, "cannot prepare/enable core clock\n");
1004 goto err_clk_iface;
1005 }
1006
1007 ret = clk_prepare_enable(res->axi_m_clk);
1008 if (ret) {
1009 dev_err(dev, "cannot prepare/enable core clock\n");
1010 goto err_clk_axi_m;
1011 }
1012
1013 ret = clk_prepare_enable(res->axi_s_clk);
1014 if (ret) {
1015 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1016 goto err_clk_axi_s;
1017 }
1018
1019 ret = clk_prepare_enable(res->ahb_clk);
1020 if (ret) {
1021 dev_err(dev, "cannot prepare/enable ahb clock\n");
1022 goto err_clk_ahb;
1023 }
1024
1025 ret = clk_prepare_enable(res->aux_clk);
1026 if (ret) {
1027 dev_err(dev, "cannot prepare/enable aux clock\n");
1028 goto err_clk_aux;
1029 }
1030
1031 writel(SLV_ADDR_SPACE_SZ,
1032 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1033
1034 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1035 val &= ~BIT(0);
1036 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1037
1038 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1039
1040 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1041 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1042 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1043 pcie->parf + PCIE20_PARF_SYS_CTRL);
1044 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1045
1046 writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
1047 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1048 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
1049
1050 val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1051 val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
1052 writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1053
1054 writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
1055 PCIE20_DEVICE_CONTROL2_STATUS2);
1056
1057 return 0;
1058
1059err_clk_aux:
1060 clk_disable_unprepare(res->ahb_clk);
1061err_clk_ahb:
1062 clk_disable_unprepare(res->axi_s_clk);
1063err_clk_axi_s:
1064 clk_disable_unprepare(res->axi_m_clk);
1065err_clk_axi_m:
1066 clk_disable_unprepare(res->iface);
1067err_clk_iface:
1068 /*
1069 * Not checking for failure, will anyway return
1070 * the original failure in 'ret'.
1071 */
1072 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1073 reset_control_assert(res->rst[i]);
1074
1075 return ret;
1076}
1077
1078static int qcom_pcie_link_up(struct dw_pcie *pci)
1079{
1080 u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
1081
1082 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1083}
1084
1085static int qcom_pcie_host_init(struct pcie_port *pp)
1086{
1087 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1088 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1089 int ret;
1090
1091 qcom_ep_reset_assert(pcie);
1092
1093 ret = pcie->ops->init(pcie);
1094 if (ret)
1095 return ret;
1096
1097 ret = phy_power_on(pcie->phy);
1098 if (ret)
1099 goto err_deinit;
1100
1101 if (pcie->ops->post_init) {
1102 ret = pcie->ops->post_init(pcie);
1103 if (ret)
1104 goto err_disable_phy;
1105 }
1106
1107 dw_pcie_setup_rc(pp);
1108
1109 if (IS_ENABLED(CONFIG_PCI_MSI))
1110 dw_pcie_msi_init(pp);
1111
1112 qcom_ep_reset_deassert(pcie);
1113
1114 ret = qcom_pcie_establish_link(pcie);
1115 if (ret)
1116 goto err;
1117
1118 return 0;
1119err:
1120 qcom_ep_reset_assert(pcie);
1121 if (pcie->ops->post_deinit)
1122 pcie->ops->post_deinit(pcie);
1123err_disable_phy:
1124 phy_power_off(pcie->phy);
1125err_deinit:
1126 pcie->ops->deinit(pcie);
1127
1128 return ret;
1129}
1130
1131static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
1132 u32 *val)
1133{
1134 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1135
1136 /* the device class is not reported correctly from the register */
1137 if (where == PCI_CLASS_REVISION && size == 4) {
1138 *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
1139 *val &= 0xff; /* keep revision id */
1140 *val |= PCI_CLASS_BRIDGE_PCI << 16;
1141 return PCIBIOS_SUCCESSFUL;
1142 }
1143
1144 return dw_pcie_read(pci->dbi_base + where, size, val);
1145}
1146
1147static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1148 .host_init = qcom_pcie_host_init,
1149 .rd_own_conf = qcom_pcie_rd_own_conf,
1150};
1151
1152/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1153static const struct qcom_pcie_ops ops_2_1_0 = {
1154 .get_resources = qcom_pcie_get_resources_2_1_0,
1155 .init = qcom_pcie_init_2_1_0,
1156 .deinit = qcom_pcie_deinit_2_1_0,
1157 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1158};
1159
1160/* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1161static const struct qcom_pcie_ops ops_1_0_0 = {
1162 .get_resources = qcom_pcie_get_resources_1_0_0,
1163 .init = qcom_pcie_init_1_0_0,
1164 .deinit = qcom_pcie_deinit_1_0_0,
1165 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1166};
1167
1168/* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1169static const struct qcom_pcie_ops ops_2_3_2 = {
1170 .get_resources = qcom_pcie_get_resources_2_3_2,
1171 .init = qcom_pcie_init_2_3_2,
1172 .post_init = qcom_pcie_post_init_2_3_2,
1173 .deinit = qcom_pcie_deinit_2_3_2,
1174 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1175 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1176};
1177
1178/* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1179static const struct qcom_pcie_ops ops_2_4_0 = {
1180 .get_resources = qcom_pcie_get_resources_2_4_0,
1181 .init = qcom_pcie_init_2_4_0,
1182 .deinit = qcom_pcie_deinit_2_4_0,
1183 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1184};
1185
1186/* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1187static const struct qcom_pcie_ops ops_2_3_3 = {
1188 .get_resources = qcom_pcie_get_resources_2_3_3,
1189 .init = qcom_pcie_init_2_3_3,
1190 .deinit = qcom_pcie_deinit_2_3_3,
1191 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1192};
1193
1194static const struct dw_pcie_ops dw_pcie_ops = {
1195 .link_up = qcom_pcie_link_up,
1196};
1197
1198static int qcom_pcie_probe(struct platform_device *pdev)
1199{
1200 struct device *dev = &pdev->dev;
1201 struct resource *res;
1202 struct pcie_port *pp;
1203 struct dw_pcie *pci;
1204 struct qcom_pcie *pcie;
1205 int ret;
1206
1207 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1208 if (!pcie)
1209 return -ENOMEM;
1210
1211 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1212 if (!pci)
1213 return -ENOMEM;
1214
1215 pci->dev = dev;
1216 pci->ops = &dw_pcie_ops;
1217 pp = &pci->pp;
1218
1219 pcie->pci = pci;
1220
1221 pcie->ops = of_device_get_match_data(dev);
1222
1223 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
1224 if (IS_ERR(pcie->reset))
1225 return PTR_ERR(pcie->reset);
1226
1227 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
1228 pcie->parf = devm_ioremap_resource(dev, res);
1229 if (IS_ERR(pcie->parf))
1230 return PTR_ERR(pcie->parf);
1231
1232 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1233 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
1234 if (IS_ERR(pci->dbi_base))
1235 return PTR_ERR(pci->dbi_base);
1236
1237 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
1238 pcie->elbi = devm_ioremap_resource(dev, res);
1239 if (IS_ERR(pcie->elbi))
1240 return PTR_ERR(pcie->elbi);
1241
1242 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1243 if (IS_ERR(pcie->phy))
1244 return PTR_ERR(pcie->phy);
1245
1246 ret = pcie->ops->get_resources(pcie);
1247 if (ret)
1248 return ret;
1249
1250 pp->root_bus_nr = -1;
1251 pp->ops = &qcom_pcie_dw_ops;
1252
1253 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1254 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
1255 if (pp->msi_irq < 0)
1256 return pp->msi_irq;
1257 }
1258
1259 ret = phy_init(pcie->phy);
1260 if (ret)
1261 return ret;
1262
1263 platform_set_drvdata(pdev, pcie);
1264
1265 ret = dw_pcie_host_init(pp);
1266 if (ret) {
1267 dev_err(dev, "cannot initialize host\n");
1268 return ret;
1269 }
1270
1271 return 0;
1272}
1273
1274static const struct of_device_id qcom_pcie_match[] = {
1275 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1276 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1277 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1278 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1279 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1280 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1281 { }
1282};
1283
1284static struct platform_driver qcom_pcie_driver = {
1285 .probe = qcom_pcie_probe,
1286 .driver = {
1287 .name = "qcom-pcie",
1288 .suppress_bind_attrs = true,
1289 .of_match_table = qcom_pcie_match,
1290 },
1291};
1292builtin_platform_driver(qcom_pcie_driver);