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1// SPDX-License-Identifier: GPL-2.0
2/* Intel(R) Gigabit Ethernet Linux driver
3 * Copyright(c) 2007-2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, see <http://www.gnu.org/licenses/>.
16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 *
20 * Contact Information:
21 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 */
24
25#include <linux/if_ether.h>
26#include <linux/delay.h>
27
28#include "e1000_mac.h"
29#include "e1000_phy.h"
30
31static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
32static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
33 u16 *phy_ctrl);
34static s32 igb_wait_autoneg(struct e1000_hw *hw);
35static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
36
37/* Cable length tables */
38static const u16 e1000_m88_cable_length_table[] = {
39 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
40
41static const u16 e1000_igp_2_cable_length_table[] = {
42 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
43 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
44 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
45 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
46 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
47 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
48 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
49 104, 109, 114, 118, 121, 124};
50
51/**
52 * igb_check_reset_block - Check if PHY reset is blocked
53 * @hw: pointer to the HW structure
54 *
55 * Read the PHY management control register and check whether a PHY reset
56 * is blocked. If a reset is not blocked return 0, otherwise
57 * return E1000_BLK_PHY_RESET (12).
58 **/
59s32 igb_check_reset_block(struct e1000_hw *hw)
60{
61 u32 manc;
62
63 manc = rd32(E1000_MANC);
64
65 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
66}
67
68/**
69 * igb_get_phy_id - Retrieve the PHY ID and revision
70 * @hw: pointer to the HW structure
71 *
72 * Reads the PHY registers and stores the PHY ID and possibly the PHY
73 * revision in the hardware structure.
74 **/
75s32 igb_get_phy_id(struct e1000_hw *hw)
76{
77 struct e1000_phy_info *phy = &hw->phy;
78 s32 ret_val = 0;
79 u16 phy_id;
80
81 /* ensure PHY page selection to fix misconfigured i210 */
82 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
83 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
84
85 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
86 if (ret_val)
87 goto out;
88
89 phy->id = (u32)(phy_id << 16);
90 udelay(20);
91 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
92 if (ret_val)
93 goto out;
94
95 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
96 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
97
98out:
99 return ret_val;
100}
101
102/**
103 * igb_phy_reset_dsp - Reset PHY DSP
104 * @hw: pointer to the HW structure
105 *
106 * Reset the digital signal processor.
107 **/
108static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
109{
110 s32 ret_val = 0;
111
112 if (!(hw->phy.ops.write_reg))
113 goto out;
114
115 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
116 if (ret_val)
117 goto out;
118
119 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
120
121out:
122 return ret_val;
123}
124
125/**
126 * igb_read_phy_reg_mdic - Read MDI control register
127 * @hw: pointer to the HW structure
128 * @offset: register offset to be read
129 * @data: pointer to the read data
130 *
131 * Reads the MDI control register in the PHY at offset and stores the
132 * information read to data.
133 **/
134s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
135{
136 struct e1000_phy_info *phy = &hw->phy;
137 u32 i, mdic = 0;
138 s32 ret_val = 0;
139
140 if (offset > MAX_PHY_REG_ADDRESS) {
141 hw_dbg("PHY Address %d is out of range\n", offset);
142 ret_val = -E1000_ERR_PARAM;
143 goto out;
144 }
145
146 /* Set up Op-code, Phy Address, and register offset in the MDI
147 * Control register. The MAC will take care of interfacing with the
148 * PHY to retrieve the desired data.
149 */
150 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
151 (phy->addr << E1000_MDIC_PHY_SHIFT) |
152 (E1000_MDIC_OP_READ));
153
154 wr32(E1000_MDIC, mdic);
155
156 /* Poll the ready bit to see if the MDI read completed
157 * Increasing the time out as testing showed failures with
158 * the lower time out
159 */
160 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
161 udelay(50);
162 mdic = rd32(E1000_MDIC);
163 if (mdic & E1000_MDIC_READY)
164 break;
165 }
166 if (!(mdic & E1000_MDIC_READY)) {
167 hw_dbg("MDI Read did not complete\n");
168 ret_val = -E1000_ERR_PHY;
169 goto out;
170 }
171 if (mdic & E1000_MDIC_ERROR) {
172 hw_dbg("MDI Error\n");
173 ret_val = -E1000_ERR_PHY;
174 goto out;
175 }
176 *data = (u16) mdic;
177
178out:
179 return ret_val;
180}
181
182/**
183 * igb_write_phy_reg_mdic - Write MDI control register
184 * @hw: pointer to the HW structure
185 * @offset: register offset to write to
186 * @data: data to write to register at offset
187 *
188 * Writes data to MDI control register in the PHY at offset.
189 **/
190s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
191{
192 struct e1000_phy_info *phy = &hw->phy;
193 u32 i, mdic = 0;
194 s32 ret_val = 0;
195
196 if (offset > MAX_PHY_REG_ADDRESS) {
197 hw_dbg("PHY Address %d is out of range\n", offset);
198 ret_val = -E1000_ERR_PARAM;
199 goto out;
200 }
201
202 /* Set up Op-code, Phy Address, and register offset in the MDI
203 * Control register. The MAC will take care of interfacing with the
204 * PHY to retrieve the desired data.
205 */
206 mdic = (((u32)data) |
207 (offset << E1000_MDIC_REG_SHIFT) |
208 (phy->addr << E1000_MDIC_PHY_SHIFT) |
209 (E1000_MDIC_OP_WRITE));
210
211 wr32(E1000_MDIC, mdic);
212
213 /* Poll the ready bit to see if the MDI read completed
214 * Increasing the time out as testing showed failures with
215 * the lower time out
216 */
217 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
218 udelay(50);
219 mdic = rd32(E1000_MDIC);
220 if (mdic & E1000_MDIC_READY)
221 break;
222 }
223 if (!(mdic & E1000_MDIC_READY)) {
224 hw_dbg("MDI Write did not complete\n");
225 ret_val = -E1000_ERR_PHY;
226 goto out;
227 }
228 if (mdic & E1000_MDIC_ERROR) {
229 hw_dbg("MDI Error\n");
230 ret_val = -E1000_ERR_PHY;
231 goto out;
232 }
233
234out:
235 return ret_val;
236}
237
238/**
239 * igb_read_phy_reg_i2c - Read PHY register using i2c
240 * @hw: pointer to the HW structure
241 * @offset: register offset to be read
242 * @data: pointer to the read data
243 *
244 * Reads the PHY register at offset using the i2c interface and stores the
245 * retrieved information in data.
246 **/
247s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
248{
249 struct e1000_phy_info *phy = &hw->phy;
250 u32 i, i2ccmd = 0;
251
252 /* Set up Op-code, Phy Address, and register address in the I2CCMD
253 * register. The MAC will take care of interfacing with the
254 * PHY to retrieve the desired data.
255 */
256 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
257 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
258 (E1000_I2CCMD_OPCODE_READ));
259
260 wr32(E1000_I2CCMD, i2ccmd);
261
262 /* Poll the ready bit to see if the I2C read completed */
263 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
264 udelay(50);
265 i2ccmd = rd32(E1000_I2CCMD);
266 if (i2ccmd & E1000_I2CCMD_READY)
267 break;
268 }
269 if (!(i2ccmd & E1000_I2CCMD_READY)) {
270 hw_dbg("I2CCMD Read did not complete\n");
271 return -E1000_ERR_PHY;
272 }
273 if (i2ccmd & E1000_I2CCMD_ERROR) {
274 hw_dbg("I2CCMD Error bit set\n");
275 return -E1000_ERR_PHY;
276 }
277
278 /* Need to byte-swap the 16-bit value. */
279 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
280
281 return 0;
282}
283
284/**
285 * igb_write_phy_reg_i2c - Write PHY register using i2c
286 * @hw: pointer to the HW structure
287 * @offset: register offset to write to
288 * @data: data to write at register offset
289 *
290 * Writes the data to PHY register at the offset using the i2c interface.
291 **/
292s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
293{
294 struct e1000_phy_info *phy = &hw->phy;
295 u32 i, i2ccmd = 0;
296 u16 phy_data_swapped;
297
298 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
299 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
300 hw_dbg("PHY I2C Address %d is out of range.\n",
301 hw->phy.addr);
302 return -E1000_ERR_CONFIG;
303 }
304
305 /* Swap the data bytes for the I2C interface */
306 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
307
308 /* Set up Op-code, Phy Address, and register address in the I2CCMD
309 * register. The MAC will take care of interfacing with the
310 * PHY to retrieve the desired data.
311 */
312 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
313 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
314 E1000_I2CCMD_OPCODE_WRITE |
315 phy_data_swapped);
316
317 wr32(E1000_I2CCMD, i2ccmd);
318
319 /* Poll the ready bit to see if the I2C read completed */
320 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
321 udelay(50);
322 i2ccmd = rd32(E1000_I2CCMD);
323 if (i2ccmd & E1000_I2CCMD_READY)
324 break;
325 }
326 if (!(i2ccmd & E1000_I2CCMD_READY)) {
327 hw_dbg("I2CCMD Write did not complete\n");
328 return -E1000_ERR_PHY;
329 }
330 if (i2ccmd & E1000_I2CCMD_ERROR) {
331 hw_dbg("I2CCMD Error bit set\n");
332 return -E1000_ERR_PHY;
333 }
334
335 return 0;
336}
337
338/**
339 * igb_read_sfp_data_byte - Reads SFP module data.
340 * @hw: pointer to the HW structure
341 * @offset: byte location offset to be read
342 * @data: read data buffer pointer
343 *
344 * Reads one byte from SFP module data stored
345 * in SFP resided EEPROM memory or SFP diagnostic area.
346 * Function should be called with
347 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
348 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
349 * access
350 **/
351s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
352{
353 u32 i = 0;
354 u32 i2ccmd = 0;
355 u32 data_local = 0;
356
357 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
358 hw_dbg("I2CCMD command address exceeds upper limit\n");
359 return -E1000_ERR_PHY;
360 }
361
362 /* Set up Op-code, EEPROM Address,in the I2CCMD
363 * register. The MAC will take care of interfacing with the
364 * EEPROM to retrieve the desired data.
365 */
366 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
367 E1000_I2CCMD_OPCODE_READ);
368
369 wr32(E1000_I2CCMD, i2ccmd);
370
371 /* Poll the ready bit to see if the I2C read completed */
372 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
373 udelay(50);
374 data_local = rd32(E1000_I2CCMD);
375 if (data_local & E1000_I2CCMD_READY)
376 break;
377 }
378 if (!(data_local & E1000_I2CCMD_READY)) {
379 hw_dbg("I2CCMD Read did not complete\n");
380 return -E1000_ERR_PHY;
381 }
382 if (data_local & E1000_I2CCMD_ERROR) {
383 hw_dbg("I2CCMD Error bit set\n");
384 return -E1000_ERR_PHY;
385 }
386 *data = (u8) data_local & 0xFF;
387
388 return 0;
389}
390
391/**
392 * igb_read_phy_reg_igp - Read igp PHY register
393 * @hw: pointer to the HW structure
394 * @offset: register offset to be read
395 * @data: pointer to the read data
396 *
397 * Acquires semaphore, if necessary, then reads the PHY register at offset
398 * and storing the retrieved information in data. Release any acquired
399 * semaphores before exiting.
400 **/
401s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
402{
403 s32 ret_val = 0;
404
405 if (!(hw->phy.ops.acquire))
406 goto out;
407
408 ret_val = hw->phy.ops.acquire(hw);
409 if (ret_val)
410 goto out;
411
412 if (offset > MAX_PHY_MULTI_PAGE_REG) {
413 ret_val = igb_write_phy_reg_mdic(hw,
414 IGP01E1000_PHY_PAGE_SELECT,
415 (u16)offset);
416 if (ret_val) {
417 hw->phy.ops.release(hw);
418 goto out;
419 }
420 }
421
422 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
423 data);
424
425 hw->phy.ops.release(hw);
426
427out:
428 return ret_val;
429}
430
431/**
432 * igb_write_phy_reg_igp - Write igp PHY register
433 * @hw: pointer to the HW structure
434 * @offset: register offset to write to
435 * @data: data to write at register offset
436 *
437 * Acquires semaphore, if necessary, then writes the data to PHY register
438 * at the offset. Release any acquired semaphores before exiting.
439 **/
440s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
441{
442 s32 ret_val = 0;
443
444 if (!(hw->phy.ops.acquire))
445 goto out;
446
447 ret_val = hw->phy.ops.acquire(hw);
448 if (ret_val)
449 goto out;
450
451 if (offset > MAX_PHY_MULTI_PAGE_REG) {
452 ret_val = igb_write_phy_reg_mdic(hw,
453 IGP01E1000_PHY_PAGE_SELECT,
454 (u16)offset);
455 if (ret_val) {
456 hw->phy.ops.release(hw);
457 goto out;
458 }
459 }
460
461 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
462 data);
463
464 hw->phy.ops.release(hw);
465
466out:
467 return ret_val;
468}
469
470/**
471 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
472 * @hw: pointer to the HW structure
473 *
474 * Sets up Carrier-sense on Transmit and downshift values.
475 **/
476s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
477{
478 struct e1000_phy_info *phy = &hw->phy;
479 s32 ret_val;
480 u16 phy_data;
481
482 if (phy->reset_disable) {
483 ret_val = 0;
484 goto out;
485 }
486
487 if (phy->type == e1000_phy_82580) {
488 ret_val = hw->phy.ops.reset(hw);
489 if (ret_val) {
490 hw_dbg("Error resetting the PHY.\n");
491 goto out;
492 }
493 }
494
495 /* Enable CRS on TX. This must be set for half-duplex operation. */
496 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
497 if (ret_val)
498 goto out;
499
500 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
501
502 /* Enable downshift */
503 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
504
505 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
506 if (ret_val)
507 goto out;
508
509 /* Set MDI/MDIX mode */
510 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
511 if (ret_val)
512 goto out;
513 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
514 /* Options:
515 * 0 - Auto (default)
516 * 1 - MDI mode
517 * 2 - MDI-X mode
518 */
519 switch (hw->phy.mdix) {
520 case 1:
521 break;
522 case 2:
523 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
524 break;
525 case 0:
526 default:
527 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
528 break;
529 }
530 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
531
532out:
533 return ret_val;
534}
535
536/**
537 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
538 * @hw: pointer to the HW structure
539 *
540 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
541 * and downshift values are set also.
542 **/
543s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
544{
545 struct e1000_phy_info *phy = &hw->phy;
546 s32 ret_val;
547 u16 phy_data;
548
549 if (phy->reset_disable) {
550 ret_val = 0;
551 goto out;
552 }
553
554 /* Enable CRS on TX. This must be set for half-duplex operation. */
555 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
556 if (ret_val)
557 goto out;
558
559 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
560
561 /* Options:
562 * MDI/MDI-X = 0 (default)
563 * 0 - Auto for all speeds
564 * 1 - MDI mode
565 * 2 - MDI-X mode
566 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
567 */
568 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
569
570 switch (phy->mdix) {
571 case 1:
572 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
573 break;
574 case 2:
575 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
576 break;
577 case 3:
578 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
579 break;
580 case 0:
581 default:
582 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
583 break;
584 }
585
586 /* Options:
587 * disable_polarity_correction = 0 (default)
588 * Automatic Correction for Reversed Cable Polarity
589 * 0 - Disabled
590 * 1 - Enabled
591 */
592 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
593 if (phy->disable_polarity_correction == 1)
594 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
595
596 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
597 if (ret_val)
598 goto out;
599
600 if (phy->revision < E1000_REVISION_4) {
601 /* Force TX_CLK in the Extended PHY Specific Control Register
602 * to 25MHz clock.
603 */
604 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
605 &phy_data);
606 if (ret_val)
607 goto out;
608
609 phy_data |= M88E1000_EPSCR_TX_CLK_25;
610
611 if ((phy->revision == E1000_REVISION_2) &&
612 (phy->id == M88E1111_I_PHY_ID)) {
613 /* 82573L PHY - set the downshift counter to 5x. */
614 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
615 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
616 } else {
617 /* Configure Master and Slave downshift values */
618 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
619 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
620 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
621 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
622 }
623 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
624 phy_data);
625 if (ret_val)
626 goto out;
627 }
628
629 /* Commit the changes. */
630 ret_val = igb_phy_sw_reset(hw);
631 if (ret_val) {
632 hw_dbg("Error committing the PHY changes\n");
633 goto out;
634 }
635
636out:
637 return ret_val;
638}
639
640/**
641 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
642 * @hw: pointer to the HW structure
643 *
644 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
645 * Also enables and sets the downshift parameters.
646 **/
647s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
648{
649 struct e1000_phy_info *phy = &hw->phy;
650 s32 ret_val;
651 u16 phy_data;
652
653 if (phy->reset_disable)
654 return 0;
655
656 /* Enable CRS on Tx. This must be set for half-duplex operation. */
657 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
658 if (ret_val)
659 return ret_val;
660
661 /* Options:
662 * MDI/MDI-X = 0 (default)
663 * 0 - Auto for all speeds
664 * 1 - MDI mode
665 * 2 - MDI-X mode
666 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
667 */
668 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
669
670 switch (phy->mdix) {
671 case 1:
672 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
673 break;
674 case 2:
675 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
676 break;
677 case 3:
678 /* M88E1112 does not support this mode) */
679 if (phy->id != M88E1112_E_PHY_ID) {
680 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
681 break;
682 }
683 case 0:
684 default:
685 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
686 break;
687 }
688
689 /* Options:
690 * disable_polarity_correction = 0 (default)
691 * Automatic Correction for Reversed Cable Polarity
692 * 0 - Disabled
693 * 1 - Enabled
694 */
695 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
696 if (phy->disable_polarity_correction == 1)
697 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
698
699 /* Enable downshift and setting it to X6 */
700 if (phy->id == M88E1543_E_PHY_ID) {
701 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
702 ret_val =
703 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
704 if (ret_val)
705 return ret_val;
706
707 ret_val = igb_phy_sw_reset(hw);
708 if (ret_val) {
709 hw_dbg("Error committing the PHY changes\n");
710 return ret_val;
711 }
712 }
713
714 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
715 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
716 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
717
718 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
719 if (ret_val)
720 return ret_val;
721
722 /* Commit the changes. */
723 ret_val = igb_phy_sw_reset(hw);
724 if (ret_val) {
725 hw_dbg("Error committing the PHY changes\n");
726 return ret_val;
727 }
728 ret_val = igb_set_master_slave_mode(hw);
729 if (ret_val)
730 return ret_val;
731
732 return 0;
733}
734
735/**
736 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
737 * @hw: pointer to the HW structure
738 *
739 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
740 * igp PHY's.
741 **/
742s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
743{
744 struct e1000_phy_info *phy = &hw->phy;
745 s32 ret_val;
746 u16 data;
747
748 if (phy->reset_disable) {
749 ret_val = 0;
750 goto out;
751 }
752
753 ret_val = phy->ops.reset(hw);
754 if (ret_val) {
755 hw_dbg("Error resetting the PHY.\n");
756 goto out;
757 }
758
759 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
760 * timeout issues when LFS is enabled.
761 */
762 msleep(100);
763
764 /* The NVM settings will configure LPLU in D3 for
765 * non-IGP1 PHYs.
766 */
767 if (phy->type == e1000_phy_igp) {
768 /* disable lplu d3 during driver init */
769 if (phy->ops.set_d3_lplu_state)
770 ret_val = phy->ops.set_d3_lplu_state(hw, false);
771 if (ret_val) {
772 hw_dbg("Error Disabling LPLU D3\n");
773 goto out;
774 }
775 }
776
777 /* disable lplu d0 during driver init */
778 ret_val = phy->ops.set_d0_lplu_state(hw, false);
779 if (ret_val) {
780 hw_dbg("Error Disabling LPLU D0\n");
781 goto out;
782 }
783 /* Configure mdi-mdix settings */
784 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
785 if (ret_val)
786 goto out;
787
788 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
789
790 switch (phy->mdix) {
791 case 1:
792 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
793 break;
794 case 2:
795 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
796 break;
797 case 0:
798 default:
799 data |= IGP01E1000_PSCR_AUTO_MDIX;
800 break;
801 }
802 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
803 if (ret_val)
804 goto out;
805
806 /* set auto-master slave resolution settings */
807 if (hw->mac.autoneg) {
808 /* when autonegotiation advertisement is only 1000Mbps then we
809 * should disable SmartSpeed and enable Auto MasterSlave
810 * resolution as hardware default.
811 */
812 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
813 /* Disable SmartSpeed */
814 ret_val = phy->ops.read_reg(hw,
815 IGP01E1000_PHY_PORT_CONFIG,
816 &data);
817 if (ret_val)
818 goto out;
819
820 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
821 ret_val = phy->ops.write_reg(hw,
822 IGP01E1000_PHY_PORT_CONFIG,
823 data);
824 if (ret_val)
825 goto out;
826
827 /* Set auto Master/Slave resolution process */
828 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
829 if (ret_val)
830 goto out;
831
832 data &= ~CR_1000T_MS_ENABLE;
833 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
834 if (ret_val)
835 goto out;
836 }
837
838 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
839 if (ret_val)
840 goto out;
841
842 /* load defaults for future use */
843 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
844 ((data & CR_1000T_MS_VALUE) ?
845 e1000_ms_force_master :
846 e1000_ms_force_slave) :
847 e1000_ms_auto;
848
849 switch (phy->ms_type) {
850 case e1000_ms_force_master:
851 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
852 break;
853 case e1000_ms_force_slave:
854 data |= CR_1000T_MS_ENABLE;
855 data &= ~(CR_1000T_MS_VALUE);
856 break;
857 case e1000_ms_auto:
858 data &= ~CR_1000T_MS_ENABLE;
859 default:
860 break;
861 }
862 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
863 if (ret_val)
864 goto out;
865 }
866
867out:
868 return ret_val;
869}
870
871/**
872 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
873 * @hw: pointer to the HW structure
874 *
875 * Performs initial bounds checking on autoneg advertisement parameter, then
876 * configure to advertise the full capability. Setup the PHY to autoneg
877 * and restart the negotiation process between the link partner. If
878 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
879 **/
880static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
881{
882 struct e1000_phy_info *phy = &hw->phy;
883 s32 ret_val;
884 u16 phy_ctrl;
885
886 /* Perform some bounds checking on the autoneg advertisement
887 * parameter.
888 */
889 phy->autoneg_advertised &= phy->autoneg_mask;
890
891 /* If autoneg_advertised is zero, we assume it was not defaulted
892 * by the calling code so we set to advertise full capability.
893 */
894 if (phy->autoneg_advertised == 0)
895 phy->autoneg_advertised = phy->autoneg_mask;
896
897 hw_dbg("Reconfiguring auto-neg advertisement params\n");
898 ret_val = igb_phy_setup_autoneg(hw);
899 if (ret_val) {
900 hw_dbg("Error Setting up Auto-Negotiation\n");
901 goto out;
902 }
903 hw_dbg("Restarting Auto-Neg\n");
904
905 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
906 * the Auto Neg Restart bit in the PHY control register.
907 */
908 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
909 if (ret_val)
910 goto out;
911
912 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
913 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
914 if (ret_val)
915 goto out;
916
917 /* Does the user want to wait for Auto-Neg to complete here, or
918 * check at a later time (for example, callback routine).
919 */
920 if (phy->autoneg_wait_to_complete) {
921 ret_val = igb_wait_autoneg(hw);
922 if (ret_val) {
923 hw_dbg("Error while waiting for autoneg to complete\n");
924 goto out;
925 }
926 }
927
928 hw->mac.get_link_status = true;
929
930out:
931 return ret_val;
932}
933
934/**
935 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
936 * @hw: pointer to the HW structure
937 *
938 * Reads the MII auto-neg advertisement register and/or the 1000T control
939 * register and if the PHY is already setup for auto-negotiation, then
940 * return successful. Otherwise, setup advertisement and flow control to
941 * the appropriate values for the wanted auto-negotiation.
942 **/
943static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
944{
945 struct e1000_phy_info *phy = &hw->phy;
946 s32 ret_val;
947 u16 mii_autoneg_adv_reg;
948 u16 mii_1000t_ctrl_reg = 0;
949
950 phy->autoneg_advertised &= phy->autoneg_mask;
951
952 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
953 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
954 if (ret_val)
955 goto out;
956
957 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
958 /* Read the MII 1000Base-T Control Register (Address 9). */
959 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
960 &mii_1000t_ctrl_reg);
961 if (ret_val)
962 goto out;
963 }
964
965 /* Need to parse both autoneg_advertised and fc and set up
966 * the appropriate PHY registers. First we will parse for
967 * autoneg_advertised software override. Since we can advertise
968 * a plethora of combinations, we need to check each bit
969 * individually.
970 */
971
972 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
973 * Advertisement Register (Address 4) and the 1000 mb speed bits in
974 * the 1000Base-T Control Register (Address 9).
975 */
976 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
977 NWAY_AR_100TX_HD_CAPS |
978 NWAY_AR_10T_FD_CAPS |
979 NWAY_AR_10T_HD_CAPS);
980 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
981
982 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
983
984 /* Do we want to advertise 10 Mb Half Duplex? */
985 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
986 hw_dbg("Advertise 10mb Half duplex\n");
987 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
988 }
989
990 /* Do we want to advertise 10 Mb Full Duplex? */
991 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
992 hw_dbg("Advertise 10mb Full duplex\n");
993 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
994 }
995
996 /* Do we want to advertise 100 Mb Half Duplex? */
997 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
998 hw_dbg("Advertise 100mb Half duplex\n");
999 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1000 }
1001
1002 /* Do we want to advertise 100 Mb Full Duplex? */
1003 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1004 hw_dbg("Advertise 100mb Full duplex\n");
1005 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1006 }
1007
1008 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1009 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1010 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1011
1012 /* Do we want to advertise 1000 Mb Full Duplex? */
1013 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1014 hw_dbg("Advertise 1000mb Full duplex\n");
1015 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1016 }
1017
1018 /* Check for a software override of the flow control settings, and
1019 * setup the PHY advertisement registers accordingly. If
1020 * auto-negotiation is enabled, then software will have to set the
1021 * "PAUSE" bits to the correct value in the Auto-Negotiation
1022 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1023 * negotiation.
1024 *
1025 * The possible values of the "fc" parameter are:
1026 * 0: Flow control is completely disabled
1027 * 1: Rx flow control is enabled (we can receive pause frames
1028 * but not send pause frames).
1029 * 2: Tx flow control is enabled (we can send pause frames
1030 * but we do not support receiving pause frames).
1031 * 3: Both Rx and TX flow control (symmetric) are enabled.
1032 * other: No software override. The flow control configuration
1033 * in the EEPROM is used.
1034 */
1035 switch (hw->fc.current_mode) {
1036 case e1000_fc_none:
1037 /* Flow control (RX & TX) is completely disabled by a
1038 * software over-ride.
1039 */
1040 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1041 break;
1042 case e1000_fc_rx_pause:
1043 /* RX Flow control is enabled, and TX Flow control is
1044 * disabled, by a software over-ride.
1045 *
1046 * Since there really isn't a way to advertise that we are
1047 * capable of RX Pause ONLY, we will advertise that we
1048 * support both symmetric and asymmetric RX PAUSE. Later
1049 * (in e1000_config_fc_after_link_up) we will disable the
1050 * hw's ability to send PAUSE frames.
1051 */
1052 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1053 break;
1054 case e1000_fc_tx_pause:
1055 /* TX Flow control is enabled, and RX Flow control is
1056 * disabled, by a software over-ride.
1057 */
1058 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1059 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1060 break;
1061 case e1000_fc_full:
1062 /* Flow control (both RX and TX) is enabled by a software
1063 * over-ride.
1064 */
1065 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1066 break;
1067 default:
1068 hw_dbg("Flow control param set incorrectly\n");
1069 ret_val = -E1000_ERR_CONFIG;
1070 goto out;
1071 }
1072
1073 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1074 if (ret_val)
1075 goto out;
1076
1077 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1078
1079 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1080 ret_val = phy->ops.write_reg(hw,
1081 PHY_1000T_CTRL,
1082 mii_1000t_ctrl_reg);
1083 if (ret_val)
1084 goto out;
1085 }
1086
1087out:
1088 return ret_val;
1089}
1090
1091/**
1092 * igb_setup_copper_link - Configure copper link settings
1093 * @hw: pointer to the HW structure
1094 *
1095 * Calls the appropriate function to configure the link for auto-neg or forced
1096 * speed and duplex. Then we check for link, once link is established calls
1097 * to configure collision distance and flow control are called. If link is
1098 * not established, we return -E1000_ERR_PHY (-2).
1099 **/
1100s32 igb_setup_copper_link(struct e1000_hw *hw)
1101{
1102 s32 ret_val;
1103 bool link;
1104
1105 if (hw->mac.autoneg) {
1106 /* Setup autoneg and flow control advertisement and perform
1107 * autonegotiation.
1108 */
1109 ret_val = igb_copper_link_autoneg(hw);
1110 if (ret_val)
1111 goto out;
1112 } else {
1113 /* PHY will be set to 10H, 10F, 100H or 100F
1114 * depending on user settings.
1115 */
1116 hw_dbg("Forcing Speed and Duplex\n");
1117 ret_val = hw->phy.ops.force_speed_duplex(hw);
1118 if (ret_val) {
1119 hw_dbg("Error Forcing Speed and Duplex\n");
1120 goto out;
1121 }
1122 }
1123
1124 /* Check link status. Wait up to 100 microseconds for link to become
1125 * valid.
1126 */
1127 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1128 if (ret_val)
1129 goto out;
1130
1131 if (link) {
1132 hw_dbg("Valid link established!!!\n");
1133 igb_config_collision_dist(hw);
1134 ret_val = igb_config_fc_after_link_up(hw);
1135 } else {
1136 hw_dbg("Unable to establish link!!!\n");
1137 }
1138
1139out:
1140 return ret_val;
1141}
1142
1143/**
1144 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1145 * @hw: pointer to the HW structure
1146 *
1147 * Calls the PHY setup function to force speed and duplex. Clears the
1148 * auto-crossover to force MDI manually. Waits for link and returns
1149 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1150 **/
1151s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1152{
1153 struct e1000_phy_info *phy = &hw->phy;
1154 s32 ret_val;
1155 u16 phy_data;
1156 bool link;
1157
1158 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1159 if (ret_val)
1160 goto out;
1161
1162 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1163
1164 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1165 if (ret_val)
1166 goto out;
1167
1168 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1169 * forced whenever speed and duplex are forced.
1170 */
1171 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1172 if (ret_val)
1173 goto out;
1174
1175 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1176 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1177
1178 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1179 if (ret_val)
1180 goto out;
1181
1182 hw_dbg("IGP PSCR: %X\n", phy_data);
1183
1184 udelay(1);
1185
1186 if (phy->autoneg_wait_to_complete) {
1187 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1188
1189 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1190 if (ret_val)
1191 goto out;
1192
1193 if (!link)
1194 hw_dbg("Link taking longer than expected.\n");
1195
1196 /* Try once more */
1197 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1198 if (ret_val)
1199 goto out;
1200 }
1201
1202out:
1203 return ret_val;
1204}
1205
1206/**
1207 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1208 * @hw: pointer to the HW structure
1209 *
1210 * Calls the PHY setup function to force speed and duplex. Clears the
1211 * auto-crossover to force MDI manually. Resets the PHY to commit the
1212 * changes. If time expires while waiting for link up, we reset the DSP.
1213 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1214 * successful completion, else return corresponding error code.
1215 **/
1216s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1217{
1218 struct e1000_phy_info *phy = &hw->phy;
1219 s32 ret_val;
1220 u16 phy_data;
1221 bool link;
1222
1223 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1224 if (phy->type != e1000_phy_i210) {
1225 /* Clear Auto-Crossover to force MDI manually. M88E1000
1226 * requires MDI forced whenever speed and duplex are forced.
1227 */
1228 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1229 &phy_data);
1230 if (ret_val)
1231 goto out;
1232
1233 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1234 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1235 phy_data);
1236 if (ret_val)
1237 goto out;
1238
1239 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1240 }
1241
1242 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1243 if (ret_val)
1244 goto out;
1245
1246 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1247
1248 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1249 if (ret_val)
1250 goto out;
1251
1252 /* Reset the phy to commit changes. */
1253 ret_val = igb_phy_sw_reset(hw);
1254 if (ret_val)
1255 goto out;
1256
1257 if (phy->autoneg_wait_to_complete) {
1258 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1259
1260 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1261 if (ret_val)
1262 goto out;
1263
1264 if (!link) {
1265 bool reset_dsp = true;
1266
1267 switch (hw->phy.id) {
1268 case I347AT4_E_PHY_ID:
1269 case M88E1112_E_PHY_ID:
1270 case M88E1543_E_PHY_ID:
1271 case M88E1512_E_PHY_ID:
1272 case I210_I_PHY_ID:
1273 reset_dsp = false;
1274 break;
1275 default:
1276 if (hw->phy.type != e1000_phy_m88)
1277 reset_dsp = false;
1278 break;
1279 }
1280 if (!reset_dsp) {
1281 hw_dbg("Link taking longer than expected.\n");
1282 } else {
1283 /* We didn't get link.
1284 * Reset the DSP and cross our fingers.
1285 */
1286 ret_val = phy->ops.write_reg(hw,
1287 M88E1000_PHY_PAGE_SELECT,
1288 0x001d);
1289 if (ret_val)
1290 goto out;
1291 ret_val = igb_phy_reset_dsp(hw);
1292 if (ret_val)
1293 goto out;
1294 }
1295 }
1296
1297 /* Try once more */
1298 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1299 100000, &link);
1300 if (ret_val)
1301 goto out;
1302 }
1303
1304 if (hw->phy.type != e1000_phy_m88 ||
1305 hw->phy.id == I347AT4_E_PHY_ID ||
1306 hw->phy.id == M88E1112_E_PHY_ID ||
1307 hw->phy.id == M88E1543_E_PHY_ID ||
1308 hw->phy.id == M88E1512_E_PHY_ID ||
1309 hw->phy.id == I210_I_PHY_ID)
1310 goto out;
1311
1312 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1313 if (ret_val)
1314 goto out;
1315
1316 /* Resetting the phy means we need to re-force TX_CLK in the
1317 * Extended PHY Specific Control Register to 25MHz clock from
1318 * the reset value of 2.5MHz.
1319 */
1320 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1321 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1322 if (ret_val)
1323 goto out;
1324
1325 /* In addition, we must re-enable CRS on Tx for both half and full
1326 * duplex.
1327 */
1328 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1329 if (ret_val)
1330 goto out;
1331
1332 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1333 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1334
1335out:
1336 return ret_val;
1337}
1338
1339/**
1340 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1341 * @hw: pointer to the HW structure
1342 * @phy_ctrl: pointer to current value of PHY_CONTROL
1343 *
1344 * Forces speed and duplex on the PHY by doing the following: disable flow
1345 * control, force speed/duplex on the MAC, disable auto speed detection,
1346 * disable auto-negotiation, configure duplex, configure speed, configure
1347 * the collision distance, write configuration to CTRL register. The
1348 * caller must write to the PHY_CONTROL register for these settings to
1349 * take affect.
1350 **/
1351static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1352 u16 *phy_ctrl)
1353{
1354 struct e1000_mac_info *mac = &hw->mac;
1355 u32 ctrl;
1356
1357 /* Turn off flow control when forcing speed/duplex */
1358 hw->fc.current_mode = e1000_fc_none;
1359
1360 /* Force speed/duplex on the mac */
1361 ctrl = rd32(E1000_CTRL);
1362 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1363 ctrl &= ~E1000_CTRL_SPD_SEL;
1364
1365 /* Disable Auto Speed Detection */
1366 ctrl &= ~E1000_CTRL_ASDE;
1367
1368 /* Disable autoneg on the phy */
1369 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1370
1371 /* Forcing Full or Half Duplex? */
1372 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1373 ctrl &= ~E1000_CTRL_FD;
1374 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1375 hw_dbg("Half Duplex\n");
1376 } else {
1377 ctrl |= E1000_CTRL_FD;
1378 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1379 hw_dbg("Full Duplex\n");
1380 }
1381
1382 /* Forcing 10mb or 100mb? */
1383 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1384 ctrl |= E1000_CTRL_SPD_100;
1385 *phy_ctrl |= MII_CR_SPEED_100;
1386 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1387 hw_dbg("Forcing 100mb\n");
1388 } else {
1389 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1390 *phy_ctrl |= MII_CR_SPEED_10;
1391 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1392 hw_dbg("Forcing 10mb\n");
1393 }
1394
1395 igb_config_collision_dist(hw);
1396
1397 wr32(E1000_CTRL, ctrl);
1398}
1399
1400/**
1401 * igb_set_d3_lplu_state - Sets low power link up state for D3
1402 * @hw: pointer to the HW structure
1403 * @active: boolean used to enable/disable lplu
1404 *
1405 * Success returns 0, Failure returns 1
1406 *
1407 * The low power link up (lplu) state is set to the power management level D3
1408 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1409 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1410 * is used during Dx states where the power conservation is most important.
1411 * During driver activity, SmartSpeed should be enabled so performance is
1412 * maintained.
1413 **/
1414s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1415{
1416 struct e1000_phy_info *phy = &hw->phy;
1417 s32 ret_val = 0;
1418 u16 data;
1419
1420 if (!(hw->phy.ops.read_reg))
1421 goto out;
1422
1423 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1424 if (ret_val)
1425 goto out;
1426
1427 if (!active) {
1428 data &= ~IGP02E1000_PM_D3_LPLU;
1429 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1430 data);
1431 if (ret_val)
1432 goto out;
1433 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1434 * during Dx states where the power conservation is most
1435 * important. During driver activity we should enable
1436 * SmartSpeed, so performance is maintained.
1437 */
1438 if (phy->smart_speed == e1000_smart_speed_on) {
1439 ret_val = phy->ops.read_reg(hw,
1440 IGP01E1000_PHY_PORT_CONFIG,
1441 &data);
1442 if (ret_val)
1443 goto out;
1444
1445 data |= IGP01E1000_PSCFR_SMART_SPEED;
1446 ret_val = phy->ops.write_reg(hw,
1447 IGP01E1000_PHY_PORT_CONFIG,
1448 data);
1449 if (ret_val)
1450 goto out;
1451 } else if (phy->smart_speed == e1000_smart_speed_off) {
1452 ret_val = phy->ops.read_reg(hw,
1453 IGP01E1000_PHY_PORT_CONFIG,
1454 &data);
1455 if (ret_val)
1456 goto out;
1457
1458 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1459 ret_val = phy->ops.write_reg(hw,
1460 IGP01E1000_PHY_PORT_CONFIG,
1461 data);
1462 if (ret_val)
1463 goto out;
1464 }
1465 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1466 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1467 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1468 data |= IGP02E1000_PM_D3_LPLU;
1469 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1470 data);
1471 if (ret_val)
1472 goto out;
1473
1474 /* When LPLU is enabled, we should disable SmartSpeed */
1475 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1476 &data);
1477 if (ret_val)
1478 goto out;
1479
1480 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1481 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1482 data);
1483 }
1484
1485out:
1486 return ret_val;
1487}
1488
1489/**
1490 * igb_check_downshift - Checks whether a downshift in speed occurred
1491 * @hw: pointer to the HW structure
1492 *
1493 * Success returns 0, Failure returns 1
1494 *
1495 * A downshift is detected by querying the PHY link health.
1496 **/
1497s32 igb_check_downshift(struct e1000_hw *hw)
1498{
1499 struct e1000_phy_info *phy = &hw->phy;
1500 s32 ret_val;
1501 u16 phy_data, offset, mask;
1502
1503 switch (phy->type) {
1504 case e1000_phy_i210:
1505 case e1000_phy_m88:
1506 case e1000_phy_gg82563:
1507 offset = M88E1000_PHY_SPEC_STATUS;
1508 mask = M88E1000_PSSR_DOWNSHIFT;
1509 break;
1510 case e1000_phy_igp_2:
1511 case e1000_phy_igp:
1512 case e1000_phy_igp_3:
1513 offset = IGP01E1000_PHY_LINK_HEALTH;
1514 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1515 break;
1516 default:
1517 /* speed downshift not supported */
1518 phy->speed_downgraded = false;
1519 ret_val = 0;
1520 goto out;
1521 }
1522
1523 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1524
1525 if (!ret_val)
1526 phy->speed_downgraded = (phy_data & mask) ? true : false;
1527
1528out:
1529 return ret_val;
1530}
1531
1532/**
1533 * igb_check_polarity_m88 - Checks the polarity.
1534 * @hw: pointer to the HW structure
1535 *
1536 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1537 *
1538 * Polarity is determined based on the PHY specific status register.
1539 **/
1540s32 igb_check_polarity_m88(struct e1000_hw *hw)
1541{
1542 struct e1000_phy_info *phy = &hw->phy;
1543 s32 ret_val;
1544 u16 data;
1545
1546 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1547
1548 if (!ret_val)
1549 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1550 ? e1000_rev_polarity_reversed
1551 : e1000_rev_polarity_normal;
1552
1553 return ret_val;
1554}
1555
1556/**
1557 * igb_check_polarity_igp - Checks the polarity.
1558 * @hw: pointer to the HW structure
1559 *
1560 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1561 *
1562 * Polarity is determined based on the PHY port status register, and the
1563 * current speed (since there is no polarity at 100Mbps).
1564 **/
1565static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1566{
1567 struct e1000_phy_info *phy = &hw->phy;
1568 s32 ret_val;
1569 u16 data, offset, mask;
1570
1571 /* Polarity is determined based on the speed of
1572 * our connection.
1573 */
1574 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1575 if (ret_val)
1576 goto out;
1577
1578 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1579 IGP01E1000_PSSR_SPEED_1000MBPS) {
1580 offset = IGP01E1000_PHY_PCS_INIT_REG;
1581 mask = IGP01E1000_PHY_POLARITY_MASK;
1582 } else {
1583 /* This really only applies to 10Mbps since
1584 * there is no polarity for 100Mbps (always 0).
1585 */
1586 offset = IGP01E1000_PHY_PORT_STATUS;
1587 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1588 }
1589
1590 ret_val = phy->ops.read_reg(hw, offset, &data);
1591
1592 if (!ret_val)
1593 phy->cable_polarity = (data & mask)
1594 ? e1000_rev_polarity_reversed
1595 : e1000_rev_polarity_normal;
1596
1597out:
1598 return ret_val;
1599}
1600
1601/**
1602 * igb_wait_autoneg - Wait for auto-neg completion
1603 * @hw: pointer to the HW structure
1604 *
1605 * Waits for auto-negotiation to complete or for the auto-negotiation time
1606 * limit to expire, which ever happens first.
1607 **/
1608static s32 igb_wait_autoneg(struct e1000_hw *hw)
1609{
1610 s32 ret_val = 0;
1611 u16 i, phy_status;
1612
1613 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1614 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1615 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1616 if (ret_val)
1617 break;
1618 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1619 if (ret_val)
1620 break;
1621 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1622 break;
1623 msleep(100);
1624 }
1625
1626 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1627 * has completed.
1628 */
1629 return ret_val;
1630}
1631
1632/**
1633 * igb_phy_has_link - Polls PHY for link
1634 * @hw: pointer to the HW structure
1635 * @iterations: number of times to poll for link
1636 * @usec_interval: delay between polling attempts
1637 * @success: pointer to whether polling was successful or not
1638 *
1639 * Polls the PHY status register for link, 'iterations' number of times.
1640 **/
1641s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1642 u32 usec_interval, bool *success)
1643{
1644 s32 ret_val = 0;
1645 u16 i, phy_status;
1646
1647 for (i = 0; i < iterations; i++) {
1648 /* Some PHYs require the PHY_STATUS register to be read
1649 * twice due to the link bit being sticky. No harm doing
1650 * it across the board.
1651 */
1652 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1653 if (ret_val && usec_interval > 0) {
1654 /* If the first read fails, another entity may have
1655 * ownership of the resources, wait and try again to
1656 * see if they have relinquished the resources yet.
1657 */
1658 if (usec_interval >= 1000)
1659 mdelay(usec_interval/1000);
1660 else
1661 udelay(usec_interval);
1662 }
1663 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1664 if (ret_val)
1665 break;
1666 if (phy_status & MII_SR_LINK_STATUS)
1667 break;
1668 if (usec_interval >= 1000)
1669 mdelay(usec_interval/1000);
1670 else
1671 udelay(usec_interval);
1672 }
1673
1674 *success = (i < iterations) ? true : false;
1675
1676 return ret_val;
1677}
1678
1679/**
1680 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1681 * @hw: pointer to the HW structure
1682 *
1683 * Reads the PHY specific status register to retrieve the cable length
1684 * information. The cable length is determined by averaging the minimum and
1685 * maximum values to get the "average" cable length. The m88 PHY has four
1686 * possible cable length values, which are:
1687 * Register Value Cable Length
1688 * 0 < 50 meters
1689 * 1 50 - 80 meters
1690 * 2 80 - 110 meters
1691 * 3 110 - 140 meters
1692 * 4 > 140 meters
1693 **/
1694s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1695{
1696 struct e1000_phy_info *phy = &hw->phy;
1697 s32 ret_val;
1698 u16 phy_data, index;
1699
1700 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1701 if (ret_val)
1702 goto out;
1703
1704 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1705 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1706 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1707 ret_val = -E1000_ERR_PHY;
1708 goto out;
1709 }
1710
1711 phy->min_cable_length = e1000_m88_cable_length_table[index];
1712 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1713
1714 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1715
1716out:
1717 return ret_val;
1718}
1719
1720s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1721{
1722 struct e1000_phy_info *phy = &hw->phy;
1723 s32 ret_val;
1724 u16 phy_data, phy_data2, index, default_page, is_cm;
1725 int len_tot = 0;
1726 u16 len_min;
1727 u16 len_max;
1728
1729 switch (hw->phy.id) {
1730 case M88E1543_E_PHY_ID:
1731 case M88E1512_E_PHY_ID:
1732 case I347AT4_E_PHY_ID:
1733 case I210_I_PHY_ID:
1734 /* Remember the original page select and set it to 7 */
1735 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1736 &default_page);
1737 if (ret_val)
1738 goto out;
1739
1740 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1741 if (ret_val)
1742 goto out;
1743
1744 /* Check if the unit of cable length is meters or cm */
1745 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1746 if (ret_val)
1747 goto out;
1748
1749 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1750
1751 /* Get cable length from Pair 0 length Regs */
1752 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL0, &phy_data);
1753 if (ret_val)
1754 goto out;
1755
1756 phy->pair_length[0] = phy_data / (is_cm ? 100 : 1);
1757 len_tot = phy->pair_length[0];
1758 len_min = phy->pair_length[0];
1759 len_max = phy->pair_length[0];
1760
1761 /* Get cable length from Pair 1 length Regs */
1762 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL1, &phy_data);
1763 if (ret_val)
1764 goto out;
1765
1766 phy->pair_length[1] = phy_data / (is_cm ? 100 : 1);
1767 len_tot += phy->pair_length[1];
1768 len_min = min(len_min, phy->pair_length[1]);
1769 len_max = max(len_max, phy->pair_length[1]);
1770
1771 /* Get cable length from Pair 2 length Regs */
1772 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL2, &phy_data);
1773 if (ret_val)
1774 goto out;
1775
1776 phy->pair_length[2] = phy_data / (is_cm ? 100 : 1);
1777 len_tot += phy->pair_length[2];
1778 len_min = min(len_min, phy->pair_length[2]);
1779 len_max = max(len_max, phy->pair_length[2]);
1780
1781 /* Get cable length from Pair 3 length Regs */
1782 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL3, &phy_data);
1783 if (ret_val)
1784 goto out;
1785
1786 phy->pair_length[3] = phy_data / (is_cm ? 100 : 1);
1787 len_tot += phy->pair_length[3];
1788 len_min = min(len_min, phy->pair_length[3]);
1789 len_max = max(len_max, phy->pair_length[3]);
1790
1791 /* Populate the phy structure with cable length in meters */
1792 phy->min_cable_length = len_min;
1793 phy->max_cable_length = len_max;
1794 phy->cable_length = len_tot / 4;
1795
1796 /* Reset the page selec to its original value */
1797 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1798 default_page);
1799 if (ret_val)
1800 goto out;
1801 break;
1802 case M88E1112_E_PHY_ID:
1803 /* Remember the original page select and set it to 5 */
1804 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1805 &default_page);
1806 if (ret_val)
1807 goto out;
1808
1809 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1810 if (ret_val)
1811 goto out;
1812
1813 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1814 &phy_data);
1815 if (ret_val)
1816 goto out;
1817
1818 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1819 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1820 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1821 ret_val = -E1000_ERR_PHY;
1822 goto out;
1823 }
1824
1825 phy->min_cable_length = e1000_m88_cable_length_table[index];
1826 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1827
1828 phy->cable_length = (phy->min_cable_length +
1829 phy->max_cable_length) / 2;
1830
1831 /* Reset the page select to its original value */
1832 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1833 default_page);
1834 if (ret_val)
1835 goto out;
1836
1837 break;
1838 default:
1839 ret_val = -E1000_ERR_PHY;
1840 goto out;
1841 }
1842
1843out:
1844 return ret_val;
1845}
1846
1847/**
1848 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1849 * @hw: pointer to the HW structure
1850 *
1851 * The automatic gain control (agc) normalizes the amplitude of the
1852 * received signal, adjusting for the attenuation produced by the
1853 * cable. By reading the AGC registers, which represent the
1854 * combination of coarse and fine gain value, the value can be put
1855 * into a lookup table to obtain the approximate cable length
1856 * for each channel.
1857 **/
1858s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1859{
1860 struct e1000_phy_info *phy = &hw->phy;
1861 s32 ret_val = 0;
1862 u16 phy_data, i, agc_value = 0;
1863 u16 cur_agc_index, max_agc_index = 0;
1864 u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1;
1865 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1866 IGP02E1000_PHY_AGC_A,
1867 IGP02E1000_PHY_AGC_B,
1868 IGP02E1000_PHY_AGC_C,
1869 IGP02E1000_PHY_AGC_D
1870 };
1871
1872 /* Read the AGC registers for all channels */
1873 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1874 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1875 if (ret_val)
1876 goto out;
1877
1878 /* Getting bits 15:9, which represent the combination of
1879 * coarse and fine gain values. The result is a number
1880 * that can be put into the lookup table to obtain the
1881 * approximate cable length.
1882 */
1883 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1884 IGP02E1000_AGC_LENGTH_MASK;
1885
1886 /* Array index bound check. */
1887 if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) ||
1888 (cur_agc_index == 0)) {
1889 ret_val = -E1000_ERR_PHY;
1890 goto out;
1891 }
1892
1893 /* Remove min & max AGC values from calculation. */
1894 if (e1000_igp_2_cable_length_table[min_agc_index] >
1895 e1000_igp_2_cable_length_table[cur_agc_index])
1896 min_agc_index = cur_agc_index;
1897 if (e1000_igp_2_cable_length_table[max_agc_index] <
1898 e1000_igp_2_cable_length_table[cur_agc_index])
1899 max_agc_index = cur_agc_index;
1900
1901 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1902 }
1903
1904 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1905 e1000_igp_2_cable_length_table[max_agc_index]);
1906 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1907
1908 /* Calculate cable length with the error range of +/- 10 meters. */
1909 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1910 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1911 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1912
1913 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1914
1915out:
1916 return ret_val;
1917}
1918
1919/**
1920 * igb_get_phy_info_m88 - Retrieve PHY information
1921 * @hw: pointer to the HW structure
1922 *
1923 * Valid for only copper links. Read the PHY status register (sticky read)
1924 * to verify that link is up. Read the PHY special control register to
1925 * determine the polarity and 10base-T extended distance. Read the PHY
1926 * special status register to determine MDI/MDIx and current speed. If
1927 * speed is 1000, then determine cable length, local and remote receiver.
1928 **/
1929s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1930{
1931 struct e1000_phy_info *phy = &hw->phy;
1932 s32 ret_val;
1933 u16 phy_data;
1934 bool link;
1935
1936 if (phy->media_type != e1000_media_type_copper) {
1937 hw_dbg("Phy info is only valid for copper media\n");
1938 ret_val = -E1000_ERR_CONFIG;
1939 goto out;
1940 }
1941
1942 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1943 if (ret_val)
1944 goto out;
1945
1946 if (!link) {
1947 hw_dbg("Phy info is only valid if link is up\n");
1948 ret_val = -E1000_ERR_CONFIG;
1949 goto out;
1950 }
1951
1952 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1953 if (ret_val)
1954 goto out;
1955
1956 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1957 ? true : false;
1958
1959 ret_val = igb_check_polarity_m88(hw);
1960 if (ret_val)
1961 goto out;
1962
1963 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1964 if (ret_val)
1965 goto out;
1966
1967 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1968
1969 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1970 ret_val = phy->ops.get_cable_length(hw);
1971 if (ret_val)
1972 goto out;
1973
1974 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1975 if (ret_val)
1976 goto out;
1977
1978 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1979 ? e1000_1000t_rx_status_ok
1980 : e1000_1000t_rx_status_not_ok;
1981
1982 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1983 ? e1000_1000t_rx_status_ok
1984 : e1000_1000t_rx_status_not_ok;
1985 } else {
1986 /* Set values to "undefined" */
1987 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1988 phy->local_rx = e1000_1000t_rx_status_undefined;
1989 phy->remote_rx = e1000_1000t_rx_status_undefined;
1990 }
1991
1992out:
1993 return ret_val;
1994}
1995
1996/**
1997 * igb_get_phy_info_igp - Retrieve igp PHY information
1998 * @hw: pointer to the HW structure
1999 *
2000 * Read PHY status to determine if link is up. If link is up, then
2001 * set/determine 10base-T extended distance and polarity correction. Read
2002 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2003 * determine on the cable length, local and remote receiver.
2004 **/
2005s32 igb_get_phy_info_igp(struct e1000_hw *hw)
2006{
2007 struct e1000_phy_info *phy = &hw->phy;
2008 s32 ret_val;
2009 u16 data;
2010 bool link;
2011
2012 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2013 if (ret_val)
2014 goto out;
2015
2016 if (!link) {
2017 hw_dbg("Phy info is only valid if link is up\n");
2018 ret_val = -E1000_ERR_CONFIG;
2019 goto out;
2020 }
2021
2022 phy->polarity_correction = true;
2023
2024 ret_val = igb_check_polarity_igp(hw);
2025 if (ret_val)
2026 goto out;
2027
2028 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2029 if (ret_val)
2030 goto out;
2031
2032 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2033
2034 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2035 IGP01E1000_PSSR_SPEED_1000MBPS) {
2036 ret_val = phy->ops.get_cable_length(hw);
2037 if (ret_val)
2038 goto out;
2039
2040 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2041 if (ret_val)
2042 goto out;
2043
2044 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2045 ? e1000_1000t_rx_status_ok
2046 : e1000_1000t_rx_status_not_ok;
2047
2048 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2049 ? e1000_1000t_rx_status_ok
2050 : e1000_1000t_rx_status_not_ok;
2051 } else {
2052 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2053 phy->local_rx = e1000_1000t_rx_status_undefined;
2054 phy->remote_rx = e1000_1000t_rx_status_undefined;
2055 }
2056
2057out:
2058 return ret_val;
2059}
2060
2061/**
2062 * igb_phy_sw_reset - PHY software reset
2063 * @hw: pointer to the HW structure
2064 *
2065 * Does a software reset of the PHY by reading the PHY control register and
2066 * setting/write the control register reset bit to the PHY.
2067 **/
2068s32 igb_phy_sw_reset(struct e1000_hw *hw)
2069{
2070 s32 ret_val = 0;
2071 u16 phy_ctrl;
2072
2073 if (!(hw->phy.ops.read_reg))
2074 goto out;
2075
2076 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2077 if (ret_val)
2078 goto out;
2079
2080 phy_ctrl |= MII_CR_RESET;
2081 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2082 if (ret_val)
2083 goto out;
2084
2085 udelay(1);
2086
2087out:
2088 return ret_val;
2089}
2090
2091/**
2092 * igb_phy_hw_reset - PHY hardware reset
2093 * @hw: pointer to the HW structure
2094 *
2095 * Verify the reset block is not blocking us from resetting. Acquire
2096 * semaphore (if necessary) and read/set/write the device control reset
2097 * bit in the PHY. Wait the appropriate delay time for the device to
2098 * reset and release the semaphore (if necessary).
2099 **/
2100s32 igb_phy_hw_reset(struct e1000_hw *hw)
2101{
2102 struct e1000_phy_info *phy = &hw->phy;
2103 s32 ret_val;
2104 u32 ctrl;
2105
2106 ret_val = igb_check_reset_block(hw);
2107 if (ret_val) {
2108 ret_val = 0;
2109 goto out;
2110 }
2111
2112 ret_val = phy->ops.acquire(hw);
2113 if (ret_val)
2114 goto out;
2115
2116 ctrl = rd32(E1000_CTRL);
2117 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2118 wrfl();
2119
2120 udelay(phy->reset_delay_us);
2121
2122 wr32(E1000_CTRL, ctrl);
2123 wrfl();
2124
2125 udelay(150);
2126
2127 phy->ops.release(hw);
2128
2129 ret_val = phy->ops.get_cfg_done(hw);
2130
2131out:
2132 return ret_val;
2133}
2134
2135/**
2136 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2137 * @hw: pointer to the HW structure
2138 *
2139 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2140 **/
2141s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2142{
2143 hw_dbg("Running IGP 3 PHY init script\n");
2144
2145 /* PHY init IGP 3 */
2146 /* Enable rise/fall, 10-mode work in class-A */
2147 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2148 /* Remove all caps from Replica path filter */
2149 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2150 /* Bias trimming for ADC, AFE and Driver (Default) */
2151 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2152 /* Increase Hybrid poly bias */
2153 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2154 /* Add 4% to TX amplitude in Giga mode */
2155 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2156 /* Disable trimming (TTT) */
2157 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2158 /* Poly DC correction to 94.6% + 2% for all channels */
2159 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2160 /* ABS DC correction to 95.9% */
2161 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2162 /* BG temp curve trim */
2163 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2164 /* Increasing ADC OPAMP stage 1 currents to max */
2165 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2166 /* Force 1000 ( required for enabling PHY regs configuration) */
2167 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2168 /* Set upd_freq to 6 */
2169 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2170 /* Disable NPDFE */
2171 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2172 /* Disable adaptive fixed FFE (Default) */
2173 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2174 /* Enable FFE hysteresis */
2175 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2176 /* Fixed FFE for short cable lengths */
2177 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2178 /* Fixed FFE for medium cable lengths */
2179 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2180 /* Fixed FFE for long cable lengths */
2181 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2182 /* Enable Adaptive Clip Threshold */
2183 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2184 /* AHT reset limit to 1 */
2185 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2186 /* Set AHT master delay to 127 msec */
2187 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2188 /* Set scan bits for AHT */
2189 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2190 /* Set AHT Preset bits */
2191 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2192 /* Change integ_factor of channel A to 3 */
2193 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2194 /* Change prop_factor of channels BCD to 8 */
2195 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2196 /* Change cg_icount + enable integbp for channels BCD */
2197 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2198 /* Change cg_icount + enable integbp + change prop_factor_master
2199 * to 8 for channel A
2200 */
2201 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2202 /* Disable AHT in Slave mode on channel A */
2203 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2204 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2205 * Enable SPD+B2B
2206 */
2207 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2208 /* Enable restart AN on an1000_dis change */
2209 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2210 /* Enable wh_fifo read clock in 10/100 modes */
2211 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2212 /* Restart AN, Speed selection is 1000 */
2213 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2214
2215 return 0;
2216}
2217
2218/**
2219 * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY
2220 * @hw: pointer to the HW structure
2221 *
2222 * Initialize Marvel 1512 to work correctly with Avoton.
2223 **/
2224s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
2225{
2226 struct e1000_phy_info *phy = &hw->phy;
2227 s32 ret_val = 0;
2228
2229 /* Switch to PHY page 0xFF. */
2230 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2231 if (ret_val)
2232 goto out;
2233
2234 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2235 if (ret_val)
2236 goto out;
2237
2238 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2239 if (ret_val)
2240 goto out;
2241
2242 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2243 if (ret_val)
2244 goto out;
2245
2246 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2247 if (ret_val)
2248 goto out;
2249
2250 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2251 if (ret_val)
2252 goto out;
2253
2254 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2255 if (ret_val)
2256 goto out;
2257
2258 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2259 if (ret_val)
2260 goto out;
2261
2262 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2263 if (ret_val)
2264 goto out;
2265
2266 /* Switch to PHY page 0xFB. */
2267 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2268 if (ret_val)
2269 goto out;
2270
2271 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2272 if (ret_val)
2273 goto out;
2274
2275 /* Switch to PHY page 0x12. */
2276 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2277 if (ret_val)
2278 goto out;
2279
2280 /* Change mode to SGMII-to-Copper */
2281 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2282 if (ret_val)
2283 goto out;
2284
2285 /* Return the PHY to page 0. */
2286 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2287 if (ret_val)
2288 goto out;
2289
2290 ret_val = igb_phy_sw_reset(hw);
2291 if (ret_val) {
2292 hw_dbg("Error committing the PHY changes\n");
2293 return ret_val;
2294 }
2295
2296 /* msec_delay(1000); */
2297 usleep_range(1000, 2000);
2298out:
2299 return ret_val;
2300}
2301
2302/**
2303 * igb_initialize_M88E1543_phy - Initialize M88E1512 PHY
2304 * @hw: pointer to the HW structure
2305 *
2306 * Initialize Marvell 1543 to work correctly with Avoton.
2307 **/
2308s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw)
2309{
2310 struct e1000_phy_info *phy = &hw->phy;
2311 s32 ret_val = 0;
2312
2313 /* Switch to PHY page 0xFF. */
2314 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2315 if (ret_val)
2316 goto out;
2317
2318 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2319 if (ret_val)
2320 goto out;
2321
2322 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2323 if (ret_val)
2324 goto out;
2325
2326 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2327 if (ret_val)
2328 goto out;
2329
2330 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2331 if (ret_val)
2332 goto out;
2333
2334 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2335 if (ret_val)
2336 goto out;
2337
2338 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2339 if (ret_val)
2340 goto out;
2341
2342 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2343 if (ret_val)
2344 goto out;
2345
2346 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2347 if (ret_val)
2348 goto out;
2349
2350 /* Switch to PHY page 0xFB. */
2351 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2352 if (ret_val)
2353 goto out;
2354
2355 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D);
2356 if (ret_val)
2357 goto out;
2358
2359 /* Switch to PHY page 0x12. */
2360 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2361 if (ret_val)
2362 goto out;
2363
2364 /* Change mode to SGMII-to-Copper */
2365 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2366 if (ret_val)
2367 goto out;
2368
2369 /* Switch to PHY page 1. */
2370 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2371 if (ret_val)
2372 goto out;
2373
2374 /* Change mode to 1000BASE-X/SGMII and autoneg enable */
2375 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2376 if (ret_val)
2377 goto out;
2378
2379 /* Return the PHY to page 0. */
2380 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2381 if (ret_val)
2382 goto out;
2383
2384 ret_val = igb_phy_sw_reset(hw);
2385 if (ret_val) {
2386 hw_dbg("Error committing the PHY changes\n");
2387 return ret_val;
2388 }
2389
2390 /* msec_delay(1000); */
2391 usleep_range(1000, 2000);
2392out:
2393 return ret_val;
2394}
2395
2396/**
2397 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2398 * @hw: pointer to the HW structure
2399 *
2400 * In the case of a PHY power down to save power, or to turn off link during a
2401 * driver unload, restore the link to previous settings.
2402 **/
2403void igb_power_up_phy_copper(struct e1000_hw *hw)
2404{
2405 u16 mii_reg = 0;
2406
2407 /* The PHY will retain its settings across a power down/up cycle */
2408 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2409 mii_reg &= ~MII_CR_POWER_DOWN;
2410 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2411}
2412
2413/**
2414 * igb_power_down_phy_copper - Power down copper PHY
2415 * @hw: pointer to the HW structure
2416 *
2417 * Power down PHY to save power when interface is down and wake on lan
2418 * is not enabled.
2419 **/
2420void igb_power_down_phy_copper(struct e1000_hw *hw)
2421{
2422 u16 mii_reg = 0;
2423
2424 /* The PHY will retain its settings across a power down/up cycle */
2425 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2426 mii_reg |= MII_CR_POWER_DOWN;
2427 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2428 usleep_range(1000, 2000);
2429}
2430
2431/**
2432 * igb_check_polarity_82580 - Checks the polarity.
2433 * @hw: pointer to the HW structure
2434 *
2435 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2436 *
2437 * Polarity is determined based on the PHY specific status register.
2438 **/
2439static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2440{
2441 struct e1000_phy_info *phy = &hw->phy;
2442 s32 ret_val;
2443 u16 data;
2444
2445
2446 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2447
2448 if (!ret_val)
2449 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2450 ? e1000_rev_polarity_reversed
2451 : e1000_rev_polarity_normal;
2452
2453 return ret_val;
2454}
2455
2456/**
2457 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2458 * @hw: pointer to the HW structure
2459 *
2460 * Calls the PHY setup function to force speed and duplex. Clears the
2461 * auto-crossover to force MDI manually. Waits for link and returns
2462 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2463 **/
2464s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2465{
2466 struct e1000_phy_info *phy = &hw->phy;
2467 s32 ret_val;
2468 u16 phy_data;
2469 bool link;
2470
2471 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2472 if (ret_val)
2473 goto out;
2474
2475 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2476
2477 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2478 if (ret_val)
2479 goto out;
2480
2481 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2482 * forced whenever speed and duplex are forced.
2483 */
2484 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2485 if (ret_val)
2486 goto out;
2487
2488 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2489
2490 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2491 if (ret_val)
2492 goto out;
2493
2494 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2495
2496 udelay(1);
2497
2498 if (phy->autoneg_wait_to_complete) {
2499 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2500
2501 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2502 if (ret_val)
2503 goto out;
2504
2505 if (!link)
2506 hw_dbg("Link taking longer than expected.\n");
2507
2508 /* Try once more */
2509 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2510 if (ret_val)
2511 goto out;
2512 }
2513
2514out:
2515 return ret_val;
2516}
2517
2518/**
2519 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2520 * @hw: pointer to the HW structure
2521 *
2522 * Read PHY status to determine if link is up. If link is up, then
2523 * set/determine 10base-T extended distance and polarity correction. Read
2524 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2525 * determine on the cable length, local and remote receiver.
2526 **/
2527s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2528{
2529 struct e1000_phy_info *phy = &hw->phy;
2530 s32 ret_val;
2531 u16 data;
2532 bool link;
2533
2534 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2535 if (ret_val)
2536 goto out;
2537
2538 if (!link) {
2539 hw_dbg("Phy info is only valid if link is up\n");
2540 ret_val = -E1000_ERR_CONFIG;
2541 goto out;
2542 }
2543
2544 phy->polarity_correction = true;
2545
2546 ret_val = igb_check_polarity_82580(hw);
2547 if (ret_val)
2548 goto out;
2549
2550 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2551 if (ret_val)
2552 goto out;
2553
2554 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2555
2556 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2557 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2558 ret_val = hw->phy.ops.get_cable_length(hw);
2559 if (ret_val)
2560 goto out;
2561
2562 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2563 if (ret_val)
2564 goto out;
2565
2566 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2567 ? e1000_1000t_rx_status_ok
2568 : e1000_1000t_rx_status_not_ok;
2569
2570 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2571 ? e1000_1000t_rx_status_ok
2572 : e1000_1000t_rx_status_not_ok;
2573 } else {
2574 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2575 phy->local_rx = e1000_1000t_rx_status_undefined;
2576 phy->remote_rx = e1000_1000t_rx_status_undefined;
2577 }
2578
2579out:
2580 return ret_val;
2581}
2582
2583/**
2584 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2585 * @hw: pointer to the HW structure
2586 *
2587 * Reads the diagnostic status register and verifies result is valid before
2588 * placing it in the phy_cable_length field.
2589 **/
2590s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2591{
2592 struct e1000_phy_info *phy = &hw->phy;
2593 s32 ret_val;
2594 u16 phy_data, length;
2595
2596 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2597 if (ret_val)
2598 goto out;
2599
2600 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2601 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2602
2603 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2604 ret_val = -E1000_ERR_PHY;
2605
2606 phy->cable_length = length;
2607
2608out:
2609 return ret_val;
2610}
2611
2612/**
2613 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2614 * @hw: pointer to the HW structure
2615 *
2616 * Sets up Master/slave mode
2617 **/
2618static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2619{
2620 s32 ret_val;
2621 u16 phy_data;
2622
2623 /* Resolve Master/Slave mode */
2624 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2625 if (ret_val)
2626 return ret_val;
2627
2628 /* load defaults for future use */
2629 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2630 ((phy_data & CR_1000T_MS_VALUE) ?
2631 e1000_ms_force_master :
2632 e1000_ms_force_slave) : e1000_ms_auto;
2633
2634 switch (hw->phy.ms_type) {
2635 case e1000_ms_force_master:
2636 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2637 break;
2638 case e1000_ms_force_slave:
2639 phy_data |= CR_1000T_MS_ENABLE;
2640 phy_data &= ~(CR_1000T_MS_VALUE);
2641 break;
2642 case e1000_ms_auto:
2643 phy_data &= ~CR_1000T_MS_ENABLE;
2644 /* fall-through */
2645 default:
2646 break;
2647 }
2648
2649 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2650}
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
27#include <linux/if_ether.h>
28#include <linux/delay.h>
29
30#include "e1000_mac.h"
31#include "e1000_phy.h"
32
33static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
34static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
35 u16 *phy_ctrl);
36static s32 igb_wait_autoneg(struct e1000_hw *hw);
37static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
38
39/* Cable length tables */
40static const u16 e1000_m88_cable_length_table[] = {
41 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
42#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
43 (sizeof(e1000_m88_cable_length_table) / \
44 sizeof(e1000_m88_cable_length_table[0]))
45
46static const u16 e1000_igp_2_cable_length_table[] = {
47 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
48 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
49 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
50 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
51 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
52 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
53 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
54 104, 109, 114, 118, 121, 124};
55#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
56 (sizeof(e1000_igp_2_cable_length_table) / \
57 sizeof(e1000_igp_2_cable_length_table[0]))
58
59/**
60 * igb_check_reset_block - Check if PHY reset is blocked
61 * @hw: pointer to the HW structure
62 *
63 * Read the PHY management control register and check whether a PHY reset
64 * is blocked. If a reset is not blocked return 0, otherwise
65 * return E1000_BLK_PHY_RESET (12).
66 **/
67s32 igb_check_reset_block(struct e1000_hw *hw)
68{
69 u32 manc;
70
71 manc = rd32(E1000_MANC);
72
73 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
74}
75
76/**
77 * igb_get_phy_id - Retrieve the PHY ID and revision
78 * @hw: pointer to the HW structure
79 *
80 * Reads the PHY registers and stores the PHY ID and possibly the PHY
81 * revision in the hardware structure.
82 **/
83s32 igb_get_phy_id(struct e1000_hw *hw)
84{
85 struct e1000_phy_info *phy = &hw->phy;
86 s32 ret_val = 0;
87 u16 phy_id;
88
89 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
90 if (ret_val)
91 goto out;
92
93 phy->id = (u32)(phy_id << 16);
94 udelay(20);
95 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
96 if (ret_val)
97 goto out;
98
99 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
100 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
101
102out:
103 return ret_val;
104}
105
106/**
107 * igb_phy_reset_dsp - Reset PHY DSP
108 * @hw: pointer to the HW structure
109 *
110 * Reset the digital signal processor.
111 **/
112static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
113{
114 s32 ret_val = 0;
115
116 if (!(hw->phy.ops.write_reg))
117 goto out;
118
119 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
120 if (ret_val)
121 goto out;
122
123 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
124
125out:
126 return ret_val;
127}
128
129/**
130 * igb_read_phy_reg_mdic - Read MDI control register
131 * @hw: pointer to the HW structure
132 * @offset: register offset to be read
133 * @data: pointer to the read data
134 *
135 * Reads the MDI control regsiter in the PHY at offset and stores the
136 * information read to data.
137 **/
138s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
139{
140 struct e1000_phy_info *phy = &hw->phy;
141 u32 i, mdic = 0;
142 s32 ret_val = 0;
143
144 if (offset > MAX_PHY_REG_ADDRESS) {
145 hw_dbg("PHY Address %d is out of range\n", offset);
146 ret_val = -E1000_ERR_PARAM;
147 goto out;
148 }
149
150 /* Set up Op-code, Phy Address, and register offset in the MDI
151 * Control register. The MAC will take care of interfacing with the
152 * PHY to retrieve the desired data.
153 */
154 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
155 (phy->addr << E1000_MDIC_PHY_SHIFT) |
156 (E1000_MDIC_OP_READ));
157
158 wr32(E1000_MDIC, mdic);
159
160 /* Poll the ready bit to see if the MDI read completed
161 * Increasing the time out as testing showed failures with
162 * the lower time out
163 */
164 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
165 udelay(50);
166 mdic = rd32(E1000_MDIC);
167 if (mdic & E1000_MDIC_READY)
168 break;
169 }
170 if (!(mdic & E1000_MDIC_READY)) {
171 hw_dbg("MDI Read did not complete\n");
172 ret_val = -E1000_ERR_PHY;
173 goto out;
174 }
175 if (mdic & E1000_MDIC_ERROR) {
176 hw_dbg("MDI Error\n");
177 ret_val = -E1000_ERR_PHY;
178 goto out;
179 }
180 *data = (u16) mdic;
181
182out:
183 return ret_val;
184}
185
186/**
187 * igb_write_phy_reg_mdic - Write MDI control register
188 * @hw: pointer to the HW structure
189 * @offset: register offset to write to
190 * @data: data to write to register at offset
191 *
192 * Writes data to MDI control register in the PHY at offset.
193 **/
194s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
195{
196 struct e1000_phy_info *phy = &hw->phy;
197 u32 i, mdic = 0;
198 s32 ret_val = 0;
199
200 if (offset > MAX_PHY_REG_ADDRESS) {
201 hw_dbg("PHY Address %d is out of range\n", offset);
202 ret_val = -E1000_ERR_PARAM;
203 goto out;
204 }
205
206 /* Set up Op-code, Phy Address, and register offset in the MDI
207 * Control register. The MAC will take care of interfacing with the
208 * PHY to retrieve the desired data.
209 */
210 mdic = (((u32)data) |
211 (offset << E1000_MDIC_REG_SHIFT) |
212 (phy->addr << E1000_MDIC_PHY_SHIFT) |
213 (E1000_MDIC_OP_WRITE));
214
215 wr32(E1000_MDIC, mdic);
216
217 /* Poll the ready bit to see if the MDI read completed
218 * Increasing the time out as testing showed failures with
219 * the lower time out
220 */
221 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
222 udelay(50);
223 mdic = rd32(E1000_MDIC);
224 if (mdic & E1000_MDIC_READY)
225 break;
226 }
227 if (!(mdic & E1000_MDIC_READY)) {
228 hw_dbg("MDI Write did not complete\n");
229 ret_val = -E1000_ERR_PHY;
230 goto out;
231 }
232 if (mdic & E1000_MDIC_ERROR) {
233 hw_dbg("MDI Error\n");
234 ret_val = -E1000_ERR_PHY;
235 goto out;
236 }
237
238out:
239 return ret_val;
240}
241
242/**
243 * igb_read_phy_reg_i2c - Read PHY register using i2c
244 * @hw: pointer to the HW structure
245 * @offset: register offset to be read
246 * @data: pointer to the read data
247 *
248 * Reads the PHY register at offset using the i2c interface and stores the
249 * retrieved information in data.
250 **/
251s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
252{
253 struct e1000_phy_info *phy = &hw->phy;
254 u32 i, i2ccmd = 0;
255
256 /* Set up Op-code, Phy Address, and register address in the I2CCMD
257 * register. The MAC will take care of interfacing with the
258 * PHY to retrieve the desired data.
259 */
260 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
261 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
262 (E1000_I2CCMD_OPCODE_READ));
263
264 wr32(E1000_I2CCMD, i2ccmd);
265
266 /* Poll the ready bit to see if the I2C read completed */
267 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
268 udelay(50);
269 i2ccmd = rd32(E1000_I2CCMD);
270 if (i2ccmd & E1000_I2CCMD_READY)
271 break;
272 }
273 if (!(i2ccmd & E1000_I2CCMD_READY)) {
274 hw_dbg("I2CCMD Read did not complete\n");
275 return -E1000_ERR_PHY;
276 }
277 if (i2ccmd & E1000_I2CCMD_ERROR) {
278 hw_dbg("I2CCMD Error bit set\n");
279 return -E1000_ERR_PHY;
280 }
281
282 /* Need to byte-swap the 16-bit value. */
283 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
284
285 return 0;
286}
287
288/**
289 * igb_write_phy_reg_i2c - Write PHY register using i2c
290 * @hw: pointer to the HW structure
291 * @offset: register offset to write to
292 * @data: data to write at register offset
293 *
294 * Writes the data to PHY register at the offset using the i2c interface.
295 **/
296s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
297{
298 struct e1000_phy_info *phy = &hw->phy;
299 u32 i, i2ccmd = 0;
300 u16 phy_data_swapped;
301
302 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
303 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
304 hw_dbg("PHY I2C Address %d is out of range.\n",
305 hw->phy.addr);
306 return -E1000_ERR_CONFIG;
307 }
308
309 /* Swap the data bytes for the I2C interface */
310 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
311
312 /* Set up Op-code, Phy Address, and register address in the I2CCMD
313 * register. The MAC will take care of interfacing with the
314 * PHY to retrieve the desired data.
315 */
316 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
317 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
318 E1000_I2CCMD_OPCODE_WRITE |
319 phy_data_swapped);
320
321 wr32(E1000_I2CCMD, i2ccmd);
322
323 /* Poll the ready bit to see if the I2C read completed */
324 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
325 udelay(50);
326 i2ccmd = rd32(E1000_I2CCMD);
327 if (i2ccmd & E1000_I2CCMD_READY)
328 break;
329 }
330 if (!(i2ccmd & E1000_I2CCMD_READY)) {
331 hw_dbg("I2CCMD Write did not complete\n");
332 return -E1000_ERR_PHY;
333 }
334 if (i2ccmd & E1000_I2CCMD_ERROR) {
335 hw_dbg("I2CCMD Error bit set\n");
336 return -E1000_ERR_PHY;
337 }
338
339 return 0;
340}
341
342/**
343 * igb_read_sfp_data_byte - Reads SFP module data.
344 * @hw: pointer to the HW structure
345 * @offset: byte location offset to be read
346 * @data: read data buffer pointer
347 *
348 * Reads one byte from SFP module data stored
349 * in SFP resided EEPROM memory or SFP diagnostic area.
350 * Function should be called with
351 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
352 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
353 * access
354 **/
355s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
356{
357 u32 i = 0;
358 u32 i2ccmd = 0;
359 u32 data_local = 0;
360
361 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
362 hw_dbg("I2CCMD command address exceeds upper limit\n");
363 return -E1000_ERR_PHY;
364 }
365
366 /* Set up Op-code, EEPROM Address,in the I2CCMD
367 * register. The MAC will take care of interfacing with the
368 * EEPROM to retrieve the desired data.
369 */
370 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
371 E1000_I2CCMD_OPCODE_READ);
372
373 wr32(E1000_I2CCMD, i2ccmd);
374
375 /* Poll the ready bit to see if the I2C read completed */
376 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
377 udelay(50);
378 data_local = rd32(E1000_I2CCMD);
379 if (data_local & E1000_I2CCMD_READY)
380 break;
381 }
382 if (!(data_local & E1000_I2CCMD_READY)) {
383 hw_dbg("I2CCMD Read did not complete\n");
384 return -E1000_ERR_PHY;
385 }
386 if (data_local & E1000_I2CCMD_ERROR) {
387 hw_dbg("I2CCMD Error bit set\n");
388 return -E1000_ERR_PHY;
389 }
390 *data = (u8) data_local & 0xFF;
391
392 return 0;
393}
394
395/**
396 * igb_read_phy_reg_igp - Read igp PHY register
397 * @hw: pointer to the HW structure
398 * @offset: register offset to be read
399 * @data: pointer to the read data
400 *
401 * Acquires semaphore, if necessary, then reads the PHY register at offset
402 * and storing the retrieved information in data. Release any acquired
403 * semaphores before exiting.
404 **/
405s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
406{
407 s32 ret_val = 0;
408
409 if (!(hw->phy.ops.acquire))
410 goto out;
411
412 ret_val = hw->phy.ops.acquire(hw);
413 if (ret_val)
414 goto out;
415
416 if (offset > MAX_PHY_MULTI_PAGE_REG) {
417 ret_val = igb_write_phy_reg_mdic(hw,
418 IGP01E1000_PHY_PAGE_SELECT,
419 (u16)offset);
420 if (ret_val) {
421 hw->phy.ops.release(hw);
422 goto out;
423 }
424 }
425
426 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
427 data);
428
429 hw->phy.ops.release(hw);
430
431out:
432 return ret_val;
433}
434
435/**
436 * igb_write_phy_reg_igp - Write igp PHY register
437 * @hw: pointer to the HW structure
438 * @offset: register offset to write to
439 * @data: data to write at register offset
440 *
441 * Acquires semaphore, if necessary, then writes the data to PHY register
442 * at the offset. Release any acquired semaphores before exiting.
443 **/
444s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
445{
446 s32 ret_val = 0;
447
448 if (!(hw->phy.ops.acquire))
449 goto out;
450
451 ret_val = hw->phy.ops.acquire(hw);
452 if (ret_val)
453 goto out;
454
455 if (offset > MAX_PHY_MULTI_PAGE_REG) {
456 ret_val = igb_write_phy_reg_mdic(hw,
457 IGP01E1000_PHY_PAGE_SELECT,
458 (u16)offset);
459 if (ret_val) {
460 hw->phy.ops.release(hw);
461 goto out;
462 }
463 }
464
465 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
466 data);
467
468 hw->phy.ops.release(hw);
469
470out:
471 return ret_val;
472}
473
474/**
475 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
476 * @hw: pointer to the HW structure
477 *
478 * Sets up Carrier-sense on Transmit and downshift values.
479 **/
480s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
481{
482 struct e1000_phy_info *phy = &hw->phy;
483 s32 ret_val;
484 u16 phy_data;
485
486 if (phy->reset_disable) {
487 ret_val = 0;
488 goto out;
489 }
490
491 if (phy->type == e1000_phy_82580) {
492 ret_val = hw->phy.ops.reset(hw);
493 if (ret_val) {
494 hw_dbg("Error resetting the PHY.\n");
495 goto out;
496 }
497 }
498
499 /* Enable CRS on TX. This must be set for half-duplex operation. */
500 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
501 if (ret_val)
502 goto out;
503
504 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
505
506 /* Enable downshift */
507 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
508
509 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
510 if (ret_val)
511 goto out;
512
513 /* Set MDI/MDIX mode */
514 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
515 if (ret_val)
516 goto out;
517 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
518 /* Options:
519 * 0 - Auto (default)
520 * 1 - MDI mode
521 * 2 - MDI-X mode
522 */
523 switch (hw->phy.mdix) {
524 case 1:
525 break;
526 case 2:
527 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
528 break;
529 case 0:
530 default:
531 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
532 break;
533 }
534 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
535
536out:
537 return ret_val;
538}
539
540/**
541 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
542 * @hw: pointer to the HW structure
543 *
544 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
545 * and downshift values are set also.
546 **/
547s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
548{
549 struct e1000_phy_info *phy = &hw->phy;
550 s32 ret_val;
551 u16 phy_data;
552
553 if (phy->reset_disable) {
554 ret_val = 0;
555 goto out;
556 }
557
558 /* Enable CRS on TX. This must be set for half-duplex operation. */
559 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
560 if (ret_val)
561 goto out;
562
563 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
564
565 /* Options:
566 * MDI/MDI-X = 0 (default)
567 * 0 - Auto for all speeds
568 * 1 - MDI mode
569 * 2 - MDI-X mode
570 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
571 */
572 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
573
574 switch (phy->mdix) {
575 case 1:
576 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
577 break;
578 case 2:
579 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
580 break;
581 case 3:
582 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
583 break;
584 case 0:
585 default:
586 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
587 break;
588 }
589
590 /* Options:
591 * disable_polarity_correction = 0 (default)
592 * Automatic Correction for Reversed Cable Polarity
593 * 0 - Disabled
594 * 1 - Enabled
595 */
596 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
597 if (phy->disable_polarity_correction == 1)
598 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
599
600 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
601 if (ret_val)
602 goto out;
603
604 if (phy->revision < E1000_REVISION_4) {
605 /* Force TX_CLK in the Extended PHY Specific Control Register
606 * to 25MHz clock.
607 */
608 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
609 &phy_data);
610 if (ret_val)
611 goto out;
612
613 phy_data |= M88E1000_EPSCR_TX_CLK_25;
614
615 if ((phy->revision == E1000_REVISION_2) &&
616 (phy->id == M88E1111_I_PHY_ID)) {
617 /* 82573L PHY - set the downshift counter to 5x. */
618 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
619 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
620 } else {
621 /* Configure Master and Slave downshift values */
622 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
623 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
624 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
625 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
626 }
627 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
628 phy_data);
629 if (ret_val)
630 goto out;
631 }
632
633 /* Commit the changes. */
634 ret_val = igb_phy_sw_reset(hw);
635 if (ret_val) {
636 hw_dbg("Error committing the PHY changes\n");
637 goto out;
638 }
639
640out:
641 return ret_val;
642}
643
644/**
645 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
646 * @hw: pointer to the HW structure
647 *
648 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
649 * Also enables and sets the downshift parameters.
650 **/
651s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
652{
653 struct e1000_phy_info *phy = &hw->phy;
654 s32 ret_val;
655 u16 phy_data;
656
657 if (phy->reset_disable)
658 return 0;
659
660 /* Enable CRS on Tx. This must be set for half-duplex operation. */
661 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
662 if (ret_val)
663 return ret_val;
664
665 /* Options:
666 * MDI/MDI-X = 0 (default)
667 * 0 - Auto for all speeds
668 * 1 - MDI mode
669 * 2 - MDI-X mode
670 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
671 */
672 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
673
674 switch (phy->mdix) {
675 case 1:
676 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
677 break;
678 case 2:
679 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
680 break;
681 case 3:
682 /* M88E1112 does not support this mode) */
683 if (phy->id != M88E1112_E_PHY_ID) {
684 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
685 break;
686 }
687 case 0:
688 default:
689 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
690 break;
691 }
692
693 /* Options:
694 * disable_polarity_correction = 0 (default)
695 * Automatic Correction for Reversed Cable Polarity
696 * 0 - Disabled
697 * 1 - Enabled
698 */
699 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
700 if (phy->disable_polarity_correction == 1)
701 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
702
703 /* Enable downshift and setting it to X6 */
704 if (phy->id == M88E1543_E_PHY_ID) {
705 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
706 ret_val =
707 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
708 if (ret_val)
709 return ret_val;
710
711 ret_val = igb_phy_sw_reset(hw);
712 if (ret_val) {
713 hw_dbg("Error committing the PHY changes\n");
714 return ret_val;
715 }
716 }
717
718 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
719 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
720 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
721
722 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
723 if (ret_val)
724 return ret_val;
725
726 /* Commit the changes. */
727 ret_val = igb_phy_sw_reset(hw);
728 if (ret_val) {
729 hw_dbg("Error committing the PHY changes\n");
730 return ret_val;
731 }
732 ret_val = igb_set_master_slave_mode(hw);
733 if (ret_val)
734 return ret_val;
735
736 return 0;
737}
738
739/**
740 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
741 * @hw: pointer to the HW structure
742 *
743 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
744 * igp PHY's.
745 **/
746s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
747{
748 struct e1000_phy_info *phy = &hw->phy;
749 s32 ret_val;
750 u16 data;
751
752 if (phy->reset_disable) {
753 ret_val = 0;
754 goto out;
755 }
756
757 ret_val = phy->ops.reset(hw);
758 if (ret_val) {
759 hw_dbg("Error resetting the PHY.\n");
760 goto out;
761 }
762
763 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
764 * timeout issues when LFS is enabled.
765 */
766 msleep(100);
767
768 /* The NVM settings will configure LPLU in D3 for
769 * non-IGP1 PHYs.
770 */
771 if (phy->type == e1000_phy_igp) {
772 /* disable lplu d3 during driver init */
773 if (phy->ops.set_d3_lplu_state)
774 ret_val = phy->ops.set_d3_lplu_state(hw, false);
775 if (ret_val) {
776 hw_dbg("Error Disabling LPLU D3\n");
777 goto out;
778 }
779 }
780
781 /* disable lplu d0 during driver init */
782 ret_val = phy->ops.set_d0_lplu_state(hw, false);
783 if (ret_val) {
784 hw_dbg("Error Disabling LPLU D0\n");
785 goto out;
786 }
787 /* Configure mdi-mdix settings */
788 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
789 if (ret_val)
790 goto out;
791
792 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
793
794 switch (phy->mdix) {
795 case 1:
796 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
797 break;
798 case 2:
799 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
800 break;
801 case 0:
802 default:
803 data |= IGP01E1000_PSCR_AUTO_MDIX;
804 break;
805 }
806 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
807 if (ret_val)
808 goto out;
809
810 /* set auto-master slave resolution settings */
811 if (hw->mac.autoneg) {
812 /* when autonegotiation advertisement is only 1000Mbps then we
813 * should disable SmartSpeed and enable Auto MasterSlave
814 * resolution as hardware default.
815 */
816 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
817 /* Disable SmartSpeed */
818 ret_val = phy->ops.read_reg(hw,
819 IGP01E1000_PHY_PORT_CONFIG,
820 &data);
821 if (ret_val)
822 goto out;
823
824 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
825 ret_val = phy->ops.write_reg(hw,
826 IGP01E1000_PHY_PORT_CONFIG,
827 data);
828 if (ret_val)
829 goto out;
830
831 /* Set auto Master/Slave resolution process */
832 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
833 if (ret_val)
834 goto out;
835
836 data &= ~CR_1000T_MS_ENABLE;
837 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
838 if (ret_val)
839 goto out;
840 }
841
842 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
843 if (ret_val)
844 goto out;
845
846 /* load defaults for future use */
847 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
848 ((data & CR_1000T_MS_VALUE) ?
849 e1000_ms_force_master :
850 e1000_ms_force_slave) :
851 e1000_ms_auto;
852
853 switch (phy->ms_type) {
854 case e1000_ms_force_master:
855 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
856 break;
857 case e1000_ms_force_slave:
858 data |= CR_1000T_MS_ENABLE;
859 data &= ~(CR_1000T_MS_VALUE);
860 break;
861 case e1000_ms_auto:
862 data &= ~CR_1000T_MS_ENABLE;
863 default:
864 break;
865 }
866 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
867 if (ret_val)
868 goto out;
869 }
870
871out:
872 return ret_val;
873}
874
875/**
876 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
877 * @hw: pointer to the HW structure
878 *
879 * Performs initial bounds checking on autoneg advertisement parameter, then
880 * configure to advertise the full capability. Setup the PHY to autoneg
881 * and restart the negotiation process between the link partner. If
882 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
883 **/
884static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
885{
886 struct e1000_phy_info *phy = &hw->phy;
887 s32 ret_val;
888 u16 phy_ctrl;
889
890 /* Perform some bounds checking on the autoneg advertisement
891 * parameter.
892 */
893 phy->autoneg_advertised &= phy->autoneg_mask;
894
895 /* If autoneg_advertised is zero, we assume it was not defaulted
896 * by the calling code so we set to advertise full capability.
897 */
898 if (phy->autoneg_advertised == 0)
899 phy->autoneg_advertised = phy->autoneg_mask;
900
901 hw_dbg("Reconfiguring auto-neg advertisement params\n");
902 ret_val = igb_phy_setup_autoneg(hw);
903 if (ret_val) {
904 hw_dbg("Error Setting up Auto-Negotiation\n");
905 goto out;
906 }
907 hw_dbg("Restarting Auto-Neg\n");
908
909 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
910 * the Auto Neg Restart bit in the PHY control register.
911 */
912 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
913 if (ret_val)
914 goto out;
915
916 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
917 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
918 if (ret_val)
919 goto out;
920
921 /* Does the user want to wait for Auto-Neg to complete here, or
922 * check at a later time (for example, callback routine).
923 */
924 if (phy->autoneg_wait_to_complete) {
925 ret_val = igb_wait_autoneg(hw);
926 if (ret_val) {
927 hw_dbg("Error while waiting for "
928 "autoneg to complete\n");
929 goto out;
930 }
931 }
932
933 hw->mac.get_link_status = true;
934
935out:
936 return ret_val;
937}
938
939/**
940 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
941 * @hw: pointer to the HW structure
942 *
943 * Reads the MII auto-neg advertisement register and/or the 1000T control
944 * register and if the PHY is already setup for auto-negotiation, then
945 * return successful. Otherwise, setup advertisement and flow control to
946 * the appropriate values for the wanted auto-negotiation.
947 **/
948static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
949{
950 struct e1000_phy_info *phy = &hw->phy;
951 s32 ret_val;
952 u16 mii_autoneg_adv_reg;
953 u16 mii_1000t_ctrl_reg = 0;
954
955 phy->autoneg_advertised &= phy->autoneg_mask;
956
957 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
958 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
959 if (ret_val)
960 goto out;
961
962 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
963 /* Read the MII 1000Base-T Control Register (Address 9). */
964 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
965 &mii_1000t_ctrl_reg);
966 if (ret_val)
967 goto out;
968 }
969
970 /* Need to parse both autoneg_advertised and fc and set up
971 * the appropriate PHY registers. First we will parse for
972 * autoneg_advertised software override. Since we can advertise
973 * a plethora of combinations, we need to check each bit
974 * individually.
975 */
976
977 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
978 * Advertisement Register (Address 4) and the 1000 mb speed bits in
979 * the 1000Base-T Control Register (Address 9).
980 */
981 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
982 NWAY_AR_100TX_HD_CAPS |
983 NWAY_AR_10T_FD_CAPS |
984 NWAY_AR_10T_HD_CAPS);
985 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
986
987 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
988
989 /* Do we want to advertise 10 Mb Half Duplex? */
990 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
991 hw_dbg("Advertise 10mb Half duplex\n");
992 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
993 }
994
995 /* Do we want to advertise 10 Mb Full Duplex? */
996 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
997 hw_dbg("Advertise 10mb Full duplex\n");
998 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
999 }
1000
1001 /* Do we want to advertise 100 Mb Half Duplex? */
1002 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1003 hw_dbg("Advertise 100mb Half duplex\n");
1004 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1005 }
1006
1007 /* Do we want to advertise 100 Mb Full Duplex? */
1008 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1009 hw_dbg("Advertise 100mb Full duplex\n");
1010 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1011 }
1012
1013 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1014 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1015 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1016
1017 /* Do we want to advertise 1000 Mb Full Duplex? */
1018 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1019 hw_dbg("Advertise 1000mb Full duplex\n");
1020 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1021 }
1022
1023 /* Check for a software override of the flow control settings, and
1024 * setup the PHY advertisement registers accordingly. If
1025 * auto-negotiation is enabled, then software will have to set the
1026 * "PAUSE" bits to the correct value in the Auto-Negotiation
1027 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1028 * negotiation.
1029 *
1030 * The possible values of the "fc" parameter are:
1031 * 0: Flow control is completely disabled
1032 * 1: Rx flow control is enabled (we can receive pause frames
1033 * but not send pause frames).
1034 * 2: Tx flow control is enabled (we can send pause frames
1035 * but we do not support receiving pause frames).
1036 * 3: Both Rx and TX flow control (symmetric) are enabled.
1037 * other: No software override. The flow control configuration
1038 * in the EEPROM is used.
1039 */
1040 switch (hw->fc.current_mode) {
1041 case e1000_fc_none:
1042 /* Flow control (RX & TX) is completely disabled by a
1043 * software over-ride.
1044 */
1045 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1046 break;
1047 case e1000_fc_rx_pause:
1048 /* RX Flow control is enabled, and TX Flow control is
1049 * disabled, by a software over-ride.
1050 *
1051 * Since there really isn't a way to advertise that we are
1052 * capable of RX Pause ONLY, we will advertise that we
1053 * support both symmetric and asymmetric RX PAUSE. Later
1054 * (in e1000_config_fc_after_link_up) we will disable the
1055 * hw's ability to send PAUSE frames.
1056 */
1057 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1058 break;
1059 case e1000_fc_tx_pause:
1060 /* TX Flow control is enabled, and RX Flow control is
1061 * disabled, by a software over-ride.
1062 */
1063 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1064 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1065 break;
1066 case e1000_fc_full:
1067 /* Flow control (both RX and TX) is enabled by a software
1068 * over-ride.
1069 */
1070 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1071 break;
1072 default:
1073 hw_dbg("Flow control param set incorrectly\n");
1074 ret_val = -E1000_ERR_CONFIG;
1075 goto out;
1076 }
1077
1078 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1079 if (ret_val)
1080 goto out;
1081
1082 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1083
1084 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1085 ret_val = phy->ops.write_reg(hw,
1086 PHY_1000T_CTRL,
1087 mii_1000t_ctrl_reg);
1088 if (ret_val)
1089 goto out;
1090 }
1091
1092out:
1093 return ret_val;
1094}
1095
1096/**
1097 * igb_setup_copper_link - Configure copper link settings
1098 * @hw: pointer to the HW structure
1099 *
1100 * Calls the appropriate function to configure the link for auto-neg or forced
1101 * speed and duplex. Then we check for link, once link is established calls
1102 * to configure collision distance and flow control are called. If link is
1103 * not established, we return -E1000_ERR_PHY (-2).
1104 **/
1105s32 igb_setup_copper_link(struct e1000_hw *hw)
1106{
1107 s32 ret_val;
1108 bool link;
1109
1110 if (hw->mac.autoneg) {
1111 /* Setup autoneg and flow control advertisement and perform
1112 * autonegotiation.
1113 */
1114 ret_val = igb_copper_link_autoneg(hw);
1115 if (ret_val)
1116 goto out;
1117 } else {
1118 /* PHY will be set to 10H, 10F, 100H or 100F
1119 * depending on user settings.
1120 */
1121 hw_dbg("Forcing Speed and Duplex\n");
1122 ret_val = hw->phy.ops.force_speed_duplex(hw);
1123 if (ret_val) {
1124 hw_dbg("Error Forcing Speed and Duplex\n");
1125 goto out;
1126 }
1127 }
1128
1129 /* Check link status. Wait up to 100 microseconds for link to become
1130 * valid.
1131 */
1132 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1133 if (ret_val)
1134 goto out;
1135
1136 if (link) {
1137 hw_dbg("Valid link established!!!\n");
1138 igb_config_collision_dist(hw);
1139 ret_val = igb_config_fc_after_link_up(hw);
1140 } else {
1141 hw_dbg("Unable to establish link!!!\n");
1142 }
1143
1144out:
1145 return ret_val;
1146}
1147
1148/**
1149 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1150 * @hw: pointer to the HW structure
1151 *
1152 * Calls the PHY setup function to force speed and duplex. Clears the
1153 * auto-crossover to force MDI manually. Waits for link and returns
1154 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1155 **/
1156s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1157{
1158 struct e1000_phy_info *phy = &hw->phy;
1159 s32 ret_val;
1160 u16 phy_data;
1161 bool link;
1162
1163 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1164 if (ret_val)
1165 goto out;
1166
1167 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1168
1169 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1170 if (ret_val)
1171 goto out;
1172
1173 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1174 * forced whenever speed and duplex are forced.
1175 */
1176 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1177 if (ret_val)
1178 goto out;
1179
1180 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1181 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1182
1183 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1184 if (ret_val)
1185 goto out;
1186
1187 hw_dbg("IGP PSCR: %X\n", phy_data);
1188
1189 udelay(1);
1190
1191 if (phy->autoneg_wait_to_complete) {
1192 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1193
1194 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1195 if (ret_val)
1196 goto out;
1197
1198 if (!link)
1199 hw_dbg("Link taking longer than expected.\n");
1200
1201 /* Try once more */
1202 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1203 if (ret_val)
1204 goto out;
1205 }
1206
1207out:
1208 return ret_val;
1209}
1210
1211/**
1212 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1213 * @hw: pointer to the HW structure
1214 *
1215 * Calls the PHY setup function to force speed and duplex. Clears the
1216 * auto-crossover to force MDI manually. Resets the PHY to commit the
1217 * changes. If time expires while waiting for link up, we reset the DSP.
1218 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1219 * successful completion, else return corresponding error code.
1220 **/
1221s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1222{
1223 struct e1000_phy_info *phy = &hw->phy;
1224 s32 ret_val;
1225 u16 phy_data;
1226 bool link;
1227
1228 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1229 if (phy->type != e1000_phy_i210) {
1230 /* Clear Auto-Crossover to force MDI manually. M88E1000
1231 * requires MDI forced whenever speed and duplex are forced.
1232 */
1233 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1234 &phy_data);
1235 if (ret_val)
1236 goto out;
1237
1238 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1239 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1240 phy_data);
1241 if (ret_val)
1242 goto out;
1243
1244 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1245 }
1246
1247 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1248 if (ret_val)
1249 goto out;
1250
1251 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1252
1253 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1254 if (ret_val)
1255 goto out;
1256
1257 /* Reset the phy to commit changes. */
1258 ret_val = igb_phy_sw_reset(hw);
1259 if (ret_val)
1260 goto out;
1261
1262 if (phy->autoneg_wait_to_complete) {
1263 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1264
1265 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1266 if (ret_val)
1267 goto out;
1268
1269 if (!link) {
1270 bool reset_dsp = true;
1271
1272 switch (hw->phy.id) {
1273 case I347AT4_E_PHY_ID:
1274 case M88E1112_E_PHY_ID:
1275 case I210_I_PHY_ID:
1276 reset_dsp = false;
1277 break;
1278 default:
1279 if (hw->phy.type != e1000_phy_m88)
1280 reset_dsp = false;
1281 break;
1282 }
1283 if (!reset_dsp)
1284 hw_dbg("Link taking longer than expected.\n");
1285 else {
1286 /* We didn't get link.
1287 * Reset the DSP and cross our fingers.
1288 */
1289 ret_val = phy->ops.write_reg(hw,
1290 M88E1000_PHY_PAGE_SELECT,
1291 0x001d);
1292 if (ret_val)
1293 goto out;
1294 ret_val = igb_phy_reset_dsp(hw);
1295 if (ret_val)
1296 goto out;
1297 }
1298 }
1299
1300 /* Try once more */
1301 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1302 100000, &link);
1303 if (ret_val)
1304 goto out;
1305 }
1306
1307 if (hw->phy.type != e1000_phy_m88 ||
1308 hw->phy.id == I347AT4_E_PHY_ID ||
1309 hw->phy.id == M88E1112_E_PHY_ID ||
1310 hw->phy.id == I210_I_PHY_ID)
1311 goto out;
1312
1313 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1314 if (ret_val)
1315 goto out;
1316
1317 /* Resetting the phy means we need to re-force TX_CLK in the
1318 * Extended PHY Specific Control Register to 25MHz clock from
1319 * the reset value of 2.5MHz.
1320 */
1321 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1322 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1323 if (ret_val)
1324 goto out;
1325
1326 /* In addition, we must re-enable CRS on Tx for both half and full
1327 * duplex.
1328 */
1329 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1330 if (ret_val)
1331 goto out;
1332
1333 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1334 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1335
1336out:
1337 return ret_val;
1338}
1339
1340/**
1341 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1342 * @hw: pointer to the HW structure
1343 * @phy_ctrl: pointer to current value of PHY_CONTROL
1344 *
1345 * Forces speed and duplex on the PHY by doing the following: disable flow
1346 * control, force speed/duplex on the MAC, disable auto speed detection,
1347 * disable auto-negotiation, configure duplex, configure speed, configure
1348 * the collision distance, write configuration to CTRL register. The
1349 * caller must write to the PHY_CONTROL register for these settings to
1350 * take affect.
1351 **/
1352static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1353 u16 *phy_ctrl)
1354{
1355 struct e1000_mac_info *mac = &hw->mac;
1356 u32 ctrl;
1357
1358 /* Turn off flow control when forcing speed/duplex */
1359 hw->fc.current_mode = e1000_fc_none;
1360
1361 /* Force speed/duplex on the mac */
1362 ctrl = rd32(E1000_CTRL);
1363 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1364 ctrl &= ~E1000_CTRL_SPD_SEL;
1365
1366 /* Disable Auto Speed Detection */
1367 ctrl &= ~E1000_CTRL_ASDE;
1368
1369 /* Disable autoneg on the phy */
1370 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1371
1372 /* Forcing Full or Half Duplex? */
1373 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1374 ctrl &= ~E1000_CTRL_FD;
1375 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1376 hw_dbg("Half Duplex\n");
1377 } else {
1378 ctrl |= E1000_CTRL_FD;
1379 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1380 hw_dbg("Full Duplex\n");
1381 }
1382
1383 /* Forcing 10mb or 100mb? */
1384 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1385 ctrl |= E1000_CTRL_SPD_100;
1386 *phy_ctrl |= MII_CR_SPEED_100;
1387 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1388 hw_dbg("Forcing 100mb\n");
1389 } else {
1390 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1391 *phy_ctrl |= MII_CR_SPEED_10;
1392 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1393 hw_dbg("Forcing 10mb\n");
1394 }
1395
1396 igb_config_collision_dist(hw);
1397
1398 wr32(E1000_CTRL, ctrl);
1399}
1400
1401/**
1402 * igb_set_d3_lplu_state - Sets low power link up state for D3
1403 * @hw: pointer to the HW structure
1404 * @active: boolean used to enable/disable lplu
1405 *
1406 * Success returns 0, Failure returns 1
1407 *
1408 * The low power link up (lplu) state is set to the power management level D3
1409 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1410 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1411 * is used during Dx states where the power conservation is most important.
1412 * During driver activity, SmartSpeed should be enabled so performance is
1413 * maintained.
1414 **/
1415s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1416{
1417 struct e1000_phy_info *phy = &hw->phy;
1418 s32 ret_val = 0;
1419 u16 data;
1420
1421 if (!(hw->phy.ops.read_reg))
1422 goto out;
1423
1424 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1425 if (ret_val)
1426 goto out;
1427
1428 if (!active) {
1429 data &= ~IGP02E1000_PM_D3_LPLU;
1430 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1431 data);
1432 if (ret_val)
1433 goto out;
1434 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1435 * during Dx states where the power conservation is most
1436 * important. During driver activity we should enable
1437 * SmartSpeed, so performance is maintained.
1438 */
1439 if (phy->smart_speed == e1000_smart_speed_on) {
1440 ret_val = phy->ops.read_reg(hw,
1441 IGP01E1000_PHY_PORT_CONFIG,
1442 &data);
1443 if (ret_val)
1444 goto out;
1445
1446 data |= IGP01E1000_PSCFR_SMART_SPEED;
1447 ret_val = phy->ops.write_reg(hw,
1448 IGP01E1000_PHY_PORT_CONFIG,
1449 data);
1450 if (ret_val)
1451 goto out;
1452 } else if (phy->smart_speed == e1000_smart_speed_off) {
1453 ret_val = phy->ops.read_reg(hw,
1454 IGP01E1000_PHY_PORT_CONFIG,
1455 &data);
1456 if (ret_val)
1457 goto out;
1458
1459 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1460 ret_val = phy->ops.write_reg(hw,
1461 IGP01E1000_PHY_PORT_CONFIG,
1462 data);
1463 if (ret_val)
1464 goto out;
1465 }
1466 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1467 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1468 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1469 data |= IGP02E1000_PM_D3_LPLU;
1470 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1471 data);
1472 if (ret_val)
1473 goto out;
1474
1475 /* When LPLU is enabled, we should disable SmartSpeed */
1476 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1477 &data);
1478 if (ret_val)
1479 goto out;
1480
1481 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1482 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1483 data);
1484 }
1485
1486out:
1487 return ret_val;
1488}
1489
1490/**
1491 * igb_check_downshift - Checks whether a downshift in speed occurred
1492 * @hw: pointer to the HW structure
1493 *
1494 * Success returns 0, Failure returns 1
1495 *
1496 * A downshift is detected by querying the PHY link health.
1497 **/
1498s32 igb_check_downshift(struct e1000_hw *hw)
1499{
1500 struct e1000_phy_info *phy = &hw->phy;
1501 s32 ret_val;
1502 u16 phy_data, offset, mask;
1503
1504 switch (phy->type) {
1505 case e1000_phy_i210:
1506 case e1000_phy_m88:
1507 case e1000_phy_gg82563:
1508 offset = M88E1000_PHY_SPEC_STATUS;
1509 mask = M88E1000_PSSR_DOWNSHIFT;
1510 break;
1511 case e1000_phy_igp_2:
1512 case e1000_phy_igp:
1513 case e1000_phy_igp_3:
1514 offset = IGP01E1000_PHY_LINK_HEALTH;
1515 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1516 break;
1517 default:
1518 /* speed downshift not supported */
1519 phy->speed_downgraded = false;
1520 ret_val = 0;
1521 goto out;
1522 }
1523
1524 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1525
1526 if (!ret_val)
1527 phy->speed_downgraded = (phy_data & mask) ? true : false;
1528
1529out:
1530 return ret_val;
1531}
1532
1533/**
1534 * igb_check_polarity_m88 - Checks the polarity.
1535 * @hw: pointer to the HW structure
1536 *
1537 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1538 *
1539 * Polarity is determined based on the PHY specific status register.
1540 **/
1541s32 igb_check_polarity_m88(struct e1000_hw *hw)
1542{
1543 struct e1000_phy_info *phy = &hw->phy;
1544 s32 ret_val;
1545 u16 data;
1546
1547 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1548
1549 if (!ret_val)
1550 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1551 ? e1000_rev_polarity_reversed
1552 : e1000_rev_polarity_normal;
1553
1554 return ret_val;
1555}
1556
1557/**
1558 * igb_check_polarity_igp - Checks the polarity.
1559 * @hw: pointer to the HW structure
1560 *
1561 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1562 *
1563 * Polarity is determined based on the PHY port status register, and the
1564 * current speed (since there is no polarity at 100Mbps).
1565 **/
1566static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1567{
1568 struct e1000_phy_info *phy = &hw->phy;
1569 s32 ret_val;
1570 u16 data, offset, mask;
1571
1572 /* Polarity is determined based on the speed of
1573 * our connection.
1574 */
1575 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1576 if (ret_val)
1577 goto out;
1578
1579 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1580 IGP01E1000_PSSR_SPEED_1000MBPS) {
1581 offset = IGP01E1000_PHY_PCS_INIT_REG;
1582 mask = IGP01E1000_PHY_POLARITY_MASK;
1583 } else {
1584 /* This really only applies to 10Mbps since
1585 * there is no polarity for 100Mbps (always 0).
1586 */
1587 offset = IGP01E1000_PHY_PORT_STATUS;
1588 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1589 }
1590
1591 ret_val = phy->ops.read_reg(hw, offset, &data);
1592
1593 if (!ret_val)
1594 phy->cable_polarity = (data & mask)
1595 ? e1000_rev_polarity_reversed
1596 : e1000_rev_polarity_normal;
1597
1598out:
1599 return ret_val;
1600}
1601
1602/**
1603 * igb_wait_autoneg - Wait for auto-neg completion
1604 * @hw: pointer to the HW structure
1605 *
1606 * Waits for auto-negotiation to complete or for the auto-negotiation time
1607 * limit to expire, which ever happens first.
1608 **/
1609static s32 igb_wait_autoneg(struct e1000_hw *hw)
1610{
1611 s32 ret_val = 0;
1612 u16 i, phy_status;
1613
1614 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1615 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1616 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1617 if (ret_val)
1618 break;
1619 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1620 if (ret_val)
1621 break;
1622 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1623 break;
1624 msleep(100);
1625 }
1626
1627 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1628 * has completed.
1629 */
1630 return ret_val;
1631}
1632
1633/**
1634 * igb_phy_has_link - Polls PHY for link
1635 * @hw: pointer to the HW structure
1636 * @iterations: number of times to poll for link
1637 * @usec_interval: delay between polling attempts
1638 * @success: pointer to whether polling was successful or not
1639 *
1640 * Polls the PHY status register for link, 'iterations' number of times.
1641 **/
1642s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1643 u32 usec_interval, bool *success)
1644{
1645 s32 ret_val = 0;
1646 u16 i, phy_status;
1647
1648 for (i = 0; i < iterations; i++) {
1649 /* Some PHYs require the PHY_STATUS register to be read
1650 * twice due to the link bit being sticky. No harm doing
1651 * it across the board.
1652 */
1653 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1654 if (ret_val && usec_interval > 0) {
1655 /* If the first read fails, another entity may have
1656 * ownership of the resources, wait and try again to
1657 * see if they have relinquished the resources yet.
1658 */
1659 if (usec_interval >= 1000)
1660 mdelay(usec_interval/1000);
1661 else
1662 udelay(usec_interval);
1663 }
1664 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1665 if (ret_val)
1666 break;
1667 if (phy_status & MII_SR_LINK_STATUS)
1668 break;
1669 if (usec_interval >= 1000)
1670 mdelay(usec_interval/1000);
1671 else
1672 udelay(usec_interval);
1673 }
1674
1675 *success = (i < iterations) ? true : false;
1676
1677 return ret_val;
1678}
1679
1680/**
1681 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1682 * @hw: pointer to the HW structure
1683 *
1684 * Reads the PHY specific status register to retrieve the cable length
1685 * information. The cable length is determined by averaging the minimum and
1686 * maximum values to get the "average" cable length. The m88 PHY has four
1687 * possible cable length values, which are:
1688 * Register Value Cable Length
1689 * 0 < 50 meters
1690 * 1 50 - 80 meters
1691 * 2 80 - 110 meters
1692 * 3 110 - 140 meters
1693 * 4 > 140 meters
1694 **/
1695s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1696{
1697 struct e1000_phy_info *phy = &hw->phy;
1698 s32 ret_val;
1699 u16 phy_data, index;
1700
1701 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1702 if (ret_val)
1703 goto out;
1704
1705 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1706 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1707 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1708 ret_val = -E1000_ERR_PHY;
1709 goto out;
1710 }
1711
1712 phy->min_cable_length = e1000_m88_cable_length_table[index];
1713 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1714
1715 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1716
1717out:
1718 return ret_val;
1719}
1720
1721s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1722{
1723 struct e1000_phy_info *phy = &hw->phy;
1724 s32 ret_val;
1725 u16 phy_data, phy_data2, index, default_page, is_cm;
1726
1727 switch (hw->phy.id) {
1728 case I210_I_PHY_ID:
1729 /* Get cable length from PHY Cable Diagnostics Control Reg */
1730 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1731 (I347AT4_PCDL + phy->addr),
1732 &phy_data);
1733 if (ret_val)
1734 return ret_val;
1735
1736 /* Check if the unit of cable length is meters or cm */
1737 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1738 I347AT4_PCDC, &phy_data2);
1739 if (ret_val)
1740 return ret_val;
1741
1742 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1743
1744 /* Populate the phy structure with cable length in meters */
1745 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1746 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1747 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1748 break;
1749 case M88E1543_E_PHY_ID:
1750 case I347AT4_E_PHY_ID:
1751 /* Remember the original page select and set it to 7 */
1752 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1753 &default_page);
1754 if (ret_val)
1755 goto out;
1756
1757 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1758 if (ret_val)
1759 goto out;
1760
1761 /* Get cable length from PHY Cable Diagnostics Control Reg */
1762 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1763 &phy_data);
1764 if (ret_val)
1765 goto out;
1766
1767 /* Check if the unit of cable length is meters or cm */
1768 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1769 if (ret_val)
1770 goto out;
1771
1772 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1773
1774 /* Populate the phy structure with cable length in meters */
1775 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1776 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1777 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1778
1779 /* Reset the page selec to its original value */
1780 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1781 default_page);
1782 if (ret_val)
1783 goto out;
1784 break;
1785 case M88E1112_E_PHY_ID:
1786 /* Remember the original page select and set it to 5 */
1787 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1788 &default_page);
1789 if (ret_val)
1790 goto out;
1791
1792 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1793 if (ret_val)
1794 goto out;
1795
1796 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1797 &phy_data);
1798 if (ret_val)
1799 goto out;
1800
1801 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1802 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1803 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1804 ret_val = -E1000_ERR_PHY;
1805 goto out;
1806 }
1807
1808 phy->min_cable_length = e1000_m88_cable_length_table[index];
1809 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1810
1811 phy->cable_length = (phy->min_cable_length +
1812 phy->max_cable_length) / 2;
1813
1814 /* Reset the page select to its original value */
1815 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1816 default_page);
1817 if (ret_val)
1818 goto out;
1819
1820 break;
1821 default:
1822 ret_val = -E1000_ERR_PHY;
1823 goto out;
1824 }
1825
1826out:
1827 return ret_val;
1828}
1829
1830/**
1831 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1832 * @hw: pointer to the HW structure
1833 *
1834 * The automatic gain control (agc) normalizes the amplitude of the
1835 * received signal, adjusting for the attenuation produced by the
1836 * cable. By reading the AGC registers, which represent the
1837 * combination of coarse and fine gain value, the value can be put
1838 * into a lookup table to obtain the approximate cable length
1839 * for each channel.
1840 **/
1841s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1842{
1843 struct e1000_phy_info *phy = &hw->phy;
1844 s32 ret_val = 0;
1845 u16 phy_data, i, agc_value = 0;
1846 u16 cur_agc_index, max_agc_index = 0;
1847 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1848 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1849 IGP02E1000_PHY_AGC_A,
1850 IGP02E1000_PHY_AGC_B,
1851 IGP02E1000_PHY_AGC_C,
1852 IGP02E1000_PHY_AGC_D
1853 };
1854
1855 /* Read the AGC registers for all channels */
1856 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1857 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1858 if (ret_val)
1859 goto out;
1860
1861 /* Getting bits 15:9, which represent the combination of
1862 * coarse and fine gain values. The result is a number
1863 * that can be put into the lookup table to obtain the
1864 * approximate cable length.
1865 */
1866 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1867 IGP02E1000_AGC_LENGTH_MASK;
1868
1869 /* Array index bound check. */
1870 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1871 (cur_agc_index == 0)) {
1872 ret_val = -E1000_ERR_PHY;
1873 goto out;
1874 }
1875
1876 /* Remove min & max AGC values from calculation. */
1877 if (e1000_igp_2_cable_length_table[min_agc_index] >
1878 e1000_igp_2_cable_length_table[cur_agc_index])
1879 min_agc_index = cur_agc_index;
1880 if (e1000_igp_2_cable_length_table[max_agc_index] <
1881 e1000_igp_2_cable_length_table[cur_agc_index])
1882 max_agc_index = cur_agc_index;
1883
1884 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1885 }
1886
1887 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1888 e1000_igp_2_cable_length_table[max_agc_index]);
1889 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1890
1891 /* Calculate cable length with the error range of +/- 10 meters. */
1892 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1893 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1894 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1895
1896 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1897
1898out:
1899 return ret_val;
1900}
1901
1902/**
1903 * igb_get_phy_info_m88 - Retrieve PHY information
1904 * @hw: pointer to the HW structure
1905 *
1906 * Valid for only copper links. Read the PHY status register (sticky read)
1907 * to verify that link is up. Read the PHY special control register to
1908 * determine the polarity and 10base-T extended distance. Read the PHY
1909 * special status register to determine MDI/MDIx and current speed. If
1910 * speed is 1000, then determine cable length, local and remote receiver.
1911 **/
1912s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1913{
1914 struct e1000_phy_info *phy = &hw->phy;
1915 s32 ret_val;
1916 u16 phy_data;
1917 bool link;
1918
1919 if (phy->media_type != e1000_media_type_copper) {
1920 hw_dbg("Phy info is only valid for copper media\n");
1921 ret_val = -E1000_ERR_CONFIG;
1922 goto out;
1923 }
1924
1925 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1926 if (ret_val)
1927 goto out;
1928
1929 if (!link) {
1930 hw_dbg("Phy info is only valid if link is up\n");
1931 ret_val = -E1000_ERR_CONFIG;
1932 goto out;
1933 }
1934
1935 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1936 if (ret_val)
1937 goto out;
1938
1939 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1940 ? true : false;
1941
1942 ret_val = igb_check_polarity_m88(hw);
1943 if (ret_val)
1944 goto out;
1945
1946 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1947 if (ret_val)
1948 goto out;
1949
1950 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1951
1952 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1953 ret_val = phy->ops.get_cable_length(hw);
1954 if (ret_val)
1955 goto out;
1956
1957 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1958 if (ret_val)
1959 goto out;
1960
1961 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1962 ? e1000_1000t_rx_status_ok
1963 : e1000_1000t_rx_status_not_ok;
1964
1965 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1966 ? e1000_1000t_rx_status_ok
1967 : e1000_1000t_rx_status_not_ok;
1968 } else {
1969 /* Set values to "undefined" */
1970 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1971 phy->local_rx = e1000_1000t_rx_status_undefined;
1972 phy->remote_rx = e1000_1000t_rx_status_undefined;
1973 }
1974
1975out:
1976 return ret_val;
1977}
1978
1979/**
1980 * igb_get_phy_info_igp - Retrieve igp PHY information
1981 * @hw: pointer to the HW structure
1982 *
1983 * Read PHY status to determine if link is up. If link is up, then
1984 * set/determine 10base-T extended distance and polarity correction. Read
1985 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1986 * determine on the cable length, local and remote receiver.
1987 **/
1988s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1989{
1990 struct e1000_phy_info *phy = &hw->phy;
1991 s32 ret_val;
1992 u16 data;
1993 bool link;
1994
1995 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1996 if (ret_val)
1997 goto out;
1998
1999 if (!link) {
2000 hw_dbg("Phy info is only valid if link is up\n");
2001 ret_val = -E1000_ERR_CONFIG;
2002 goto out;
2003 }
2004
2005 phy->polarity_correction = true;
2006
2007 ret_val = igb_check_polarity_igp(hw);
2008 if (ret_val)
2009 goto out;
2010
2011 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2012 if (ret_val)
2013 goto out;
2014
2015 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2016
2017 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2018 IGP01E1000_PSSR_SPEED_1000MBPS) {
2019 ret_val = phy->ops.get_cable_length(hw);
2020 if (ret_val)
2021 goto out;
2022
2023 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2024 if (ret_val)
2025 goto out;
2026
2027 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2028 ? e1000_1000t_rx_status_ok
2029 : e1000_1000t_rx_status_not_ok;
2030
2031 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2032 ? e1000_1000t_rx_status_ok
2033 : e1000_1000t_rx_status_not_ok;
2034 } else {
2035 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2036 phy->local_rx = e1000_1000t_rx_status_undefined;
2037 phy->remote_rx = e1000_1000t_rx_status_undefined;
2038 }
2039
2040out:
2041 return ret_val;
2042}
2043
2044/**
2045 * igb_phy_sw_reset - PHY software reset
2046 * @hw: pointer to the HW structure
2047 *
2048 * Does a software reset of the PHY by reading the PHY control register and
2049 * setting/write the control register reset bit to the PHY.
2050 **/
2051s32 igb_phy_sw_reset(struct e1000_hw *hw)
2052{
2053 s32 ret_val = 0;
2054 u16 phy_ctrl;
2055
2056 if (!(hw->phy.ops.read_reg))
2057 goto out;
2058
2059 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2060 if (ret_val)
2061 goto out;
2062
2063 phy_ctrl |= MII_CR_RESET;
2064 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2065 if (ret_val)
2066 goto out;
2067
2068 udelay(1);
2069
2070out:
2071 return ret_val;
2072}
2073
2074/**
2075 * igb_phy_hw_reset - PHY hardware reset
2076 * @hw: pointer to the HW structure
2077 *
2078 * Verify the reset block is not blocking us from resetting. Acquire
2079 * semaphore (if necessary) and read/set/write the device control reset
2080 * bit in the PHY. Wait the appropriate delay time for the device to
2081 * reset and release the semaphore (if necessary).
2082 **/
2083s32 igb_phy_hw_reset(struct e1000_hw *hw)
2084{
2085 struct e1000_phy_info *phy = &hw->phy;
2086 s32 ret_val;
2087 u32 ctrl;
2088
2089 ret_val = igb_check_reset_block(hw);
2090 if (ret_val) {
2091 ret_val = 0;
2092 goto out;
2093 }
2094
2095 ret_val = phy->ops.acquire(hw);
2096 if (ret_val)
2097 goto out;
2098
2099 ctrl = rd32(E1000_CTRL);
2100 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2101 wrfl();
2102
2103 udelay(phy->reset_delay_us);
2104
2105 wr32(E1000_CTRL, ctrl);
2106 wrfl();
2107
2108 udelay(150);
2109
2110 phy->ops.release(hw);
2111
2112 ret_val = phy->ops.get_cfg_done(hw);
2113
2114out:
2115 return ret_val;
2116}
2117
2118/**
2119 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2120 * @hw: pointer to the HW structure
2121 *
2122 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2123 **/
2124s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2125{
2126 hw_dbg("Running IGP 3 PHY init script\n");
2127
2128 /* PHY init IGP 3 */
2129 /* Enable rise/fall, 10-mode work in class-A */
2130 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2131 /* Remove all caps from Replica path filter */
2132 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2133 /* Bias trimming for ADC, AFE and Driver (Default) */
2134 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2135 /* Increase Hybrid poly bias */
2136 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2137 /* Add 4% to TX amplitude in Giga mode */
2138 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2139 /* Disable trimming (TTT) */
2140 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2141 /* Poly DC correction to 94.6% + 2% for all channels */
2142 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2143 /* ABS DC correction to 95.9% */
2144 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2145 /* BG temp curve trim */
2146 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2147 /* Increasing ADC OPAMP stage 1 currents to max */
2148 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2149 /* Force 1000 ( required for enabling PHY regs configuration) */
2150 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2151 /* Set upd_freq to 6 */
2152 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2153 /* Disable NPDFE */
2154 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2155 /* Disable adaptive fixed FFE (Default) */
2156 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2157 /* Enable FFE hysteresis */
2158 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2159 /* Fixed FFE for short cable lengths */
2160 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2161 /* Fixed FFE for medium cable lengths */
2162 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2163 /* Fixed FFE for long cable lengths */
2164 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2165 /* Enable Adaptive Clip Threshold */
2166 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2167 /* AHT reset limit to 1 */
2168 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2169 /* Set AHT master delay to 127 msec */
2170 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2171 /* Set scan bits for AHT */
2172 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2173 /* Set AHT Preset bits */
2174 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2175 /* Change integ_factor of channel A to 3 */
2176 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2177 /* Change prop_factor of channels BCD to 8 */
2178 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2179 /* Change cg_icount + enable integbp for channels BCD */
2180 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2181 /* Change cg_icount + enable integbp + change prop_factor_master
2182 * to 8 for channel A
2183 */
2184 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2185 /* Disable AHT in Slave mode on channel A */
2186 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2187 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2188 * Enable SPD+B2B
2189 */
2190 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2191 /* Enable restart AN on an1000_dis change */
2192 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2193 /* Enable wh_fifo read clock in 10/100 modes */
2194 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2195 /* Restart AN, Speed selection is 1000 */
2196 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2197
2198 return 0;
2199}
2200
2201/**
2202 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2203 * @hw: pointer to the HW structure
2204 *
2205 * In the case of a PHY power down to save power, or to turn off link during a
2206 * driver unload, restore the link to previous settings.
2207 **/
2208void igb_power_up_phy_copper(struct e1000_hw *hw)
2209{
2210 u16 mii_reg = 0;
2211 u16 power_reg = 0;
2212
2213 /* The PHY will retain its settings across a power down/up cycle */
2214 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2215 mii_reg &= ~MII_CR_POWER_DOWN;
2216 if (hw->phy.type == e1000_phy_i210) {
2217 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2218 power_reg &= ~GS40G_CS_POWER_DOWN;
2219 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2220 }
2221 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2222}
2223
2224/**
2225 * igb_power_down_phy_copper - Power down copper PHY
2226 * @hw: pointer to the HW structure
2227 *
2228 * Power down PHY to save power when interface is down and wake on lan
2229 * is not enabled.
2230 **/
2231void igb_power_down_phy_copper(struct e1000_hw *hw)
2232{
2233 u16 mii_reg = 0;
2234 u16 power_reg = 0;
2235
2236 /* The PHY will retain its settings across a power down/up cycle */
2237 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2238 mii_reg |= MII_CR_POWER_DOWN;
2239
2240 /* i210 Phy requires an additional bit for power up/down */
2241 if (hw->phy.type == e1000_phy_i210) {
2242 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2243 power_reg |= GS40G_CS_POWER_DOWN;
2244 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2245 }
2246 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2247 msleep(1);
2248}
2249
2250/**
2251 * igb_check_polarity_82580 - Checks the polarity.
2252 * @hw: pointer to the HW structure
2253 *
2254 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2255 *
2256 * Polarity is determined based on the PHY specific status register.
2257 **/
2258static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2259{
2260 struct e1000_phy_info *phy = &hw->phy;
2261 s32 ret_val;
2262 u16 data;
2263
2264
2265 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2266
2267 if (!ret_val)
2268 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2269 ? e1000_rev_polarity_reversed
2270 : e1000_rev_polarity_normal;
2271
2272 return ret_val;
2273}
2274
2275/**
2276 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2277 * @hw: pointer to the HW structure
2278 *
2279 * Calls the PHY setup function to force speed and duplex. Clears the
2280 * auto-crossover to force MDI manually. Waits for link and returns
2281 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2282 **/
2283s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2284{
2285 struct e1000_phy_info *phy = &hw->phy;
2286 s32 ret_val;
2287 u16 phy_data;
2288 bool link;
2289
2290 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2291 if (ret_val)
2292 goto out;
2293
2294 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2295
2296 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2297 if (ret_val)
2298 goto out;
2299
2300 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2301 * forced whenever speed and duplex are forced.
2302 */
2303 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2304 if (ret_val)
2305 goto out;
2306
2307 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2308
2309 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2310 if (ret_val)
2311 goto out;
2312
2313 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2314
2315 udelay(1);
2316
2317 if (phy->autoneg_wait_to_complete) {
2318 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2319
2320 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2321 if (ret_val)
2322 goto out;
2323
2324 if (!link)
2325 hw_dbg("Link taking longer than expected.\n");
2326
2327 /* Try once more */
2328 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2329 if (ret_val)
2330 goto out;
2331 }
2332
2333out:
2334 return ret_val;
2335}
2336
2337/**
2338 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2339 * @hw: pointer to the HW structure
2340 *
2341 * Read PHY status to determine if link is up. If link is up, then
2342 * set/determine 10base-T extended distance and polarity correction. Read
2343 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2344 * determine on the cable length, local and remote receiver.
2345 **/
2346s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2347{
2348 struct e1000_phy_info *phy = &hw->phy;
2349 s32 ret_val;
2350 u16 data;
2351 bool link;
2352
2353 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2354 if (ret_val)
2355 goto out;
2356
2357 if (!link) {
2358 hw_dbg("Phy info is only valid if link is up\n");
2359 ret_val = -E1000_ERR_CONFIG;
2360 goto out;
2361 }
2362
2363 phy->polarity_correction = true;
2364
2365 ret_val = igb_check_polarity_82580(hw);
2366 if (ret_val)
2367 goto out;
2368
2369 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2370 if (ret_val)
2371 goto out;
2372
2373 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2374
2375 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2376 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2377 ret_val = hw->phy.ops.get_cable_length(hw);
2378 if (ret_val)
2379 goto out;
2380
2381 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2382 if (ret_val)
2383 goto out;
2384
2385 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2386 ? e1000_1000t_rx_status_ok
2387 : e1000_1000t_rx_status_not_ok;
2388
2389 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2390 ? e1000_1000t_rx_status_ok
2391 : e1000_1000t_rx_status_not_ok;
2392 } else {
2393 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2394 phy->local_rx = e1000_1000t_rx_status_undefined;
2395 phy->remote_rx = e1000_1000t_rx_status_undefined;
2396 }
2397
2398out:
2399 return ret_val;
2400}
2401
2402/**
2403 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2404 * @hw: pointer to the HW structure
2405 *
2406 * Reads the diagnostic status register and verifies result is valid before
2407 * placing it in the phy_cable_length field.
2408 **/
2409s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2410{
2411 struct e1000_phy_info *phy = &hw->phy;
2412 s32 ret_val;
2413 u16 phy_data, length;
2414
2415 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2416 if (ret_val)
2417 goto out;
2418
2419 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2420 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2421
2422 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2423 ret_val = -E1000_ERR_PHY;
2424
2425 phy->cable_length = length;
2426
2427out:
2428 return ret_val;
2429}
2430
2431/**
2432 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2433 * @hw: pointer to the HW structure
2434 * @offset: lower half is register offset to write to
2435 * upper half is page to use.
2436 * @data: data to write at register offset
2437 *
2438 * Acquires semaphore, if necessary, then writes the data to PHY register
2439 * at the offset. Release any acquired semaphores before exiting.
2440 **/
2441s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2442{
2443 s32 ret_val;
2444 u16 page = offset >> GS40G_PAGE_SHIFT;
2445
2446 offset = offset & GS40G_OFFSET_MASK;
2447 ret_val = hw->phy.ops.acquire(hw);
2448 if (ret_val)
2449 return ret_val;
2450
2451 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2452 if (ret_val)
2453 goto release;
2454 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2455
2456release:
2457 hw->phy.ops.release(hw);
2458 return ret_val;
2459}
2460
2461/**
2462 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2463 * @hw: pointer to the HW structure
2464 * @offset: lower half is register offset to read to
2465 * upper half is page to use.
2466 * @data: data to read at register offset
2467 *
2468 * Acquires semaphore, if necessary, then reads the data in the PHY register
2469 * at the offset. Release any acquired semaphores before exiting.
2470 **/
2471s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2472{
2473 s32 ret_val;
2474 u16 page = offset >> GS40G_PAGE_SHIFT;
2475
2476 offset = offset & GS40G_OFFSET_MASK;
2477 ret_val = hw->phy.ops.acquire(hw);
2478 if (ret_val)
2479 return ret_val;
2480
2481 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2482 if (ret_val)
2483 goto release;
2484 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2485
2486release:
2487 hw->phy.ops.release(hw);
2488 return ret_val;
2489}
2490
2491/**
2492 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2493 * @hw: pointer to the HW structure
2494 *
2495 * Sets up Master/slave mode
2496 **/
2497static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2498{
2499 s32 ret_val;
2500 u16 phy_data;
2501
2502 /* Resolve Master/Slave mode */
2503 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2504 if (ret_val)
2505 return ret_val;
2506
2507 /* load defaults for future use */
2508 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2509 ((phy_data & CR_1000T_MS_VALUE) ?
2510 e1000_ms_force_master :
2511 e1000_ms_force_slave) : e1000_ms_auto;
2512
2513 switch (hw->phy.ms_type) {
2514 case e1000_ms_force_master:
2515 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2516 break;
2517 case e1000_ms_force_slave:
2518 phy_data |= CR_1000T_MS_ENABLE;
2519 phy_data &= ~(CR_1000T_MS_VALUE);
2520 break;
2521 case e1000_ms_auto:
2522 phy_data &= ~CR_1000T_MS_ENABLE;
2523 /* fall-through */
2524 default:
2525 break;
2526 }
2527
2528 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2529}