1
   2/* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
   3 * Copyright (C) 2004 Advanced Micro Devices
   4 *
   5 *
   6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
   7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
   8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
   9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  10 * Copyright 1993 United States Government as represented by the
  11 *	Director, National Security Agency.[ pcnet32.c ]
  12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
  13 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  14 *
  15 *
  16 * This program is free software; you can redistribute it and/or modify
  17 * it under the terms of the GNU General Public License as published by
  18 * the Free Software Foundation; either version 2 of the License, or
  19 * (at your option) any later version.
  20 *
  21 * This program is distributed in the hope that it will be useful,
  22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24 * GNU General Public License for more details.
  25 *
  26 * You should have received a copy of the GNU General Public License
  27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  28
  29Module Name:
  30
  31	amd8111e.c
  32
  33Abstract:
  34
  35 	 AMD8111 based 10/100 Ethernet Controller Driver.
  36
  37Environment:
  38
  39	Kernel Mode
  40
  41Revision History:
  42 	3.0.0
  43	   Initial Revision.
  44	3.0.1
  45	 1. Dynamic interrupt coalescing.
  46	 2. Removed prev_stats.
  47	 3. MII support.
  48	 4. Dynamic IPG support
  49	3.0.2  05/29/2003
  50	 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
  51	 2. Bug fix: Fixed VLAN support failure.
  52	 3. Bug fix: Fixed receive interrupt coalescing bug.
  53	 4. Dynamic IPG support is disabled by default.
  54	3.0.3 06/05/2003
  55	 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
  56	3.0.4 12/09/2003
  57	 1. Added set_mac_address routine for bonding driver support.
  58	 2. Tested the driver for bonding support
  59	 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
  60	    indicated to the h/w.
  61	 4. Modified amd8111e_rx() routine to receive all the received packets
  62	    in the first interrupt.
  63	 5. Bug fix: Corrected  rx_errors  reported in get_stats() function.
  64	3.0.5 03/22/2004
  65	 1. Added NAPI support
  66
  67*/
  68
  69
  70#include <linux/module.h>
  71#include <linux/kernel.h>
  72#include <linux/types.h>
  73#include <linux/compiler.h>
  74#include <linux/delay.h>
  75#include <linux/interrupt.h>
  76#include <linux/ioport.h>
  77#include <linux/pci.h>
  78#include <linux/netdevice.h>
  79#include <linux/etherdevice.h>
  80#include <linux/skbuff.h>
  81#include <linux/ethtool.h>
  82#include <linux/mii.h>
  83#include <linux/if_vlan.h>
  84#include <linux/ctype.h>
  85#include <linux/crc32.h>
  86#include <linux/dma-mapping.h>
  87
  88#include <asm/io.h>
  89#include <asm/byteorder.h>
  90#include <linux/uaccess.h>
  91
  92#if IS_ENABLED(CONFIG_VLAN_8021Q)
  93#define AMD8111E_VLAN_TAG_USED 1
  94#else
  95#define AMD8111E_VLAN_TAG_USED 0
  96#endif
  97
  98#include "amd8111e.h"
  99#define MODULE_NAME	"amd8111e"
 100#define MODULE_VERS	"3.0.7"
 101MODULE_AUTHOR("Advanced Micro Devices, Inc.");
 102MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
 103MODULE_LICENSE("GPL");
 
 104module_param_array(speed_duplex, int, NULL, 0);
 105MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
 106module_param_array(coalesce, bool, NULL, 0);
 107MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
 108module_param_array(dynamic_ipg, bool, NULL, 0);
 109MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
 110
 111/* This function will read the PHY registers. */
 112static int amd8111e_read_phy(struct amd8111e_priv *lp,
 113			     int phy_id, int reg, u32 *val)
 
 
 
 
 
 
 
 
 114{
 115	void __iomem *mmio = lp->mmio;
 116	unsigned int reg_val;
 117	unsigned int repeat= REPEAT_CNT;
 118
 119	reg_val = readl(mmio + PHY_ACCESS);
 120	while (reg_val & PHY_CMD_ACTIVE)
 121		reg_val = readl( mmio + PHY_ACCESS );
 122
 123	writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
 124			   ((reg & 0x1f) << 16),  mmio +PHY_ACCESS);
 125	do{
 126		reg_val = readl(mmio + PHY_ACCESS);
 127		udelay(30);  /* It takes 30 us to read/write data */
 128	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 129	if(reg_val & PHY_RD_ERR)
 130		goto err_phy_read;
 131
 132	*val = reg_val & 0xffff;
 133	return 0;
 134err_phy_read:
 135	*val = 0;
 136	return -EINVAL;
 137
 138}
 139
 140/* This function will write into PHY registers. */
 141static int amd8111e_write_phy(struct amd8111e_priv *lp,
 142			      int phy_id, int reg, u32 val)
 
 143{
 144	unsigned int repeat = REPEAT_CNT;
 145	void __iomem *mmio = lp->mmio;
 146	unsigned int reg_val;
 147
 148	reg_val = readl(mmio + PHY_ACCESS);
 149	while (reg_val & PHY_CMD_ACTIVE)
 150		reg_val = readl( mmio + PHY_ACCESS );
 151
 152	writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
 153			   ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
 154
 155	do{
 156		reg_val = readl(mmio + PHY_ACCESS);
 157		udelay(30);  /* It takes 30 us to read/write the data */
 158	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 159
 160	if(reg_val & PHY_RD_ERR)
 161		goto err_phy_write;
 162
 163	return 0;
 164
 165err_phy_write:
 166	return -EINVAL;
 167
 168}
 169
 170/* This is the mii register read function provided to the mii interface. */
 171static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num)
 
 172{
 173	struct amd8111e_priv *lp = netdev_priv(dev);
 174	unsigned int reg_val;
 175
 176	amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
 177	return reg_val;
 178
 179}
 180
 181/* This is the mii register write function provided to the mii interface. */
 182static void amd8111e_mdio_write(struct net_device *dev,
 183				int phy_id, int reg_num, int val)
 
 184{
 185	struct amd8111e_priv *lp = netdev_priv(dev);
 186
 187	amd8111e_write_phy(lp, phy_id, reg_num, val);
 188}
 189
 190/* This function will set PHY speed. During initialization sets
 191 * the original speed to 100 full
 192 */
 193static void amd8111e_set_ext_phy(struct net_device *dev)
 194{
 195	struct amd8111e_priv *lp = netdev_priv(dev);
 196	u32 bmcr,advert,tmp;
 197
 198	/* Determine mii register values to set the speed */
 199	advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
 200	tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 201	switch (lp->ext_phy_option){
 202
 203		default:
 204		case SPEED_AUTONEG: /* advertise all values */
 205			tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
 206				ADVERTISE_100HALF|ADVERTISE_100FULL) ;
 207			break;
 208		case SPEED10_HALF:
 209			tmp |= ADVERTISE_10HALF;
 210			break;
 211		case SPEED10_FULL:
 212			tmp |= ADVERTISE_10FULL;
 213			break;
 214		case SPEED100_HALF:
 215			tmp |= ADVERTISE_100HALF;
 216			break;
 217		case SPEED100_FULL:
 218			tmp |= ADVERTISE_100FULL;
 219			break;
 220	}
 221
 222	if(advert != tmp)
 223		amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
 224	/* Restart auto negotiation */
 225	bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
 226	bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
 227	amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
 228
 229}
 230
 231/* This function will unmap skb->data space and will free
 232 * all transmit and receive skbuffs.
 233 */
 
 234static int amd8111e_free_skbs(struct net_device *dev)
 235{
 236	struct amd8111e_priv *lp = netdev_priv(dev);
 237	struct sk_buff *rx_skbuff;
 238	int i;
 239
 240	/* Freeing transmit skbs */
 241	for(i = 0; i < NUM_TX_BUFFERS; i++){
 242		if(lp->tx_skbuff[i]){
 243			pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i],					lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
 244			dev_kfree_skb (lp->tx_skbuff[i]);
 245			lp->tx_skbuff[i] = NULL;
 246			lp->tx_dma_addr[i] = 0;
 247		}
 248	}
 249	/* Freeing previously allocated receive buffers */
 250	for (i = 0; i < NUM_RX_BUFFERS; i++){
 251		rx_skbuff = lp->rx_skbuff[i];
 252		if(rx_skbuff != NULL){
 253			pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
 254				  lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
 255			dev_kfree_skb(lp->rx_skbuff[i]);
 256			lp->rx_skbuff[i] = NULL;
 257			lp->rx_dma_addr[i] = 0;
 258		}
 259	}
 260
 261	return 0;
 262}
 263
 264/* This will set the receive buffer length corresponding
 265 * to the mtu size of networkinterface.
 266 */
 267static inline void amd8111e_set_rx_buff_len(struct net_device *dev)
 268{
 269	struct amd8111e_priv *lp = netdev_priv(dev);
 270	unsigned int mtu = dev->mtu;
 271
 272	if (mtu > ETH_DATA_LEN){
 273		/* MTU + ethernet header + FCS
 274		 * + optional VLAN tag + skb reserve space 2
 275		 */
 276		lp->rx_buff_len = mtu + ETH_HLEN + 10;
 277		lp->options |= OPTION_JUMBO_ENABLE;
 278	} else{
 279		lp->rx_buff_len = PKT_BUFF_SZ;
 280		lp->options &= ~OPTION_JUMBO_ENABLE;
 281	}
 282}
 283
 284/* This function will free all the previously allocated buffers,
 285 * determine new receive buffer length  and will allocate new receive buffers.
 286 * This function also allocates and initializes both the transmitter
 287 * and receive hardware descriptors.
 288 */
 289static int amd8111e_init_ring(struct net_device *dev)
 290{
 291	struct amd8111e_priv *lp = netdev_priv(dev);
 292	int i;
 293
 294	lp->rx_idx = lp->tx_idx = 0;
 295	lp->tx_complete_idx = 0;
 296	lp->tx_ring_idx = 0;
 297
 298
 299	if(lp->opened)
 300		/* Free previously allocated transmit and receive skbs */
 301		amd8111e_free_skbs(dev);
 302
 303	else{
 304		 /* allocate the tx and rx descriptors */
 305	     	if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
 306			sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 307			&lp->tx_ring_dma_addr)) == NULL)
 308
 309			goto err_no_mem;
 310
 311	     	if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
 312			sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 313			&lp->rx_ring_dma_addr)) == NULL)
 314
 315			goto err_free_tx_ring;
 316
 317	}
 318	/* Set new receive buff size */
 319	amd8111e_set_rx_buff_len(dev);
 320
 321	/* Allocating receive  skbs */
 322	for (i = 0; i < NUM_RX_BUFFERS; i++) {
 323
 324		lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len);
 325		if (!lp->rx_skbuff[i]) {
 326				/* Release previos allocated skbs */
 327				for(--i; i >= 0 ;i--)
 328					dev_kfree_skb(lp->rx_skbuff[i]);
 329				goto err_free_rx_ring;
 330		}
 331		skb_reserve(lp->rx_skbuff[i],2);
 332	}
 333        /* Initilaizing receive descriptors */
 334	for (i = 0; i < NUM_RX_BUFFERS; i++) {
 335		lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
 336			lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 337
 338		lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
 339		lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
 340		wmb();
 341		lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
 342	}
 343
 344	/* Initializing transmit descriptors */
 345	for (i = 0; i < NUM_TX_RING_DR; i++) {
 346		lp->tx_ring[i].buff_phy_addr = 0;
 347		lp->tx_ring[i].tx_flags = 0;
 348		lp->tx_ring[i].buff_count = 0;
 349	}
 350
 351	return 0;
 352
 353err_free_rx_ring:
 354
 355	pci_free_consistent(lp->pci_dev,
 356		sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
 357		lp->rx_ring_dma_addr);
 358
 359err_free_tx_ring:
 360
 361	pci_free_consistent(lp->pci_dev,
 362		 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
 363		 lp->tx_ring_dma_addr);
 364
 365err_no_mem:
 366	return -ENOMEM;
 367}
 368
 369/* This function will set the interrupt coalescing according
 370 * to the input arguments
 371 */
 372static int amd8111e_set_coalesce(struct net_device *dev, enum coal_mode cmod)
 373{
 374	unsigned int timeout;
 375	unsigned int event_count;
 376
 377	struct amd8111e_priv *lp = netdev_priv(dev);
 378	void __iomem *mmio = lp->mmio;
 379	struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
 380
 381
 382	switch(cmod)
 383	{
 384		case RX_INTR_COAL :
 385			timeout = coal_conf->rx_timeout;
 386			event_count = coal_conf->rx_event_count;
 387			if( timeout > MAX_TIMEOUT ||
 388					event_count > MAX_EVENT_COUNT )
 389				return -EINVAL;
 390
 391			timeout = timeout * DELAY_TIMER_CONV;
 392			writel(VAL0|STINTEN, mmio+INTEN0);
 393			writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
 394							mmio+DLY_INT_A);
 395			break;
 396
 397		case TX_INTR_COAL :
 398			timeout = coal_conf->tx_timeout;
 399			event_count = coal_conf->tx_event_count;
 400			if( timeout > MAX_TIMEOUT ||
 401					event_count > MAX_EVENT_COUNT )
 402				return -EINVAL;
 403
 404
 405			timeout = timeout * DELAY_TIMER_CONV;
 406			writel(VAL0|STINTEN,mmio+INTEN0);
 407			writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
 408							 mmio+DLY_INT_B);
 409			break;
 410
 411		case DISABLE_COAL:
 412			writel(0,mmio+STVAL);
 413			writel(STINTEN, mmio+INTEN0);
 414			writel(0, mmio +DLY_INT_B);
 415			writel(0, mmio+DLY_INT_A);
 416			break;
 417		 case ENABLE_COAL:
 418		       /* Start the timer */
 419			writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /*  0.5 sec */
 420			writel(VAL0|STINTEN, mmio+INTEN0);
 421			break;
 422		default:
 423			break;
 424
 425   }
 426	return 0;
 427
 428}
 429
 430/* This function initializes the device registers  and starts the device. */
 
 
 431static int amd8111e_restart(struct net_device *dev)
 432{
 433	struct amd8111e_priv *lp = netdev_priv(dev);
 434	void __iomem *mmio = lp->mmio;
 435	int i,reg_val;
 436
 437	/* stop the chip */
 438	 writel(RUN, mmio + CMD0);
 439
 440	if(amd8111e_init_ring(dev))
 441		return -ENOMEM;
 442
 443	/* enable the port manager and set auto negotiation always */
 444	writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
 445	writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
 446
 447	amd8111e_set_ext_phy(dev);
 448
 449	/* set control registers */
 450	reg_val = readl(mmio + CTRL1);
 451	reg_val &= ~XMTSP_MASK;
 452	writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
 453
 454	/* enable interrupt */
 455	writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
 456		APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
 457		SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
 458
 459	writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
 460
 461	/* initialize tx and rx ring base addresses */
 462	writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
 463	writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
 464
 465	writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
 466	writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
 467
 468	/* set default IPG to 96 */
 469	writew((u32)DEFAULT_IPG,mmio+IPG);
 470	writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
 471
 472	if(lp->options & OPTION_JUMBO_ENABLE){
 473		writel((u32)VAL2|JUMBO, mmio + CMD3);
 474		/* Reset REX_UFLO */
 475		writel( REX_UFLO, mmio + CMD2);
 476		/* Should not set REX_UFLO for jumbo frames */
 477		writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
 478	}else{
 479		writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
 480		writel((u32)JUMBO, mmio + CMD3);
 481	}
 482
 483#if AMD8111E_VLAN_TAG_USED
 484	writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
 485#endif
 486	writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
 487
 488	/* Setting the MAC address to the device */
 489	for (i = 0; i < ETH_ALEN; i++)
 490		writeb( dev->dev_addr[i], mmio + PADR + i );
 491
 492	/* Enable interrupt coalesce */
 493	if(lp->options & OPTION_INTR_COAL_ENABLE){
 494		netdev_info(dev, "Interrupt Coalescing Enabled.\n");
 
 495		amd8111e_set_coalesce(dev,ENABLE_COAL);
 496	}
 497
 498	/* set RUN bit to start the chip */
 499	writel(VAL2 | RDMD0, mmio + CMD0);
 500	writel(VAL0 | INTREN | RUN, mmio + CMD0);
 501
 502	/* To avoid PCI posting bug */
 503	readl(mmio+CMD0);
 504	return 0;
 505}
 506
 507/* This function clears necessary the device registers. */
 508static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
 
 509{
 510	unsigned int reg_val;
 511	unsigned int logic_filter[2] ={0,};
 512	void __iomem *mmio = lp->mmio;
 513
 514
 515        /* stop the chip */
 516	writel(RUN, mmio + CMD0);
 517
 518	/* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
 519	writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
 520
 521	/* Clear RCV_RING_BASE_ADDR */
 522	writel(0, mmio + RCV_RING_BASE_ADDR0);
 523
 524	/* Clear XMT_RING_BASE_ADDR */
 525	writel(0, mmio + XMT_RING_BASE_ADDR0);
 526	writel(0, mmio + XMT_RING_BASE_ADDR1);
 527	writel(0, mmio + XMT_RING_BASE_ADDR2);
 528	writel(0, mmio + XMT_RING_BASE_ADDR3);
 529
 530	/* Clear CMD0  */
 531	writel(CMD0_CLEAR,mmio + CMD0);
 532
 533	/* Clear CMD2 */
 534	writel(CMD2_CLEAR, mmio +CMD2);
 535
 536	/* Clear CMD7 */
 537	writel(CMD7_CLEAR , mmio + CMD7);
 538
 539	/* Clear DLY_INT_A and DLY_INT_B */
 540	writel(0x0, mmio + DLY_INT_A);
 541	writel(0x0, mmio + DLY_INT_B);
 542
 543	/* Clear FLOW_CONTROL */
 544	writel(0x0, mmio + FLOW_CONTROL);
 545
 546	/* Clear INT0  write 1 to clear register */
 547	reg_val = readl(mmio + INT0);
 548	writel(reg_val, mmio + INT0);
 549
 550	/* Clear STVAL */
 551	writel(0x0, mmio + STVAL);
 552
 553	/* Clear INTEN0 */
 554	writel( INTEN0_CLEAR, mmio + INTEN0);
 555
 556	/* Clear LADRF */
 557	writel(0x0 , mmio + LADRF);
 558
 559	/* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
 560	writel( 0x80010,mmio + SRAM_SIZE);
 561
 562	/* Clear RCV_RING0_LEN */
 563	writel(0x0, mmio +  RCV_RING_LEN0);
 564
 565	/* Clear XMT_RING0/1/2/3_LEN */
 566	writel(0x0, mmio +  XMT_RING_LEN0);
 567	writel(0x0, mmio +  XMT_RING_LEN1);
 568	writel(0x0, mmio +  XMT_RING_LEN2);
 569	writel(0x0, mmio +  XMT_RING_LEN3);
 570
 571	/* Clear XMT_RING_LIMIT */
 572	writel(0x0, mmio + XMT_RING_LIMIT);
 573
 574	/* Clear MIB */
 575	writew(MIB_CLEAR, mmio + MIB_ADDR);
 576
 577	/* Clear LARF */
 578	amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF);
 579
 580	/* SRAM_SIZE register */
 581	reg_val = readl(mmio + SRAM_SIZE);
 582
 583	if(lp->options & OPTION_JUMBO_ENABLE)
 584		writel( VAL2|JUMBO, mmio + CMD3);
 585#if AMD8111E_VLAN_TAG_USED
 586	writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
 587#endif
 588	/* Set default value to CTRL1 Register */
 589	writel(CTRL1_DEFAULT, mmio + CTRL1);
 590
 591	/* To avoid PCI posting bug */
 592	readl(mmio + CMD2);
 593
 594}
 595
 596/* This function disables the interrupt and clears all the pending
 597 * interrupts in INT0
 
 598 */
 599static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
 600{
 601	u32 intr0;
 602
 603	/* Disable interrupt */
 604	writel(INTREN, lp->mmio + CMD0);
 605
 606	/* Clear INT0 */
 607	intr0 = readl(lp->mmio + INT0);
 608	writel(intr0, lp->mmio + INT0);
 609
 610	/* To avoid PCI posting bug */
 611	readl(lp->mmio + INT0);
 612
 613}
 614
 615/* This function stops the chip. */
 616static void amd8111e_stop_chip(struct amd8111e_priv *lp)
 
 
 617{
 618	writel(RUN, lp->mmio + CMD0);
 619
 620	/* To avoid PCI posting bug */
 621	readl(lp->mmio + CMD0);
 622}
 623
 624/* This function frees the  transmiter and receiver descriptor rings. */
 625static void amd8111e_free_ring(struct amd8111e_priv *lp)
 
 
 626{
 627	/* Free transmit and receive descriptor rings */
 628	if(lp->rx_ring){
 629		pci_free_consistent(lp->pci_dev,
 630			sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 631			lp->rx_ring, lp->rx_ring_dma_addr);
 632		lp->rx_ring = NULL;
 633	}
 634
 635	if(lp->tx_ring){
 636		pci_free_consistent(lp->pci_dev,
 637			sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 638			lp->tx_ring, lp->tx_ring_dma_addr);
 639
 640		lp->tx_ring = NULL;
 641	}
 642
 643}
 644
 645/* This function will free all the transmit skbs that are actually
 646 * transmitted by the device. It will check the ownership of the
 647 * skb before freeing the skb.
 648 */
 649static int amd8111e_tx(struct net_device *dev)
 650{
 651	struct amd8111e_priv *lp = netdev_priv(dev);
 652	int tx_index;
 653	int status;
 654	/* Complete all the transmit packet */
 655	while (lp->tx_complete_idx != lp->tx_idx){
 656		tx_index =  lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
 657		status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
 658
 659		if(status & OWN_BIT)
 660			break;	/* It still hasn't been Txed */
 661
 662		lp->tx_ring[tx_index].buff_phy_addr = 0;
 663
 664		/* We must free the original skb */
 665		if (lp->tx_skbuff[tx_index]) {
 666			pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
 667				  	lp->tx_skbuff[tx_index]->len,
 668					PCI_DMA_TODEVICE);
 669			dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
 670			lp->tx_skbuff[tx_index] = NULL;
 671			lp->tx_dma_addr[tx_index] = 0;
 672		}
 673		lp->tx_complete_idx++;
 674		/*COAL update tx coalescing parameters */
 675		lp->coal_conf.tx_packets++;
 676		lp->coal_conf.tx_bytes +=
 677			le16_to_cpu(lp->tx_ring[tx_index].buff_count);
 678
 679		if (netif_queue_stopped(dev) &&
 680			lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
 681			/* The ring is no longer full, clear tbusy. */
 682			/* lp->tx_full = 0; */
 683			netif_wake_queue (dev);
 684		}
 685	}
 686	return 0;
 687}
 688
 689/* This function handles the driver receive operation in polling mode */
 690static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
 691{
 692	struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
 693	struct net_device *dev = lp->amd8111e_net_dev;
 694	int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
 695	void __iomem *mmio = lp->mmio;
 696	struct sk_buff *skb,*new_skb;
 697	int min_pkt_len, status;
 
 698	int num_rx_pkt = 0;
 699	short pkt_len;
 700#if AMD8111E_VLAN_TAG_USED
 701	short vtag;
 702#endif
 
 
 703
 704	while (num_rx_pkt < budget) {
 705		status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
 706		if (status & OWN_BIT)
 707			break;
 708
 709		/* There is a tricky error noted by John Murphy,
 710		 * <murf@perftech.com> to Russ Nelson: Even with
 711		 * full-sized * buffers it's possible for a
 712		 * jabber packet to use two buffers, with only
 713		 * the last correctly noting the error.
 714		 */
 715		if (status & ERR_BIT) {
 716			/* resetting flags */
 717			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 718			goto err_next_pkt;
 719		}
 720		/* check for STP and ENP */
 721		if (!((status & STP_BIT) && (status & ENP_BIT))){
 722			/* resetting flags */
 723			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 724			goto err_next_pkt;
 725		}
 726		pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
 
 
 
 
 
 
 
 
 
 
 727
 728#if AMD8111E_VLAN_TAG_USED
 729		vtag = status & TT_MASK;
 730		/* MAC will strip vlan tag */
 731		if (vtag != 0)
 732			min_pkt_len = MIN_PKT_LEN - 4;
 733			else
 734#endif
 735			min_pkt_len = MIN_PKT_LEN;
 736
 737		if (pkt_len < min_pkt_len) {
 738			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 739			lp->drv_rx_errors++;
 740			goto err_next_pkt;
 741		}
 742		new_skb = netdev_alloc_skb(dev, lp->rx_buff_len);
 743		if (!new_skb) {
 744			/* if allocation fail,
 745			 * ignore that pkt and go to next one
 746			 */
 747			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 748			lp->drv_rx_errors++;
 749			goto err_next_pkt;
 750		}
 
 751
 752		skb_reserve(new_skb, 2);
 753		skb = lp->rx_skbuff[rx_index];
 754		pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
 755				 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 756		skb_put(skb, pkt_len);
 757		lp->rx_skbuff[rx_index] = new_skb;
 758		lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
 759							   new_skb->data,
 760							   lp->rx_buff_len-2,
 761							   PCI_DMA_FROMDEVICE);
 762
 763		skb->protocol = eth_type_trans(skb, dev);
 764
 765#if AMD8111E_VLAN_TAG_USED
 766		if (vtag == TT_VLAN_TAGGED){
 767			u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info);
 768			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 769		}
 770#endif
 771		napi_gro_receive(napi, skb);
 772		/* COAL update rx coalescing parameters */
 773		lp->coal_conf.rx_packets++;
 774		lp->coal_conf.rx_bytes += pkt_len;
 775		num_rx_pkt++;
 776
 777err_next_pkt:
 778		lp->rx_ring[rx_index].buff_phy_addr
 779			= cpu_to_le32(lp->rx_dma_addr[rx_index]);
 780		lp->rx_ring[rx_index].buff_count =
 781			cpu_to_le16(lp->rx_buff_len-2);
 782		wmb();
 783		lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
 784		rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
 785	}
 
 
 
 
 
 
 786
 787	if (num_rx_pkt < budget && napi_complete_done(napi, num_rx_pkt)) {
 788		unsigned long flags;
 789
 
 790		/* Receive descriptor is empty now */
 791		spin_lock_irqsave(&lp->lock, flags);
 
 792		writel(VAL0|RINTEN0, mmio + INTEN0);
 793		writel(VAL2 | RDMD0, mmio + CMD0);
 794		spin_unlock_irqrestore(&lp->lock, flags);
 795	}
 796
 
 797	return num_rx_pkt;
 798}
 799
 800/* This function will indicate the link status to the kernel. */
 801static int amd8111e_link_change(struct net_device *dev)
 
 
 802{
 803	struct amd8111e_priv *lp = netdev_priv(dev);
 804	int status0,speed;
 805
 806	/* read the link change */
 807     	status0 = readl(lp->mmio + STAT0);
 808
 809	if(status0 & LINK_STATS){
 810		if(status0 & AUTONEG_COMPLETE)
 811			lp->link_config.autoneg = AUTONEG_ENABLE;
 812		else
 813			lp->link_config.autoneg = AUTONEG_DISABLE;
 814
 815		if(status0 & FULL_DPLX)
 816			lp->link_config.duplex = DUPLEX_FULL;
 817		else
 818			lp->link_config.duplex = DUPLEX_HALF;
 819		speed = (status0 & SPEED_MASK) >> 7;
 820		if(speed == PHY_SPEED_10)
 821			lp->link_config.speed = SPEED_10;
 822		else if(speed == PHY_SPEED_100)
 823			lp->link_config.speed = SPEED_100;
 824
 825		netdev_info(dev, "Link is Up. Speed is %s Mbps %s Duplex\n",
 826			    (lp->link_config.speed == SPEED_100) ?
 827							"100" : "10",
 828			    (lp->link_config.duplex == DUPLEX_FULL) ?
 829							"Full" : "Half");
 830
 831		netif_carrier_on(dev);
 832	}
 833	else{
 834		lp->link_config.speed = SPEED_INVALID;
 835		lp->link_config.duplex = DUPLEX_INVALID;
 836		lp->link_config.autoneg = AUTONEG_INVALID;
 837		netdev_info(dev, "Link is Down.\n");
 838		netif_carrier_off(dev);
 839	}
 840
 841	return 0;
 842}
 843
 844/* This function reads the mib counters. */
 
 845static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
 846{
 847	unsigned int  status;
 848	unsigned  int data;
 849	unsigned int repeat = REPEAT_CNT;
 850
 851	writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
 852	do {
 853		status = readw(mmio + MIB_ADDR);
 854		udelay(2);	/* controller takes MAX 2 us to get mib data */
 855	}
 856	while (--repeat && (status & MIB_CMD_ACTIVE));
 857
 858	data = readl(mmio + MIB_DATA);
 859	return data;
 860}
 861
 862/* This function reads the mib registers and returns the hardware statistics.
 
 863 * It updates previous internal driver statistics with new values.
 864 */
 865static struct net_device_stats *amd8111e_get_stats(struct net_device *dev)
 866{
 867	struct amd8111e_priv *lp = netdev_priv(dev);
 868	void __iomem *mmio = lp->mmio;
 869	unsigned long flags;
 870	struct net_device_stats *new_stats = &dev->stats;
 871
 872	if (!lp->opened)
 873		return new_stats;
 874	spin_lock_irqsave (&lp->lock, flags);
 875
 876	/* stats.rx_packets */
 877	new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
 878				amd8111e_read_mib(mmio, rcv_multicast_pkts)+
 879				amd8111e_read_mib(mmio, rcv_unicast_pkts);
 880
 881	/* stats.tx_packets */
 882	new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
 883
 884	/*stats.rx_bytes */
 885	new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
 886
 887	/* stats.tx_bytes */
 888	new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
 889
 890	/* stats.rx_errors */
 891	/* hw errors + errors driver reported */
 892	new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
 893				amd8111e_read_mib(mmio, rcv_fragments)+
 894				amd8111e_read_mib(mmio, rcv_jabbers)+
 895				amd8111e_read_mib(mmio, rcv_alignment_errors)+
 896				amd8111e_read_mib(mmio, rcv_fcs_errors)+
 897				amd8111e_read_mib(mmio, rcv_miss_pkts)+
 898				lp->drv_rx_errors;
 899
 900	/* stats.tx_errors */
 901	new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
 902
 903	/* stats.rx_dropped*/
 904	new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
 905
 906	/* stats.tx_dropped*/
 907	new_stats->tx_dropped = amd8111e_read_mib(mmio,  xmt_underrun_pkts);
 908
 909	/* stats.multicast*/
 910	new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
 911
 912	/* stats.collisions*/
 913	new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
 914
 915	/* stats.rx_length_errors*/
 916	new_stats->rx_length_errors =
 917		amd8111e_read_mib(mmio, rcv_undersize_pkts)+
 918		amd8111e_read_mib(mmio, rcv_oversize_pkts);
 919
 920	/* stats.rx_over_errors*/
 921	new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 922
 923	/* stats.rx_crc_errors*/
 924	new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
 925
 926	/* stats.rx_frame_errors*/
 927	new_stats->rx_frame_errors =
 928		amd8111e_read_mib(mmio, rcv_alignment_errors);
 929
 930	/* stats.rx_fifo_errors */
 931	new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 932
 933	/* stats.rx_missed_errors */
 934	new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
 935
 936	/* stats.tx_aborted_errors*/
 937	new_stats->tx_aborted_errors =
 938		amd8111e_read_mib(mmio, xmt_excessive_collision);
 939
 940	/* stats.tx_carrier_errors*/
 941	new_stats->tx_carrier_errors =
 942		amd8111e_read_mib(mmio, xmt_loss_carrier);
 943
 944	/* stats.tx_fifo_errors*/
 945	new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
 946
 947	/* stats.tx_window_errors*/
 948	new_stats->tx_window_errors =
 949		amd8111e_read_mib(mmio, xmt_late_collision);
 950
 951	/* Reset the mibs for collecting new statistics */
 952	/* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
 953
 954	spin_unlock_irqrestore (&lp->lock, flags);
 955
 956	return new_stats;
 957}
 958
 959/* This function recalculate the interrupt coalescing  mode on every interrupt
 960 * according to the datarate and the packet rate.
 961 */
 962static int amd8111e_calc_coalesce(struct net_device *dev)
 963{
 964	struct amd8111e_priv *lp = netdev_priv(dev);
 965	struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
 966	int tx_pkt_rate;
 967	int rx_pkt_rate;
 968	int tx_data_rate;
 969	int rx_data_rate;
 970	int rx_pkt_size;
 971	int tx_pkt_size;
 972
 973	tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
 974	coal_conf->tx_prev_packets =  coal_conf->tx_packets;
 975
 976	tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
 977	coal_conf->tx_prev_bytes =  coal_conf->tx_bytes;
 978
 979	rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
 980	coal_conf->rx_prev_packets =  coal_conf->rx_packets;
 981
 982	rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
 983	coal_conf->rx_prev_bytes =  coal_conf->rx_bytes;
 984
 985	if(rx_pkt_rate < 800){
 986		if(coal_conf->rx_coal_type != NO_COALESCE){
 987
 988			coal_conf->rx_timeout = 0x0;
 989			coal_conf->rx_event_count = 0;
 990			amd8111e_set_coalesce(dev,RX_INTR_COAL);
 991			coal_conf->rx_coal_type = NO_COALESCE;
 992		}
 993	}
 994	else{
 995
 996		rx_pkt_size = rx_data_rate/rx_pkt_rate;
 997		if (rx_pkt_size < 128){
 998			if(coal_conf->rx_coal_type != NO_COALESCE){
 999
1000				coal_conf->rx_timeout = 0;
1001				coal_conf->rx_event_count = 0;
1002				amd8111e_set_coalesce(dev,RX_INTR_COAL);
1003				coal_conf->rx_coal_type = NO_COALESCE;
1004			}
1005
1006		}
1007		else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1008
1009			if(coal_conf->rx_coal_type !=  LOW_COALESCE){
1010				coal_conf->rx_timeout = 1;
1011				coal_conf->rx_event_count = 4;
1012				amd8111e_set_coalesce(dev,RX_INTR_COAL);
1013				coal_conf->rx_coal_type = LOW_COALESCE;
1014			}
1015		}
1016		else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1017
1018			if(coal_conf->rx_coal_type !=  MEDIUM_COALESCE){
1019				coal_conf->rx_timeout = 1;
1020				coal_conf->rx_event_count = 4;
1021				amd8111e_set_coalesce(dev,RX_INTR_COAL);
1022				coal_conf->rx_coal_type = MEDIUM_COALESCE;
1023			}
1024
1025		}
1026		else if(rx_pkt_size >= 1024){
1027			if(coal_conf->rx_coal_type !=  HIGH_COALESCE){
1028				coal_conf->rx_timeout = 2;
1029				coal_conf->rx_event_count = 3;
1030				amd8111e_set_coalesce(dev,RX_INTR_COAL);
1031				coal_conf->rx_coal_type = HIGH_COALESCE;
1032			}
1033		}
1034	}
1035    	/* NOW FOR TX INTR COALESC */
1036	if(tx_pkt_rate < 800){
1037		if(coal_conf->tx_coal_type != NO_COALESCE){
1038
1039			coal_conf->tx_timeout = 0x0;
1040			coal_conf->tx_event_count = 0;
1041			amd8111e_set_coalesce(dev,TX_INTR_COAL);
1042			coal_conf->tx_coal_type = NO_COALESCE;
1043		}
1044	}
1045	else{
1046
1047		tx_pkt_size = tx_data_rate/tx_pkt_rate;
1048		if (tx_pkt_size < 128){
1049
1050			if(coal_conf->tx_coal_type != NO_COALESCE){
1051
1052				coal_conf->tx_timeout = 0;
1053				coal_conf->tx_event_count = 0;
1054				amd8111e_set_coalesce(dev,TX_INTR_COAL);
1055				coal_conf->tx_coal_type = NO_COALESCE;
1056			}
1057
1058		}
1059		else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1060
1061			if(coal_conf->tx_coal_type !=  LOW_COALESCE){
1062				coal_conf->tx_timeout = 1;
1063				coal_conf->tx_event_count = 2;
1064				amd8111e_set_coalesce(dev,TX_INTR_COAL);
1065				coal_conf->tx_coal_type = LOW_COALESCE;
1066
1067			}
1068		}
1069		else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1070
1071			if(coal_conf->tx_coal_type !=  MEDIUM_COALESCE){
1072				coal_conf->tx_timeout = 2;
1073				coal_conf->tx_event_count = 5;
1074				amd8111e_set_coalesce(dev,TX_INTR_COAL);
1075				coal_conf->tx_coal_type = MEDIUM_COALESCE;
1076			}
1077
1078		}
1079		else if(tx_pkt_size >= 1024){
1080			if (tx_pkt_size >= 1024){
1081				if(coal_conf->tx_coal_type !=  HIGH_COALESCE){
1082					coal_conf->tx_timeout = 4;
1083					coal_conf->tx_event_count = 8;
1084					amd8111e_set_coalesce(dev,TX_INTR_COAL);
1085					coal_conf->tx_coal_type = HIGH_COALESCE;
1086				}
1087			}
1088		}
1089	}
1090	return 0;
1091
1092}
1093
1094/* This is device interrupt function. It handles transmit,
1095 * receive,link change and hardware timer interrupts.
1096 */
1097static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1098{
1099
1100	struct net_device *dev = (struct net_device *)dev_id;
1101	struct amd8111e_priv *lp = netdev_priv(dev);
1102	void __iomem *mmio = lp->mmio;
1103	unsigned int intr0, intren0;
1104	unsigned int handled = 1;
1105
1106	if(unlikely(dev == NULL))
1107		return IRQ_NONE;
1108
1109	spin_lock(&lp->lock);
1110
1111	/* disabling interrupt */
1112	writel(INTREN, mmio + CMD0);
1113
1114	/* Read interrupt status */
1115	intr0 = readl(mmio + INT0);
1116	intren0 = readl(mmio + INTEN0);
1117
1118	/* Process all the INT event until INTR bit is clear. */
1119
1120	if (!(intr0 & INTR)){
1121		handled = 0;
1122		goto err_no_interrupt;
1123	}
1124
1125	/* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1126	writel(intr0, mmio + INT0);
1127
1128	/* Check if Receive Interrupt has occurred. */
1129	if (intr0 & RINT0) {
1130		if (napi_schedule_prep(&lp->napi)) {
1131			/* Disable receive interupts */
1132			writel(RINTEN0, mmio + INTEN0);
1133			/* Schedule a polling routine */
1134			__napi_schedule(&lp->napi);
1135		} else if (intren0 & RINTEN0) {
1136			netdev_dbg(dev, "************Driver bug! interrupt while in poll\n");
1137			/* Fix by disable receive interrupts */
1138			writel(RINTEN0, mmio + INTEN0);
1139		}
1140	}
1141
1142	/* Check if  Transmit Interrupt has occurred. */
1143	if (intr0 & TINT0)
1144		amd8111e_tx(dev);
1145
1146	/* Check if  Link Change Interrupt has occurred. */
1147	if (intr0 & LCINT)
1148		amd8111e_link_change(dev);
1149
1150	/* Check if Hardware Timer Interrupt has occurred. */
1151	if (intr0 & STINT)
1152		amd8111e_calc_coalesce(dev);
1153
1154err_no_interrupt:
1155	writel( VAL0 | INTREN,mmio + CMD0);
1156
1157	spin_unlock(&lp->lock);
1158
1159	return IRQ_RETVAL(handled);
1160}
1161
1162#ifdef CONFIG_NET_POLL_CONTROLLER
1163static void amd8111e_poll(struct net_device *dev)
1164{
1165	unsigned long flags;
1166	local_irq_save(flags);
1167	amd8111e_interrupt(0, dev);
1168	local_irq_restore(flags);
1169}
1170#endif
1171
1172
1173/* This function closes the network interface and updates
1174 * the statistics so that most recent statistics will be
1175 * available after the interface is down.
1176 */
1177static int amd8111e_close(struct net_device *dev)
1178{
1179	struct amd8111e_priv *lp = netdev_priv(dev);
1180	netif_stop_queue(dev);
1181
1182	napi_disable(&lp->napi);
1183
1184	spin_lock_irq(&lp->lock);
1185
1186	amd8111e_disable_interrupt(lp);
1187	amd8111e_stop_chip(lp);
1188
1189	/* Free transmit and receive skbs */
1190	amd8111e_free_skbs(lp->amd8111e_net_dev);
1191
1192	netif_carrier_off(lp->amd8111e_net_dev);
1193
1194	/* Delete ipg timer */
1195	if(lp->options & OPTION_DYN_IPG_ENABLE)
1196		del_timer_sync(&lp->ipg_data.ipg_timer);
1197
1198	spin_unlock_irq(&lp->lock);
1199	free_irq(dev->irq, dev);
1200	amd8111e_free_ring(lp);
1201
1202	/* Update the statistics before closing */
1203	amd8111e_get_stats(dev);
1204	lp->opened = 0;
1205	return 0;
1206}
1207
1208/* This function opens new interface.It requests irq for the device,
1209 * initializes the device,buffers and descriptors, and starts the device.
1210 */
1211static int amd8111e_open(struct net_device *dev)
1212{
1213	struct amd8111e_priv *lp = netdev_priv(dev);
1214
1215	if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1216					 dev->name, dev))
1217		return -EAGAIN;
1218
1219	napi_enable(&lp->napi);
1220
1221	spin_lock_irq(&lp->lock);
1222
1223	amd8111e_init_hw_default(lp);
1224
1225	if(amd8111e_restart(dev)){
1226		spin_unlock_irq(&lp->lock);
1227		napi_disable(&lp->napi);
1228		if (dev->irq)
1229			free_irq(dev->irq, dev);
1230		return -ENOMEM;
1231	}
1232	/* Start ipg timer */
1233	if(lp->options & OPTION_DYN_IPG_ENABLE){
1234		add_timer(&lp->ipg_data.ipg_timer);
1235		netdev_info(dev, "Dynamic IPG Enabled\n");
1236	}
1237
1238	lp->opened = 1;
1239
1240	spin_unlock_irq(&lp->lock);
1241
1242	netif_start_queue(dev);
1243
1244	return 0;
1245}
1246
1247/* This function checks if there is any transmit  descriptors
1248 * available to queue more packet.
1249 */
1250static int amd8111e_tx_queue_avail(struct amd8111e_priv *lp)
1251{
1252	int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1253	if (lp->tx_skbuff[tx_index])
1254		return -1;
1255	else
1256		return 0;
1257
1258}
 
 
 
1259
1260/* This function will queue the transmit packets to the
1261 * descriptors and will trigger the send operation. It also
1262 * initializes the transmit descriptors with buffer physical address,
1263 * byte count, ownership to hardware etc.
1264 */
1265static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1266				       struct net_device *dev)
1267{
1268	struct amd8111e_priv *lp = netdev_priv(dev);
1269	int tx_index;
1270	unsigned long flags;
1271
1272	spin_lock_irqsave(&lp->lock, flags);
1273
1274	tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1275
1276	lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1277
1278	lp->tx_skbuff[tx_index] = skb;
1279	lp->tx_ring[tx_index].tx_flags = 0;
1280
1281#if AMD8111E_VLAN_TAG_USED
1282	if (skb_vlan_tag_present(skb)) {
1283		lp->tx_ring[tx_index].tag_ctrl_cmd |=
1284				cpu_to_le16(TCC_VLAN_INSERT);
1285		lp->tx_ring[tx_index].tag_ctrl_info =
1286				cpu_to_le16(skb_vlan_tag_get(skb));
1287
1288	}
1289#endif
1290	lp->tx_dma_addr[tx_index] =
1291	    pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1292	lp->tx_ring[tx_index].buff_phy_addr =
1293	    cpu_to_le32(lp->tx_dma_addr[tx_index]);
1294
1295	/*  Set FCS and LTINT bits */
1296	wmb();
1297	lp->tx_ring[tx_index].tx_flags |=
1298	    cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1299
1300	lp->tx_idx++;
1301
1302	/* Trigger an immediate send poll. */
1303	writel( VAL1 | TDMD0, lp->mmio + CMD0);
1304	writel( VAL2 | RDMD0,lp->mmio + CMD0);
1305
1306	if(amd8111e_tx_queue_avail(lp) < 0){
1307		netif_stop_queue(dev);
1308	}
1309	spin_unlock_irqrestore(&lp->lock, flags);
1310	return NETDEV_TX_OK;
1311}
1312/* This function returns all the memory mapped registers of the device. */
 
 
1313static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1314{
1315	void __iomem *mmio = lp->mmio;
1316	/* Read only necessary registers */
1317	buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1318	buf[1] = readl(mmio + XMT_RING_LEN0);
1319	buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1320	buf[3] = readl(mmio + RCV_RING_LEN0);
1321	buf[4] = readl(mmio + CMD0);
1322	buf[5] = readl(mmio + CMD2);
1323	buf[6] = readl(mmio + CMD3);
1324	buf[7] = readl(mmio + CMD7);
1325	buf[8] = readl(mmio + INT0);
1326	buf[9] = readl(mmio + INTEN0);
1327	buf[10] = readl(mmio + LADRF);
1328	buf[11] = readl(mmio + LADRF+4);
1329	buf[12] = readl(mmio + STAT0);
1330}
1331
1332
1333/* This function sets promiscuos mode, all-multi mode or the multicast address
1334 * list to the device.
1335 */
 
1336static void amd8111e_set_multicast_list(struct net_device *dev)
1337{
1338	struct netdev_hw_addr *ha;
1339	struct amd8111e_priv *lp = netdev_priv(dev);
1340	u32 mc_filter[2] ;
1341	int bit_num;
1342
1343	if(dev->flags & IFF_PROMISC){
1344		writel( VAL2 | PROM, lp->mmio + CMD2);
1345		return;
1346	}
1347	else
1348		writel( PROM, lp->mmio + CMD2);
1349	if (dev->flags & IFF_ALLMULTI ||
1350	    netdev_mc_count(dev) > MAX_FILTER_SIZE) {
1351		/* get all multicast packet */
1352		mc_filter[1] = mc_filter[0] = 0xffffffff;
1353		lp->options |= OPTION_MULTICAST_ENABLE;
1354		amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1355		return;
1356	}
1357	if (netdev_mc_empty(dev)) {
1358		/* get only own packets */
1359		mc_filter[1] = mc_filter[0] = 0;
1360		lp->options &= ~OPTION_MULTICAST_ENABLE;
1361		amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1362		/* disable promiscuous mode */
1363		writel(PROM, lp->mmio + CMD2);
1364		return;
1365	}
1366	/* load all the multicast addresses in the logic filter */
1367	lp->options |= OPTION_MULTICAST_ENABLE;
1368	mc_filter[1] = mc_filter[0] = 0;
1369	netdev_for_each_mc_addr(ha, dev) {
1370		bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f;
1371		mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1372	}
1373	amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1374
1375	/* To eliminate PCI posting bug */
1376	readl(lp->mmio + CMD2);
1377
1378}
1379
1380static void amd8111e_get_drvinfo(struct net_device *dev,
1381				 struct ethtool_drvinfo *info)
1382{
1383	struct amd8111e_priv *lp = netdev_priv(dev);
1384	struct pci_dev *pci_dev = lp->pci_dev;
1385	strlcpy(info->driver, MODULE_NAME, sizeof(info->driver));
1386	strlcpy(info->version, MODULE_VERS, sizeof(info->version));
1387	snprintf(info->fw_version, sizeof(info->fw_version),
1388		"%u", chip_version);
1389	strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
1390}
1391
1392static int amd8111e_get_regs_len(struct net_device *dev)
1393{
1394	return AMD8111E_REG_DUMP_LEN;
1395}
1396
1397static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1398{
1399	struct amd8111e_priv *lp = netdev_priv(dev);
1400	regs->version = 0;
1401	amd8111e_read_regs(lp, buf);
1402}
1403
1404static int amd8111e_get_link_ksettings(struct net_device *dev,
1405				       struct ethtool_link_ksettings *cmd)
1406{
1407	struct amd8111e_priv *lp = netdev_priv(dev);
1408	spin_lock_irq(&lp->lock);
1409	mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
1410	spin_unlock_irq(&lp->lock);
1411	return 0;
1412}
1413
1414static int amd8111e_set_link_ksettings(struct net_device *dev,
1415				       const struct ethtool_link_ksettings *cmd)
1416{
1417	struct amd8111e_priv *lp = netdev_priv(dev);
1418	int res;
1419	spin_lock_irq(&lp->lock);
1420	res = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
1421	spin_unlock_irq(&lp->lock);
1422	return res;
1423}
1424
1425static int amd8111e_nway_reset(struct net_device *dev)
1426{
1427	struct amd8111e_priv *lp = netdev_priv(dev);
1428	return mii_nway_restart(&lp->mii_if);
1429}
1430
1431static u32 amd8111e_get_link(struct net_device *dev)
1432{
1433	struct amd8111e_priv *lp = netdev_priv(dev);
1434	return mii_link_ok(&lp->mii_if);
1435}
1436
1437static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1438{
1439	struct amd8111e_priv *lp = netdev_priv(dev);
1440	wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1441	if (lp->options & OPTION_WOL_ENABLE)
1442		wol_info->wolopts = WAKE_MAGIC;
1443}
1444
1445static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1446{
1447	struct amd8111e_priv *lp = netdev_priv(dev);
1448	if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1449		return -EINVAL;
1450	spin_lock_irq(&lp->lock);
1451	if (wol_info->wolopts & WAKE_MAGIC)
1452		lp->options |=
1453			(OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1454	else if(wol_info->wolopts & WAKE_PHY)
1455		lp->options |=
1456			(OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1457	else
1458		lp->options &= ~OPTION_WOL_ENABLE;
1459	spin_unlock_irq(&lp->lock);
1460	return 0;
1461}
1462
1463static const struct ethtool_ops ops = {
1464	.get_drvinfo = amd8111e_get_drvinfo,
1465	.get_regs_len = amd8111e_get_regs_len,
1466	.get_regs = amd8111e_get_regs,
 
 
1467	.nway_reset = amd8111e_nway_reset,
1468	.get_link = amd8111e_get_link,
1469	.get_wol = amd8111e_get_wol,
1470	.set_wol = amd8111e_set_wol,
1471	.get_link_ksettings = amd8111e_get_link_ksettings,
1472	.set_link_ksettings = amd8111e_set_link_ksettings,
1473};
1474
1475/* This function handles all the  ethtool ioctls. It gives driver info,
1476 * gets/sets driver speed, gets memory mapped register values, forces
1477 * auto negotiation, sets/gets WOL options for ethtool application.
1478 */
1479static int amd8111e_ioctl(struct net_device *dev , struct ifreq *ifr, int cmd)
1480{
1481	struct mii_ioctl_data *data = if_mii(ifr);
1482	struct amd8111e_priv *lp = netdev_priv(dev);
1483	int err;
1484	u32 mii_regval;
1485
1486	switch(cmd) {
1487	case SIOCGMIIPHY:
1488		data->phy_id = lp->ext_phy_addr;
1489
1490	/* fallthru */
1491	case SIOCGMIIREG:
1492
1493		spin_lock_irq(&lp->lock);
1494		err = amd8111e_read_phy(lp, data->phy_id,
1495			data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1496		spin_unlock_irq(&lp->lock);
1497
1498		data->val_out = mii_regval;
1499		return err;
1500
1501	case SIOCSMIIREG:
1502
1503		spin_lock_irq(&lp->lock);
1504		err = amd8111e_write_phy(lp, data->phy_id,
1505			data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1506		spin_unlock_irq(&lp->lock);
1507
1508		return err;
1509
1510	default:
1511		/* do nothing */
1512		break;
1513	}
1514	return -EOPNOTSUPP;
1515}
1516static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1517{
1518	struct amd8111e_priv *lp = netdev_priv(dev);
1519	int i;
1520	struct sockaddr *addr = p;
1521
1522	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1523	spin_lock_irq(&lp->lock);
1524	/* Setting the MAC address to the device */
1525	for (i = 0; i < ETH_ALEN; i++)
1526		writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1527
1528	spin_unlock_irq(&lp->lock);
1529
1530	return 0;
1531}
1532
1533/* This function changes the mtu of the device. It restarts the device  to
1534 * initialize the descriptor with new receive buffers.
1535 */
1536static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1537{
1538	struct amd8111e_priv *lp = netdev_priv(dev);
1539	int err;
1540
 
 
 
1541	if (!netif_running(dev)) {
1542		/* new_mtu will be used
1543		 * when device starts netxt time
1544		 */
1545		dev->mtu = new_mtu;
1546		return 0;
1547	}
1548
1549	spin_lock_irq(&lp->lock);
1550
1551        /* stop the chip */
1552	writel(RUN, lp->mmio + CMD0);
1553
1554	dev->mtu = new_mtu;
1555
1556	err = amd8111e_restart(dev);
1557	spin_unlock_irq(&lp->lock);
1558	if(!err)
1559		netif_start_queue(dev);
1560	return err;
1561}
1562
1563static int amd8111e_enable_magicpkt(struct amd8111e_priv *lp)
1564{
1565	writel( VAL1|MPPLBA, lp->mmio + CMD3);
1566	writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1567
1568	/* To eliminate PCI posting bug */
1569	readl(lp->mmio + CMD7);
1570	return 0;
1571}
1572
1573static int amd8111e_enable_link_change(struct amd8111e_priv *lp)
1574{
1575
1576	/* Adapter is already stoped/suspended/interrupt-disabled */
1577	writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1578
1579	/* To eliminate PCI posting bug */
1580	readl(lp->mmio + CMD7);
1581	return 0;
1582}
1583
1584/* This function is called when a packet transmission fails to complete
 
1585 * within a reasonable period, on the assumption that an interrupt have
1586 * failed or the interface is locked up. This function will reinitialize
1587 * the hardware.
1588 */
1589static void amd8111e_tx_timeout(struct net_device *dev)
1590{
1591	struct amd8111e_priv *lp = netdev_priv(dev);
1592	int err;
1593
1594	netdev_err(dev, "transmit timed out, resetting\n");
1595
1596	spin_lock_irq(&lp->lock);
1597	err = amd8111e_restart(dev);
1598	spin_unlock_irq(&lp->lock);
1599	if(!err)
1600		netif_wake_queue(dev);
1601}
1602static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1603{
1604	struct net_device *dev = pci_get_drvdata(pci_dev);
1605	struct amd8111e_priv *lp = netdev_priv(dev);
1606
1607	if (!netif_running(dev))
1608		return 0;
1609
1610	/* disable the interrupt */
1611	spin_lock_irq(&lp->lock);
1612	amd8111e_disable_interrupt(lp);
1613	spin_unlock_irq(&lp->lock);
1614
1615	netif_device_detach(dev);
1616
1617	/* stop chip */
1618	spin_lock_irq(&lp->lock);
1619	if(lp->options & OPTION_DYN_IPG_ENABLE)
1620		del_timer_sync(&lp->ipg_data.ipg_timer);
1621	amd8111e_stop_chip(lp);
1622	spin_unlock_irq(&lp->lock);
1623
1624	if(lp->options & OPTION_WOL_ENABLE){
1625		 /* enable wol */
1626		if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1627			amd8111e_enable_magicpkt(lp);
1628		if(lp->options & OPTION_WAKE_PHY_ENABLE)
1629			amd8111e_enable_link_change(lp);
1630
1631		pci_enable_wake(pci_dev, PCI_D3hot, 1);
1632		pci_enable_wake(pci_dev, PCI_D3cold, 1);
1633
1634	}
1635	else{
1636		pci_enable_wake(pci_dev, PCI_D3hot, 0);
1637		pci_enable_wake(pci_dev, PCI_D3cold, 0);
1638	}
1639
1640	pci_save_state(pci_dev);
1641	pci_set_power_state(pci_dev, PCI_D3hot);
1642
1643	return 0;
1644}
1645static int amd8111e_resume(struct pci_dev *pci_dev)
1646{
1647	struct net_device *dev = pci_get_drvdata(pci_dev);
1648	struct amd8111e_priv *lp = netdev_priv(dev);
1649
1650	if (!netif_running(dev))
1651		return 0;
1652
1653	pci_set_power_state(pci_dev, PCI_D0);
1654	pci_restore_state(pci_dev);
1655
1656	pci_enable_wake(pci_dev, PCI_D3hot, 0);
1657	pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1658
1659	netif_device_attach(dev);
1660
1661	spin_lock_irq(&lp->lock);
1662	amd8111e_restart(dev);
1663	/* Restart ipg timer */
1664	if(lp->options & OPTION_DYN_IPG_ENABLE)
1665		mod_timer(&lp->ipg_data.ipg_timer,
1666				jiffies + IPG_CONVERGE_JIFFIES);
1667	spin_unlock_irq(&lp->lock);
1668
1669	return 0;
1670}
1671
1672static void amd8111e_config_ipg(struct timer_list *t)
 
 
 
 
 
 
 
 
 
 
 
 
1673{
1674	struct amd8111e_priv *lp = from_timer(lp, t, ipg_data.ipg_timer);
1675	struct ipg_info *ipg_data = &lp->ipg_data;
1676	void __iomem *mmio = lp->mmio;
1677	unsigned int prev_col_cnt = ipg_data->col_cnt;
1678	unsigned int total_col_cnt;
1679	unsigned int tmp_ipg;
1680
1681	if(lp->link_config.duplex == DUPLEX_FULL){
1682		ipg_data->ipg = DEFAULT_IPG;
1683		return;
1684	}
1685
1686	if(ipg_data->ipg_state == SSTATE){
1687
1688		if(ipg_data->timer_tick == IPG_STABLE_TIME){
1689
1690			ipg_data->timer_tick = 0;
1691			ipg_data->ipg = MIN_IPG - IPG_STEP;
1692			ipg_data->current_ipg = MIN_IPG;
1693			ipg_data->diff_col_cnt = 0xFFFFFFFF;
1694			ipg_data->ipg_state = CSTATE;
1695		}
1696		else
1697			ipg_data->timer_tick++;
1698	}
1699
1700	if(ipg_data->ipg_state == CSTATE){
1701
1702		/* Get the current collision count */
1703
1704		total_col_cnt = ipg_data->col_cnt =
1705				amd8111e_read_mib(mmio, xmt_collisions);
1706
1707		if ((total_col_cnt - prev_col_cnt) <
1708				(ipg_data->diff_col_cnt)){
1709
1710			ipg_data->diff_col_cnt =
1711				total_col_cnt - prev_col_cnt ;
1712
1713			ipg_data->ipg = ipg_data->current_ipg;
1714		}
1715
1716		ipg_data->current_ipg += IPG_STEP;
1717
1718		if (ipg_data->current_ipg <= MAX_IPG)
1719			tmp_ipg = ipg_data->current_ipg;
1720		else{
1721			tmp_ipg = ipg_data->ipg;
1722			ipg_data->ipg_state = SSTATE;
1723		}
1724		writew((u32)tmp_ipg, mmio + IPG);
1725		writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1726	}
1727	 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1728	return;
1729
1730}
1731
1732static void amd8111e_probe_ext_phy(struct net_device *dev)
1733{
1734	struct amd8111e_priv *lp = netdev_priv(dev);
1735	int i;
1736
1737	for (i = 0x1e; i >= 0; i--) {
1738		u32 id1, id2;
1739
1740		if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1741			continue;
1742		if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1743			continue;
1744		lp->ext_phy_id = (id1 << 16) | id2;
1745		lp->ext_phy_addr = i;
1746		return;
1747	}
1748	lp->ext_phy_id = 0;
1749	lp->ext_phy_addr = 1;
1750}
1751
1752static const struct net_device_ops amd8111e_netdev_ops = {
1753	.ndo_open		= amd8111e_open,
1754	.ndo_stop		= amd8111e_close,
1755	.ndo_start_xmit		= amd8111e_start_xmit,
1756	.ndo_tx_timeout		= amd8111e_tx_timeout,
1757	.ndo_get_stats		= amd8111e_get_stats,
1758	.ndo_set_rx_mode	= amd8111e_set_multicast_list,
1759	.ndo_validate_addr	= eth_validate_addr,
1760	.ndo_set_mac_address	= amd8111e_set_mac_address,
1761	.ndo_do_ioctl		= amd8111e_ioctl,
1762	.ndo_change_mtu		= amd8111e_change_mtu,
1763#ifdef CONFIG_NET_POLL_CONTROLLER
1764	.ndo_poll_controller	 = amd8111e_poll,
1765#endif
1766};
1767
1768static int amd8111e_probe_one(struct pci_dev *pdev,
1769				  const struct pci_device_id *ent)
1770{
1771	int err, i;
1772	unsigned long reg_addr,reg_len;
1773	struct amd8111e_priv *lp;
1774	struct net_device *dev;
1775
1776	err = pci_enable_device(pdev);
1777	if(err){
1778		dev_err(&pdev->dev, "Cannot enable new PCI device\n");
 
1779		return err;
1780	}
1781
1782	if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1783		dev_err(&pdev->dev, "Cannot find PCI base address\n");
 
1784		err = -ENODEV;
1785		goto err_disable_pdev;
1786	}
1787
1788	err = pci_request_regions(pdev, MODULE_NAME);
1789	if(err){
1790		dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 
1791		goto err_disable_pdev;
1792	}
1793
1794	pci_set_master(pdev);
1795
1796	/* Find power-management capability. */
1797	if (!pdev->pm_cap) {
1798		dev_err(&pdev->dev, "No Power Management capability\n");
 
1799		err = -ENODEV;
1800		goto err_free_reg;
1801	}
1802
1803	/* Initialize DMA */
1804	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) {
1805		dev_err(&pdev->dev, "DMA not supported\n");
 
1806		err = -ENODEV;
1807		goto err_free_reg;
1808	}
1809
1810	reg_addr = pci_resource_start(pdev, 0);
1811	reg_len = pci_resource_len(pdev, 0);
1812
1813	dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1814	if (!dev) {
1815		err = -ENOMEM;
1816		goto err_free_reg;
1817	}
1818
1819	SET_NETDEV_DEV(dev, &pdev->dev);
1820
1821#if AMD8111E_VLAN_TAG_USED
1822	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX ;
1823#endif
1824
1825	lp = netdev_priv(dev);
1826	lp->pci_dev = pdev;
1827	lp->amd8111e_net_dev = dev;
1828	lp->pm_cap = pdev->pm_cap;
1829
1830	spin_lock_init(&lp->lock);
1831
1832	lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len);
1833	if (!lp->mmio) {
1834		dev_err(&pdev->dev, "Cannot map device registers\n");
 
1835		err = -ENOMEM;
1836		goto err_free_dev;
1837	}
1838
1839	/* Initializing MAC address */
1840	for (i = 0; i < ETH_ALEN; i++)
1841		dev->dev_addr[i] = readb(lp->mmio + PADR + i);
1842
1843	/* Setting user defined parametrs */
1844	lp->ext_phy_option = speed_duplex[card_idx];
1845	if(coalesce[card_idx])
1846		lp->options |= OPTION_INTR_COAL_ENABLE;
1847	if(dynamic_ipg[card_idx++])
1848		lp->options |= OPTION_DYN_IPG_ENABLE;
1849
1850
1851	/* Initialize driver entry points */
1852	dev->netdev_ops = &amd8111e_netdev_ops;
1853	dev->ethtool_ops = &ops;
1854	dev->irq =pdev->irq;
1855	dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1856	dev->min_mtu = AMD8111E_MIN_MTU;
1857	dev->max_mtu = AMD8111E_MAX_MTU;
1858	netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1859
1860#if AMD8111E_VLAN_TAG_USED
1861	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1862#endif
1863	/* Probe the external PHY */
1864	amd8111e_probe_ext_phy(dev);
1865
1866	/* setting mii default values */
1867	lp->mii_if.dev = dev;
1868	lp->mii_if.mdio_read = amd8111e_mdio_read;
1869	lp->mii_if.mdio_write = amd8111e_mdio_write;
1870	lp->mii_if.phy_id = lp->ext_phy_addr;
1871
1872	/* Set receive buffer length and set jumbo option*/
1873	amd8111e_set_rx_buff_len(dev);
1874
1875
1876	err = register_netdev(dev);
1877	if (err) {
1878		dev_err(&pdev->dev, "Cannot register net device\n");
1879		goto err_free_dev;
 
1880	}
1881
1882	pci_set_drvdata(pdev, dev);
1883
1884	/* Initialize software ipg timer */
1885	if(lp->options & OPTION_DYN_IPG_ENABLE){
1886		timer_setup(&lp->ipg_data.ipg_timer, amd8111e_config_ipg, 0);
 
 
1887		lp->ipg_data.ipg_timer.expires = jiffies +
1888						 IPG_CONVERGE_JIFFIES;
1889		lp->ipg_data.ipg = DEFAULT_IPG;
1890		lp->ipg_data.ipg_state = CSTATE;
1891	}
1892
1893	/*  display driver and device information */
 
1894    	chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
1895	dev_info(&pdev->dev, "AMD-8111e Driver Version: %s\n", MODULE_VERS);
1896	dev_info(&pdev->dev, "[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1897		 chip_version, dev->dev_addr);
 
1898	if (lp->ext_phy_id)
1899		dev_info(&pdev->dev, "Found MII PHY ID 0x%08x at address 0x%02x\n",
1900			 lp->ext_phy_id, lp->ext_phy_addr);
1901	else
1902		dev_info(&pdev->dev, "Couldn't detect MII PHY, assuming address 0x01\n");
1903
1904    	return 0;
 
 
1905
1906err_free_dev:
1907	free_netdev(dev);
1908
1909err_free_reg:
1910	pci_release_regions(pdev);
1911
1912err_disable_pdev:
1913	pci_disable_device(pdev);
1914	return err;
1915
1916}
1917
1918static void amd8111e_remove_one(struct pci_dev *pdev)
1919{
1920	struct net_device *dev = pci_get_drvdata(pdev);
1921
1922	if (dev) {
1923		unregister_netdev(dev);
1924		free_netdev(dev);
1925		pci_release_regions(pdev);
1926		pci_disable_device(pdev);
1927	}
1928}
1929
1930static const struct pci_device_id amd8111e_pci_tbl[] = {
1931	{
1932	 .vendor = PCI_VENDOR_ID_AMD,
1933	 .device = PCI_DEVICE_ID_AMD8111E_7462,
1934	},
1935	{
1936	 .vendor = 0,
1937	}
1938};
1939MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
1940
1941static struct pci_driver amd8111e_driver = {
1942	.name   	= MODULE_NAME,
1943	.id_table	= amd8111e_pci_tbl,
1944	.probe		= amd8111e_probe_one,
1945	.remove		= amd8111e_remove_one,
1946	.suspend	= amd8111e_suspend,
1947	.resume		= amd8111e_resume
1948};
1949
1950module_pci_driver(amd8111e_driver);