Loading...
Note: File does not exist in v3.15.
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "cikd.h"
30#include "cik.h"
31
32#include "bif/bif_4_1_d.h"
33#include "bif/bif_4_1_sh_mask.h"
34
35#include "gca/gfx_7_2_d.h"
36#include "gca/gfx_7_2_enum.h"
37#include "gca/gfx_7_2_sh_mask.h"
38
39#include "gmc/gmc_7_1_d.h"
40#include "gmc/gmc_7_1_sh_mask.h"
41
42#include "oss/oss_2_0_d.h"
43#include "oss/oss_2_0_sh_mask.h"
44
45static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
46{
47 SDMA0_REGISTER_OFFSET,
48 SDMA1_REGISTER_OFFSET
49};
50
51static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55static int cik_sdma_soft_reset(void *handle);
56
57MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
58MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
59MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
60MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
61MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
62MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
63MODULE_FIRMWARE("radeon/kabini_sdma.bin");
64MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
65MODULE_FIRMWARE("radeon/mullins_sdma.bin");
66MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
67
68u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
69
70
71static void cik_sdma_free_microcode(struct amdgpu_device *adev)
72{
73 int i;
74 for (i = 0; i < adev->sdma.num_instances; i++) {
75 release_firmware(adev->sdma.instance[i].fw);
76 adev->sdma.instance[i].fw = NULL;
77 }
78}
79
80/*
81 * sDMA - System DMA
82 * Starting with CIK, the GPU has new asynchronous
83 * DMA engines. These engines are used for compute
84 * and gfx. There are two DMA engines (SDMA0, SDMA1)
85 * and each one supports 1 ring buffer used for gfx
86 * and 2 queues used for compute.
87 *
88 * The programming model is very similar to the CP
89 * (ring buffer, IBs, etc.), but sDMA has it's own
90 * packet format that is different from the PM4 format
91 * used by the CP. sDMA supports copying data, writing
92 * embedded data, solid fills, and a number of other
93 * things. It also has support for tiling/detiling of
94 * buffers.
95 */
96
97/**
98 * cik_sdma_init_microcode - load ucode images from disk
99 *
100 * @adev: amdgpu_device pointer
101 *
102 * Use the firmware interface to load the ucode images into
103 * the driver (not loaded into hw).
104 * Returns 0 on success, error on failure.
105 */
106static int cik_sdma_init_microcode(struct amdgpu_device *adev)
107{
108 const char *chip_name;
109 char fw_name[30];
110 int err = 0, i;
111
112 DRM_DEBUG("\n");
113
114 switch (adev->asic_type) {
115 case CHIP_BONAIRE:
116 chip_name = "bonaire";
117 break;
118 case CHIP_HAWAII:
119 chip_name = "hawaii";
120 break;
121 case CHIP_KAVERI:
122 chip_name = "kaveri";
123 break;
124 case CHIP_KABINI:
125 chip_name = "kabini";
126 break;
127 case CHIP_MULLINS:
128 chip_name = "mullins";
129 break;
130 default: BUG();
131 }
132
133 for (i = 0; i < adev->sdma.num_instances; i++) {
134 if (i == 0)
135 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
136 else
137 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
138 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
139 if (err)
140 goto out;
141 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
142 }
143out:
144 if (err) {
145 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
146 for (i = 0; i < adev->sdma.num_instances; i++) {
147 release_firmware(adev->sdma.instance[i].fw);
148 adev->sdma.instance[i].fw = NULL;
149 }
150 }
151 return err;
152}
153
154/**
155 * cik_sdma_ring_get_rptr - get the current read pointer
156 *
157 * @ring: amdgpu ring pointer
158 *
159 * Get the current rptr from the hardware (CIK+).
160 */
161static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
162{
163 u32 rptr;
164
165 rptr = ring->adev->wb.wb[ring->rptr_offs];
166
167 return (rptr & 0x3fffc) >> 2;
168}
169
170/**
171 * cik_sdma_ring_get_wptr - get the current write pointer
172 *
173 * @ring: amdgpu ring pointer
174 *
175 * Get the current wptr from the hardware (CIK+).
176 */
177static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
178{
179 struct amdgpu_device *adev = ring->adev;
180 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
181
182 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
183}
184
185/**
186 * cik_sdma_ring_set_wptr - commit the write pointer
187 *
188 * @ring: amdgpu ring pointer
189 *
190 * Write the wptr back to the hardware (CIK+).
191 */
192static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
193{
194 struct amdgpu_device *adev = ring->adev;
195 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
196
197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
198 (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
199}
200
201static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
202{
203 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
204 int i;
205
206 for (i = 0; i < count; i++)
207 if (sdma && sdma->burst_nop && (i == 0))
208 amdgpu_ring_write(ring, ring->funcs->nop |
209 SDMA_NOP_COUNT(count - 1));
210 else
211 amdgpu_ring_write(ring, ring->funcs->nop);
212}
213
214/**
215 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
216 *
217 * @ring: amdgpu ring pointer
218 * @ib: IB object to schedule
219 *
220 * Schedule an IB in the DMA ring (CIK).
221 */
222static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
223 struct amdgpu_ib *ib,
224 unsigned vmid, bool ctx_switch)
225{
226 u32 extra_bits = vmid & 0xf;
227
228 /* IB packet must end on a 8 DW boundary */
229 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
230
231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
234 amdgpu_ring_write(ring, ib->length_dw);
235
236}
237
238/**
239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
240 *
241 * @ring: amdgpu ring pointer
242 *
243 * Emit an hdp flush packet on the requested DMA ring.
244 */
245static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
246{
247 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
249 u32 ref_and_mask;
250
251 if (ring == &ring->adev->sdma.instance[0].ring)
252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
253 else
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
255
256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */
260 amdgpu_ring_write(ring, ref_and_mask); /* mask */
261 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
262}
263
264/**
265 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
266 *
267 * @ring: amdgpu ring pointer
268 * @fence: amdgpu fence object
269 *
270 * Add a DMA fence packet to the ring to write
271 * the fence seq number and DMA trap packet to generate
272 * an interrupt if needed (CIK).
273 */
274static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
275 unsigned flags)
276{
277 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
278 /* write the fence */
279 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
280 amdgpu_ring_write(ring, lower_32_bits(addr));
281 amdgpu_ring_write(ring, upper_32_bits(addr));
282 amdgpu_ring_write(ring, lower_32_bits(seq));
283
284 /* optionally write high bits as well */
285 if (write64bit) {
286 addr += 4;
287 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
288 amdgpu_ring_write(ring, lower_32_bits(addr));
289 amdgpu_ring_write(ring, upper_32_bits(addr));
290 amdgpu_ring_write(ring, upper_32_bits(seq));
291 }
292
293 /* generate an interrupt */
294 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
295}
296
297/**
298 * cik_sdma_gfx_stop - stop the gfx async dma engines
299 *
300 * @adev: amdgpu_device pointer
301 *
302 * Stop the gfx async dma ring buffers (CIK).
303 */
304static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
305{
306 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
307 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
308 u32 rb_cntl;
309 int i;
310
311 if ((adev->mman.buffer_funcs_ring == sdma0) ||
312 (adev->mman.buffer_funcs_ring == sdma1))
313 amdgpu_ttm_set_buffer_funcs_status(adev, false);
314
315 for (i = 0; i < adev->sdma.num_instances; i++) {
316 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
317 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
318 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
319 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
320 }
321 sdma0->ready = false;
322 sdma1->ready = false;
323}
324
325/**
326 * cik_sdma_rlc_stop - stop the compute async dma engines
327 *
328 * @adev: amdgpu_device pointer
329 *
330 * Stop the compute async dma queues (CIK).
331 */
332static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
333{
334 /* XXX todo */
335}
336
337/**
338 * cik_ctx_switch_enable - stop the async dma engines context switch
339 *
340 * @adev: amdgpu_device pointer
341 * @enable: enable/disable the DMA MEs context switch.
342 *
343 * Halt or unhalt the async dma engines context switch (VI).
344 */
345static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
346{
347 u32 f32_cntl, phase_quantum = 0;
348 int i;
349
350 if (amdgpu_sdma_phase_quantum) {
351 unsigned value = amdgpu_sdma_phase_quantum;
352 unsigned unit = 0;
353
354 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
355 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
356 value = (value + 1) >> 1;
357 unit++;
358 }
359 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
360 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
361 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
363 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
364 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
365 WARN_ONCE(1,
366 "clamping sdma_phase_quantum to %uK clock cycles\n",
367 value << unit);
368 }
369 phase_quantum =
370 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
371 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
372 }
373
374 for (i = 0; i < adev->sdma.num_instances; i++) {
375 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
376 if (enable) {
377 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
378 AUTO_CTXSW_ENABLE, 1);
379 if (amdgpu_sdma_phase_quantum) {
380 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
381 phase_quantum);
382 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
383 phase_quantum);
384 }
385 } else {
386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
387 AUTO_CTXSW_ENABLE, 0);
388 }
389
390 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
391 }
392}
393
394/**
395 * cik_sdma_enable - stop the async dma engines
396 *
397 * @adev: amdgpu_device pointer
398 * @enable: enable/disable the DMA MEs.
399 *
400 * Halt or unhalt the async dma engines (CIK).
401 */
402static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
403{
404 u32 me_cntl;
405 int i;
406
407 if (!enable) {
408 cik_sdma_gfx_stop(adev);
409 cik_sdma_rlc_stop(adev);
410 }
411
412 for (i = 0; i < adev->sdma.num_instances; i++) {
413 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
414 if (enable)
415 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
416 else
417 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
418 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
419 }
420}
421
422/**
423 * cik_sdma_gfx_resume - setup and start the async dma engines
424 *
425 * @adev: amdgpu_device pointer
426 *
427 * Set up the gfx DMA ring buffers and enable them (CIK).
428 * Returns 0 for success, error for failure.
429 */
430static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
431{
432 struct amdgpu_ring *ring;
433 u32 rb_cntl, ib_cntl;
434 u32 rb_bufsz;
435 u32 wb_offset;
436 int i, j, r;
437
438 for (i = 0; i < adev->sdma.num_instances; i++) {
439 ring = &adev->sdma.instance[i].ring;
440 wb_offset = (ring->rptr_offs * 4);
441
442 mutex_lock(&adev->srbm_mutex);
443 for (j = 0; j < 16; j++) {
444 cik_srbm_select(adev, 0, 0, 0, j);
445 /* SDMA GFX */
446 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
447 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
448 /* XXX SDMA RLC - todo */
449 }
450 cik_srbm_select(adev, 0, 0, 0, 0);
451 mutex_unlock(&adev->srbm_mutex);
452
453 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
454 adev->gfx.config.gb_addr_config & 0x70);
455
456 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
457 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
458
459 /* Set ring buffer size in dwords */
460 rb_bufsz = order_base_2(ring->ring_size / 4);
461 rb_cntl = rb_bufsz << 1;
462#ifdef __BIG_ENDIAN
463 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
464 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
465#endif
466 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
467
468 /* Initialize the ring buffer's read and write pointers */
469 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
470 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
471 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
472 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
473
474 /* set the wb address whether it's enabled or not */
475 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
476 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
477 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
478 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
479
480 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
481
482 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
483 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
484
485 ring->wptr = 0;
486 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
487
488 /* enable DMA RB */
489 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
490 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
491
492 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
493#ifdef __BIG_ENDIAN
494 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
495#endif
496 /* enable DMA IBs */
497 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
498
499 ring->ready = true;
500 }
501
502 cik_sdma_enable(adev, true);
503
504 for (i = 0; i < adev->sdma.num_instances; i++) {
505 ring = &adev->sdma.instance[i].ring;
506 r = amdgpu_ring_test_ring(ring);
507 if (r) {
508 ring->ready = false;
509 return r;
510 }
511
512 if (adev->mman.buffer_funcs_ring == ring)
513 amdgpu_ttm_set_buffer_funcs_status(adev, true);
514 }
515
516 return 0;
517}
518
519/**
520 * cik_sdma_rlc_resume - setup and start the async dma engines
521 *
522 * @adev: amdgpu_device pointer
523 *
524 * Set up the compute DMA queues and enable them (CIK).
525 * Returns 0 for success, error for failure.
526 */
527static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
528{
529 /* XXX todo */
530 return 0;
531}
532
533/**
534 * cik_sdma_load_microcode - load the sDMA ME ucode
535 *
536 * @adev: amdgpu_device pointer
537 *
538 * Loads the sDMA0/1 ucode.
539 * Returns 0 for success, -EINVAL if the ucode is not available.
540 */
541static int cik_sdma_load_microcode(struct amdgpu_device *adev)
542{
543 const struct sdma_firmware_header_v1_0 *hdr;
544 const __le32 *fw_data;
545 u32 fw_size;
546 int i, j;
547
548 /* halt the MEs */
549 cik_sdma_enable(adev, false);
550
551 for (i = 0; i < adev->sdma.num_instances; i++) {
552 if (!adev->sdma.instance[i].fw)
553 return -EINVAL;
554 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
555 amdgpu_ucode_print_sdma_hdr(&hdr->header);
556 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
557 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
558 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
559 if (adev->sdma.instance[i].feature_version >= 20)
560 adev->sdma.instance[i].burst_nop = true;
561 fw_data = (const __le32 *)
562 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
563 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
564 for (j = 0; j < fw_size; j++)
565 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
566 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
567 }
568
569 return 0;
570}
571
572/**
573 * cik_sdma_start - setup and start the async dma engines
574 *
575 * @adev: amdgpu_device pointer
576 *
577 * Set up the DMA engines and enable them (CIK).
578 * Returns 0 for success, error for failure.
579 */
580static int cik_sdma_start(struct amdgpu_device *adev)
581{
582 int r;
583
584 r = cik_sdma_load_microcode(adev);
585 if (r)
586 return r;
587
588 /* halt the engine before programing */
589 cik_sdma_enable(adev, false);
590 /* enable sdma ring preemption */
591 cik_ctx_switch_enable(adev, true);
592
593 /* start the gfx rings and rlc compute queues */
594 r = cik_sdma_gfx_resume(adev);
595 if (r)
596 return r;
597 r = cik_sdma_rlc_resume(adev);
598 if (r)
599 return r;
600
601 return 0;
602}
603
604/**
605 * cik_sdma_ring_test_ring - simple async dma engine test
606 *
607 * @ring: amdgpu_ring structure holding ring information
608 *
609 * Test the DMA engine by writing using it to write an
610 * value to memory. (CIK).
611 * Returns 0 for success, error for failure.
612 */
613static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
614{
615 struct amdgpu_device *adev = ring->adev;
616 unsigned i;
617 unsigned index;
618 int r;
619 u32 tmp;
620 u64 gpu_addr;
621
622 r = amdgpu_device_wb_get(adev, &index);
623 if (r) {
624 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
625 return r;
626 }
627
628 gpu_addr = adev->wb.gpu_addr + (index * 4);
629 tmp = 0xCAFEDEAD;
630 adev->wb.wb[index] = cpu_to_le32(tmp);
631
632 r = amdgpu_ring_alloc(ring, 5);
633 if (r) {
634 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
635 amdgpu_device_wb_free(adev, index);
636 return r;
637 }
638 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
639 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
640 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
641 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
642 amdgpu_ring_write(ring, 0xDEADBEEF);
643 amdgpu_ring_commit(ring);
644
645 for (i = 0; i < adev->usec_timeout; i++) {
646 tmp = le32_to_cpu(adev->wb.wb[index]);
647 if (tmp == 0xDEADBEEF)
648 break;
649 DRM_UDELAY(1);
650 }
651
652 if (i < adev->usec_timeout) {
653 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
654 } else {
655 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
656 ring->idx, tmp);
657 r = -EINVAL;
658 }
659 amdgpu_device_wb_free(adev, index);
660
661 return r;
662}
663
664/**
665 * cik_sdma_ring_test_ib - test an IB on the DMA engine
666 *
667 * @ring: amdgpu_ring structure holding ring information
668 *
669 * Test a simple IB in the DMA ring (CIK).
670 * Returns 0 on success, error on failure.
671 */
672static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
673{
674 struct amdgpu_device *adev = ring->adev;
675 struct amdgpu_ib ib;
676 struct dma_fence *f = NULL;
677 unsigned index;
678 u32 tmp = 0;
679 u64 gpu_addr;
680 long r;
681
682 r = amdgpu_device_wb_get(adev, &index);
683 if (r) {
684 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
685 return r;
686 }
687
688 gpu_addr = adev->wb.gpu_addr + (index * 4);
689 tmp = 0xCAFEDEAD;
690 adev->wb.wb[index] = cpu_to_le32(tmp);
691 memset(&ib, 0, sizeof(ib));
692 r = amdgpu_ib_get(adev, NULL, 256, &ib);
693 if (r) {
694 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
695 goto err0;
696 }
697
698 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
699 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
700 ib.ptr[1] = lower_32_bits(gpu_addr);
701 ib.ptr[2] = upper_32_bits(gpu_addr);
702 ib.ptr[3] = 1;
703 ib.ptr[4] = 0xDEADBEEF;
704 ib.length_dw = 5;
705 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
706 if (r)
707 goto err1;
708
709 r = dma_fence_wait_timeout(f, false, timeout);
710 if (r == 0) {
711 DRM_ERROR("amdgpu: IB test timed out\n");
712 r = -ETIMEDOUT;
713 goto err1;
714 } else if (r < 0) {
715 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
716 goto err1;
717 }
718 tmp = le32_to_cpu(adev->wb.wb[index]);
719 if (tmp == 0xDEADBEEF) {
720 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
721 r = 0;
722 } else {
723 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
724 r = -EINVAL;
725 }
726
727err1:
728 amdgpu_ib_free(adev, &ib, NULL);
729 dma_fence_put(f);
730err0:
731 amdgpu_device_wb_free(adev, index);
732 return r;
733}
734
735/**
736 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
737 *
738 * @ib: indirect buffer to fill with commands
739 * @pe: addr of the page entry
740 * @src: src addr to copy from
741 * @count: number of page entries to update
742 *
743 * Update PTEs by copying them from the GART using sDMA (CIK).
744 */
745static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
746 uint64_t pe, uint64_t src,
747 unsigned count)
748{
749 unsigned bytes = count * 8;
750
751 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
752 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
753 ib->ptr[ib->length_dw++] = bytes;
754 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
755 ib->ptr[ib->length_dw++] = lower_32_bits(src);
756 ib->ptr[ib->length_dw++] = upper_32_bits(src);
757 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
758 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
759}
760
761/**
762 * cik_sdma_vm_write_pages - update PTEs by writing them manually
763 *
764 * @ib: indirect buffer to fill with commands
765 * @pe: addr of the page entry
766 * @value: dst addr to write into pe
767 * @count: number of page entries to update
768 * @incr: increase next addr by incr bytes
769 *
770 * Update PTEs by writing them manually using sDMA (CIK).
771 */
772static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
773 uint64_t value, unsigned count,
774 uint32_t incr)
775{
776 unsigned ndw = count * 2;
777
778 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
779 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
780 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
781 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
782 ib->ptr[ib->length_dw++] = ndw;
783 for (; ndw > 0; ndw -= 2) {
784 ib->ptr[ib->length_dw++] = lower_32_bits(value);
785 ib->ptr[ib->length_dw++] = upper_32_bits(value);
786 value += incr;
787 }
788}
789
790/**
791 * cik_sdma_vm_set_pages - update the page tables using sDMA
792 *
793 * @ib: indirect buffer to fill with commands
794 * @pe: addr of the page entry
795 * @addr: dst addr to write into pe
796 * @count: number of page entries to update
797 * @incr: increase next addr by incr bytes
798 * @flags: access flags
799 *
800 * Update the page tables using sDMA (CIK).
801 */
802static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
803 uint64_t addr, unsigned count,
804 uint32_t incr, uint64_t flags)
805{
806 /* for physically contiguous pages (vram) */
807 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
808 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
809 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
810 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
811 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
812 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
813 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
814 ib->ptr[ib->length_dw++] = incr; /* increment size */
815 ib->ptr[ib->length_dw++] = 0;
816 ib->ptr[ib->length_dw++] = count; /* number of entries */
817}
818
819/**
820 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
821 *
822 * @ib: indirect buffer to fill with padding
823 *
824 */
825static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
826{
827 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
828 u32 pad_count;
829 int i;
830
831 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
832 for (i = 0; i < pad_count; i++)
833 if (sdma && sdma->burst_nop && (i == 0))
834 ib->ptr[ib->length_dw++] =
835 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
836 SDMA_NOP_COUNT(pad_count - 1);
837 else
838 ib->ptr[ib->length_dw++] =
839 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
840}
841
842/**
843 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
844 *
845 * @ring: amdgpu_ring pointer
846 *
847 * Make sure all previous operations are completed (CIK).
848 */
849static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
850{
851 uint32_t seq = ring->fence_drv.sync_seq;
852 uint64_t addr = ring->fence_drv.gpu_addr;
853
854 /* wait for idle */
855 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
856 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
857 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
858 SDMA_POLL_REG_MEM_EXTRA_M));
859 amdgpu_ring_write(ring, addr & 0xfffffffc);
860 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
861 amdgpu_ring_write(ring, seq); /* reference */
862 amdgpu_ring_write(ring, 0xffffffff); /* mask */
863 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
864}
865
866/**
867 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
868 *
869 * @ring: amdgpu_ring pointer
870 * @vm: amdgpu_vm pointer
871 *
872 * Update the page table base and flush the VM TLB
873 * using sDMA (CIK).
874 */
875static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
876 unsigned vmid, uint64_t pd_addr)
877{
878 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
879 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
880
881 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
882
883 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
884 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
885 amdgpu_ring_write(ring, 0);
886 amdgpu_ring_write(ring, 0); /* reference */
887 amdgpu_ring_write(ring, 0); /* mask */
888 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
889}
890
891static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
892 uint32_t reg, uint32_t val)
893{
894 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
895 amdgpu_ring_write(ring, reg);
896 amdgpu_ring_write(ring, val);
897}
898
899static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
900 bool enable)
901{
902 u32 orig, data;
903
904 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
905 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
906 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
907 } else {
908 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
909 data |= 0xff000000;
910 if (data != orig)
911 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
912
913 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
914 data |= 0xff000000;
915 if (data != orig)
916 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
917 }
918}
919
920static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
921 bool enable)
922{
923 u32 orig, data;
924
925 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
926 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
927 data |= 0x100;
928 if (orig != data)
929 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
930
931 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
932 data |= 0x100;
933 if (orig != data)
934 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
935 } else {
936 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
937 data &= ~0x100;
938 if (orig != data)
939 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
940
941 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
942 data &= ~0x100;
943 if (orig != data)
944 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
945 }
946}
947
948static int cik_sdma_early_init(void *handle)
949{
950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
951
952 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
953
954 cik_sdma_set_ring_funcs(adev);
955 cik_sdma_set_irq_funcs(adev);
956 cik_sdma_set_buffer_funcs(adev);
957 cik_sdma_set_vm_pte_funcs(adev);
958
959 return 0;
960}
961
962static int cik_sdma_sw_init(void *handle)
963{
964 struct amdgpu_ring *ring;
965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
966 int r, i;
967
968 r = cik_sdma_init_microcode(adev);
969 if (r) {
970 DRM_ERROR("Failed to load sdma firmware!\n");
971 return r;
972 }
973
974 /* SDMA trap event */
975 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
976 &adev->sdma.trap_irq);
977 if (r)
978 return r;
979
980 /* SDMA Privileged inst */
981 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
982 &adev->sdma.illegal_inst_irq);
983 if (r)
984 return r;
985
986 /* SDMA Privileged inst */
987 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
988 &adev->sdma.illegal_inst_irq);
989 if (r)
990 return r;
991
992 for (i = 0; i < adev->sdma.num_instances; i++) {
993 ring = &adev->sdma.instance[i].ring;
994 ring->ring_obj = NULL;
995 sprintf(ring->name, "sdma%d", i);
996 r = amdgpu_ring_init(adev, ring, 1024,
997 &adev->sdma.trap_irq,
998 (i == 0) ?
999 AMDGPU_SDMA_IRQ_TRAP0 :
1000 AMDGPU_SDMA_IRQ_TRAP1);
1001 if (r)
1002 return r;
1003 }
1004
1005 return r;
1006}
1007
1008static int cik_sdma_sw_fini(void *handle)
1009{
1010 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1011 int i;
1012
1013 for (i = 0; i < adev->sdma.num_instances; i++)
1014 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1015
1016 cik_sdma_free_microcode(adev);
1017 return 0;
1018}
1019
1020static int cik_sdma_hw_init(void *handle)
1021{
1022 int r;
1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025 r = cik_sdma_start(adev);
1026 if (r)
1027 return r;
1028
1029 return r;
1030}
1031
1032static int cik_sdma_hw_fini(void *handle)
1033{
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036 cik_ctx_switch_enable(adev, false);
1037 cik_sdma_enable(adev, false);
1038
1039 return 0;
1040}
1041
1042static int cik_sdma_suspend(void *handle)
1043{
1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045
1046 return cik_sdma_hw_fini(adev);
1047}
1048
1049static int cik_sdma_resume(void *handle)
1050{
1051 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053 cik_sdma_soft_reset(handle);
1054
1055 return cik_sdma_hw_init(adev);
1056}
1057
1058static bool cik_sdma_is_idle(void *handle)
1059{
1060 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1061 u32 tmp = RREG32(mmSRBM_STATUS2);
1062
1063 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1064 SRBM_STATUS2__SDMA1_BUSY_MASK))
1065 return false;
1066
1067 return true;
1068}
1069
1070static int cik_sdma_wait_for_idle(void *handle)
1071{
1072 unsigned i;
1073 u32 tmp;
1074 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1075
1076 for (i = 0; i < adev->usec_timeout; i++) {
1077 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1078 SRBM_STATUS2__SDMA1_BUSY_MASK);
1079
1080 if (!tmp)
1081 return 0;
1082 udelay(1);
1083 }
1084 return -ETIMEDOUT;
1085}
1086
1087static int cik_sdma_soft_reset(void *handle)
1088{
1089 u32 srbm_soft_reset = 0;
1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1091 u32 tmp = RREG32(mmSRBM_STATUS2);
1092
1093 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1094 /* sdma0 */
1095 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1096 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1097 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1098 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1099 }
1100 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1101 /* sdma1 */
1102 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1103 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1104 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1105 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1106 }
1107
1108 if (srbm_soft_reset) {
1109 tmp = RREG32(mmSRBM_SOFT_RESET);
1110 tmp |= srbm_soft_reset;
1111 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1112 WREG32(mmSRBM_SOFT_RESET, tmp);
1113 tmp = RREG32(mmSRBM_SOFT_RESET);
1114
1115 udelay(50);
1116
1117 tmp &= ~srbm_soft_reset;
1118 WREG32(mmSRBM_SOFT_RESET, tmp);
1119 tmp = RREG32(mmSRBM_SOFT_RESET);
1120
1121 /* Wait a little for things to settle down */
1122 udelay(50);
1123 }
1124
1125 return 0;
1126}
1127
1128static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1129 struct amdgpu_irq_src *src,
1130 unsigned type,
1131 enum amdgpu_interrupt_state state)
1132{
1133 u32 sdma_cntl;
1134
1135 switch (type) {
1136 case AMDGPU_SDMA_IRQ_TRAP0:
1137 switch (state) {
1138 case AMDGPU_IRQ_STATE_DISABLE:
1139 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1140 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1141 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1142 break;
1143 case AMDGPU_IRQ_STATE_ENABLE:
1144 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1145 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1146 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1147 break;
1148 default:
1149 break;
1150 }
1151 break;
1152 case AMDGPU_SDMA_IRQ_TRAP1:
1153 switch (state) {
1154 case AMDGPU_IRQ_STATE_DISABLE:
1155 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1156 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1157 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1158 break;
1159 case AMDGPU_IRQ_STATE_ENABLE:
1160 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1161 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1162 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1163 break;
1164 default:
1165 break;
1166 }
1167 break;
1168 default:
1169 break;
1170 }
1171 return 0;
1172}
1173
1174static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1175 struct amdgpu_irq_src *source,
1176 struct amdgpu_iv_entry *entry)
1177{
1178 u8 instance_id, queue_id;
1179
1180 instance_id = (entry->ring_id & 0x3) >> 0;
1181 queue_id = (entry->ring_id & 0xc) >> 2;
1182 DRM_DEBUG("IH: SDMA trap\n");
1183 switch (instance_id) {
1184 case 0:
1185 switch (queue_id) {
1186 case 0:
1187 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1188 break;
1189 case 1:
1190 /* XXX compute */
1191 break;
1192 case 2:
1193 /* XXX compute */
1194 break;
1195 }
1196 break;
1197 case 1:
1198 switch (queue_id) {
1199 case 0:
1200 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1201 break;
1202 case 1:
1203 /* XXX compute */
1204 break;
1205 case 2:
1206 /* XXX compute */
1207 break;
1208 }
1209 break;
1210 }
1211
1212 return 0;
1213}
1214
1215static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1216 struct amdgpu_irq_src *source,
1217 struct amdgpu_iv_entry *entry)
1218{
1219 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1220 schedule_work(&adev->reset_work);
1221 return 0;
1222}
1223
1224static int cik_sdma_set_clockgating_state(void *handle,
1225 enum amd_clockgating_state state)
1226{
1227 bool gate = false;
1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229
1230 if (state == AMD_CG_STATE_GATE)
1231 gate = true;
1232
1233 cik_enable_sdma_mgcg(adev, gate);
1234 cik_enable_sdma_mgls(adev, gate);
1235
1236 return 0;
1237}
1238
1239static int cik_sdma_set_powergating_state(void *handle,
1240 enum amd_powergating_state state)
1241{
1242 return 0;
1243}
1244
1245static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1246 .name = "cik_sdma",
1247 .early_init = cik_sdma_early_init,
1248 .late_init = NULL,
1249 .sw_init = cik_sdma_sw_init,
1250 .sw_fini = cik_sdma_sw_fini,
1251 .hw_init = cik_sdma_hw_init,
1252 .hw_fini = cik_sdma_hw_fini,
1253 .suspend = cik_sdma_suspend,
1254 .resume = cik_sdma_resume,
1255 .is_idle = cik_sdma_is_idle,
1256 .wait_for_idle = cik_sdma_wait_for_idle,
1257 .soft_reset = cik_sdma_soft_reset,
1258 .set_clockgating_state = cik_sdma_set_clockgating_state,
1259 .set_powergating_state = cik_sdma_set_powergating_state,
1260};
1261
1262static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1263 .type = AMDGPU_RING_TYPE_SDMA,
1264 .align_mask = 0xf,
1265 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1266 .support_64bit_ptrs = false,
1267 .get_rptr = cik_sdma_ring_get_rptr,
1268 .get_wptr = cik_sdma_ring_get_wptr,
1269 .set_wptr = cik_sdma_ring_set_wptr,
1270 .emit_frame_size =
1271 6 + /* cik_sdma_ring_emit_hdp_flush */
1272 3 + /* hdp invalidate */
1273 6 + /* cik_sdma_ring_emit_pipeline_sync */
1274 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1275 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1276 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1277 .emit_ib = cik_sdma_ring_emit_ib,
1278 .emit_fence = cik_sdma_ring_emit_fence,
1279 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1280 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1281 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1282 .test_ring = cik_sdma_ring_test_ring,
1283 .test_ib = cik_sdma_ring_test_ib,
1284 .insert_nop = cik_sdma_ring_insert_nop,
1285 .pad_ib = cik_sdma_ring_pad_ib,
1286 .emit_wreg = cik_sdma_ring_emit_wreg,
1287};
1288
1289static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1290{
1291 int i;
1292
1293 for (i = 0; i < adev->sdma.num_instances; i++)
1294 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1295}
1296
1297static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1298 .set = cik_sdma_set_trap_irq_state,
1299 .process = cik_sdma_process_trap_irq,
1300};
1301
1302static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1303 .process = cik_sdma_process_illegal_inst_irq,
1304};
1305
1306static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1307{
1308 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1309 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1310 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1311}
1312
1313/**
1314 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1315 *
1316 * @ring: amdgpu_ring structure holding ring information
1317 * @src_offset: src GPU address
1318 * @dst_offset: dst GPU address
1319 * @byte_count: number of bytes to xfer
1320 *
1321 * Copy GPU buffers using the DMA engine (CIK).
1322 * Used by the amdgpu ttm implementation to move pages if
1323 * registered as the asic copy callback.
1324 */
1325static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1326 uint64_t src_offset,
1327 uint64_t dst_offset,
1328 uint32_t byte_count)
1329{
1330 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1331 ib->ptr[ib->length_dw++] = byte_count;
1332 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1333 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1334 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1335 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1336 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1337}
1338
1339/**
1340 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1341 *
1342 * @ring: amdgpu_ring structure holding ring information
1343 * @src_data: value to write to buffer
1344 * @dst_offset: dst GPU address
1345 * @byte_count: number of bytes to xfer
1346 *
1347 * Fill GPU buffers using the DMA engine (CIK).
1348 */
1349static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1350 uint32_t src_data,
1351 uint64_t dst_offset,
1352 uint32_t byte_count)
1353{
1354 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1355 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1356 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1357 ib->ptr[ib->length_dw++] = src_data;
1358 ib->ptr[ib->length_dw++] = byte_count;
1359}
1360
1361static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1362 .copy_max_bytes = 0x1fffff,
1363 .copy_num_dw = 7,
1364 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1365
1366 .fill_max_bytes = 0x1fffff,
1367 .fill_num_dw = 5,
1368 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1369};
1370
1371static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1372{
1373 if (adev->mman.buffer_funcs == NULL) {
1374 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1375 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1376 }
1377}
1378
1379static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1380 .copy_pte_num_dw = 7,
1381 .copy_pte = cik_sdma_vm_copy_pte,
1382
1383 .write_pte = cik_sdma_vm_write_pte,
1384 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1385};
1386
1387static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1388{
1389 unsigned i;
1390
1391 if (adev->vm_manager.vm_pte_funcs == NULL) {
1392 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1393 for (i = 0; i < adev->sdma.num_instances; i++)
1394 adev->vm_manager.vm_pte_rings[i] =
1395 &adev->sdma.instance[i].ring;
1396
1397 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1398 }
1399}
1400
1401const struct amdgpu_ip_block_version cik_sdma_ip_block =
1402{
1403 .type = AMD_IP_BLOCK_TYPE_SDMA,
1404 .major = 2,
1405 .minor = 0,
1406 .rev = 0,
1407 .funcs = &cik_sdma_ip_funcs,
1408};