1/*
  2 * Copyright 2014 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef __AMDGPU_IRQ_H__
 25#define __AMDGPU_IRQ_H__
 26
 27#include <linux/irqdomain.h>
 28#include "amdgpu_ih.h"
 29
 30#define AMDGPU_MAX_IRQ_SRC_ID	0x100
 31#define AMDGPU_MAX_IRQ_CLIENT_ID	0x100
 32
 33struct amdgpu_device;
 34struct amdgpu_iv_entry;
 35
 36enum amdgpu_interrupt_state {
 37	AMDGPU_IRQ_STATE_DISABLE,
 38	AMDGPU_IRQ_STATE_ENABLE,
 39};
 40
 41struct amdgpu_irq_src {
 42	unsigned				num_types;
 43	atomic_t				*enabled_types;
 44	const struct amdgpu_irq_src_funcs	*funcs;
 45	void *data;
 46};
 47
 48struct amdgpu_irq_client {
 49	struct amdgpu_irq_src **sources;
 50};
 51
 52/* provided by interrupt generating IP blocks */
 53struct amdgpu_irq_src_funcs {
 54	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
 55		   unsigned type, enum amdgpu_interrupt_state state);
 56
 57	int (*process)(struct amdgpu_device *adev,
 58		       struct amdgpu_irq_src *source,
 59		       struct amdgpu_iv_entry *entry);
 60};
 61
 62struct amdgpu_irq {
 63	bool				installed;
 64	spinlock_t			lock;
 65	/* interrupt sources */
 66	struct amdgpu_irq_client	client[AMDGPU_IH_CLIENTID_MAX];
 67
 68	/* status, etc. */
 69	bool				msi_enabled; /* msi enabled */
 70
 71	/* interrupt ring */
 72	struct amdgpu_ih_ring		ih;
 73	const struct amdgpu_ih_funcs	*ih_funcs;
 74
 75	/* gen irq stuff */
 76	struct irq_domain		*domain; /* GPU irq controller domain */
 77	unsigned			virq[AMDGPU_MAX_IRQ_SRC_ID];
 78	uint32_t                        srbm_soft_reset;
 79};
 80
 81void amdgpu_irq_disable_all(struct amdgpu_device *adev);
 82irqreturn_t amdgpu_irq_handler(int irq, void *arg);
 83
 84int amdgpu_irq_init(struct amdgpu_device *adev);
 85void amdgpu_irq_fini(struct amdgpu_device *adev);
 86int amdgpu_irq_add_id(struct amdgpu_device *adev,
 87		      unsigned client_id, unsigned src_id,
 88		      struct amdgpu_irq_src *source);
 89void amdgpu_irq_dispatch(struct amdgpu_device *adev,
 90			 struct amdgpu_iv_entry *entry);
 91int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
 92		      unsigned type);
 93int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
 94		   unsigned type);
 95int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
 96		   unsigned type);
 97bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
 98			unsigned type);
 99void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
100
101int amdgpu_irq_add_domain(struct amdgpu_device *adev);
102void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
103unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
104
105#endif