1 /*
   2 *	x86 SMP booting functions
   3 *
   4 *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
   5 *	(c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
   6 *	Copyright 2001 Andi Kleen, SuSE Labs.
   7 *
   8 *	Much of the core SMP work is based on previous work by Thomas Radke, to
   9 *	whom a great many thanks are extended.
  10 *
  11 *	Thanks to Intel for making available several different Pentium,
  12 *	Pentium Pro and Pentium-II/Xeon MP machines.
  13 *	Original development of Linux SMP code supported by Caldera.
  14 *
  15 *	This code is released under the GNU General Public License version 2 or
  16 *	later.
  17 *
  18 *	Fixes
  19 *		Felix Koop	:	NR_CPUS used properly
  20 *		Jose Renau	:	Handle single CPU case.
  21 *		Alan Cox	:	By repeated request 8) - Total BogoMIPS report.
  22 *		Greg Wright	:	Fix for kernel stacks panic.
  23 *		Erich Boleyn	:	MP v1.4 and additional changes.
  24 *	Matthias Sattler	:	Changes for 2.1 kernel map.
  25 *	Michel Lespinasse	:	Changes for 2.1 kernel map.
  26 *	Michael Chastain	:	Change trampoline.S to gnu as.
  27 *		Alan Cox	:	Dumb bug: 'B' step PPro's are fine
  28 *		Ingo Molnar	:	Added APIC timers, based on code
  29 *					from Jose Renau
  30 *		Ingo Molnar	:	various cleanups and rewrites
  31 *		Tigran Aivazian	:	fixed "0.00 in /proc/uptime on SMP" bug.
  32 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs
  33 *	Andi Kleen		:	Changed for SMP boot into long mode.
  34 *		Martin J. Bligh	: 	Added support for multi-quad systems
  35 *		Dave Jones	:	Report invalid combinations of Athlon CPUs.
  36 *		Rusty Russell	:	Hacked into shape for new "hotplug" boot process.
  37 *      Andi Kleen              :       Converted to new state machine.
  38 *	Ashok Raj		: 	CPU hotplug support
  39 *	Glauber Costa		:	i386 and x86_64 integration
  40 */
  41
  42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  43
  44#include <linux/init.h>
  45#include <linux/smp.h>
  46#include <linux/export.h>
  47#include <linux/sched.h>
  48#include <linux/sched/topology.h>
  49#include <linux/sched/hotplug.h>
  50#include <linux/sched/task_stack.h>
  51#include <linux/percpu.h>
  52#include <linux/bootmem.h>
  53#include <linux/err.h>
  54#include <linux/nmi.h>
  55#include <linux/tboot.h>
  56#include <linux/stackprotector.h>
  57#include <linux/gfp.h>
  58#include <linux/cpuidle.h>
  59
  60#include <asm/acpi.h>
  61#include <asm/desc.h>
  62#include <asm/nmi.h>
  63#include <asm/irq.h>
 
  64#include <asm/realmode.h>
  65#include <asm/cpu.h>
  66#include <asm/numa.h>
  67#include <asm/pgtable.h>
  68#include <asm/tlbflush.h>
  69#include <asm/mtrr.h>
  70#include <asm/mwait.h>
  71#include <asm/apic.h>
  72#include <asm/io_apic.h>
  73#include <asm/fpu/internal.h>
 
  74#include <asm/setup.h>
  75#include <asm/uv/uv.h>
  76#include <linux/mc146818rtc.h>
 
  77#include <asm/i8259.h>
 
  78#include <asm/misc.h>
  79#include <asm/qspinlock.h>
  80#include <asm/intel-family.h>
  81#include <asm/cpu_device_id.h>
  82#include <asm/spec-ctrl.h>
  83
  84/* Number of siblings per CPU package */
  85int smp_num_siblings = 1;
  86EXPORT_SYMBOL(smp_num_siblings);
  87
  88/* Last level cache ID of each logical CPU */
  89DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
  90
  91/* representing HT siblings of each logical CPU */
  92DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
  93EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  94
  95/* representing HT and core siblings of each logical CPU */
  96DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
  97EXPORT_PER_CPU_SYMBOL(cpu_core_map);
  98
  99DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
 100
 101/* Per CPU bogomips and other parameters */
 102DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 103EXPORT_PER_CPU_SYMBOL(cpu_info);
 104
 105/* Logical package management. We might want to allocate that dynamically */
 106unsigned int __max_logical_packages __read_mostly;
 107EXPORT_SYMBOL(__max_logical_packages);
 108static unsigned int logical_packages __read_mostly;
 109
 110/* Maximum number of SMT threads on any online core */
 111int __read_mostly __max_smt_threads = 1;
 112
 113/* Flag to indicate if a complete sched domain rebuild is required */
 114bool x86_topology_update;
 115
 116int arch_update_cpu_topology(void)
 117{
 118	int retval = x86_topology_update;
 119
 120	x86_topology_update = false;
 121	return retval;
 122}
 123
 124static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
 125{
 126	unsigned long flags;
 127
 128	spin_lock_irqsave(&rtc_lock, flags);
 129	CMOS_WRITE(0xa, 0xf);
 130	spin_unlock_irqrestore(&rtc_lock, flags);
 131	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
 132							start_eip >> 4;
 133	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
 134							start_eip & 0xf;
 135}
 136
 137static inline void smpboot_restore_warm_reset_vector(void)
 138{
 139	unsigned long flags;
 140
 141	/*
 142	 * Paranoid:  Set warm reset code and vector here back
 143	 * to default values.
 144	 */
 145	spin_lock_irqsave(&rtc_lock, flags);
 146	CMOS_WRITE(0, 0xf);
 147	spin_unlock_irqrestore(&rtc_lock, flags);
 148
 149	*((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
 150}
 151
 152/*
 153 * Report back to the Boot Processor during boot time or to the caller processor
 154 * during CPU online.
 155 */
 156static void smp_callin(void)
 157{
 158	int cpuid, phys_id;
 
 159
 160	/*
 161	 * If waken up by an INIT in an 82489DX configuration
 162	 * cpu_callout_mask guarantees we don't get here before
 163	 * an INIT_deassert IPI reaches our local APIC, so it is
 164	 * now safe to touch our local APIC.
 
 
 165	 */
 166	cpuid = smp_processor_id();
 
 
 
 167
 168	/*
 169	 * (This works even if the APIC is not enabled.)
 170	 */
 171	phys_id = read_apic_id();
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 172
 173	/*
 174	 * the boot CPU has finished the init stage and is spinning
 175	 * on callin_map until we finish. We are free to set up this
 176	 * CPU, first the APIC. (this is probably redundant on most
 177	 * boards)
 178	 */
 179	apic_ap_setup();
 
 
 
 
 
 180
 181	/*
 182	 * Save our processor parameters. Note: this information
 183	 * is needed for clock calibration.
 184	 */
 185	smp_store_cpu_info(cpuid);
 186
 187	/*
 188	 * The topology information must be up to date before
 189	 * calibrate_delay() and notify_cpu_starting().
 190	 */
 191	set_cpu_sibling_map(raw_smp_processor_id());
 192
 193	/*
 194	 * Get our bogomips.
 195	 * Update loops_per_jiffy in cpu_data. Previous call to
 196	 * smp_store_cpu_info() stored a value that is close but not as
 197	 * accurate as the value just calculated.
 198	 */
 199	calibrate_delay();
 200	cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
 201	pr_debug("Stack at about %p\n", &cpuid);
 202
 
 
 
 
 
 203	wmb();
 204
 205	notify_cpu_starting(cpuid);
 206
 207	/*
 208	 * Allow the master to continue.
 209	 */
 210	cpumask_set_cpu(cpuid, cpu_callin_mask);
 211}
 212
 213static int cpu0_logical_apicid;
 214static int enable_start_cpu0;
 215/*
 216 * Activate a secondary processor.
 217 */
 218static void notrace start_secondary(void *unused)
 219{
 220	/*
 221	 * Don't put *anything* except direct CPU state initialization
 222	 * before cpu_init(), SMP booting is too fragile that we want to
 223	 * limit the things done here to the most necessary things.
 224	 */
 225	if (boot_cpu_has(X86_FEATURE_PCID))
 226		__write_cr4(__read_cr4() | X86_CR4_PCIDE);
 227
 228#ifdef CONFIG_X86_32
 229	/* switch away from the initial page table */
 230	load_cr3(swapper_pg_dir);
 231	__flush_tlb_all();
 232#endif
 233	load_current_idt();
 234	cpu_init();
 235	x86_cpuinit.early_percpu_clock_init();
 236	preempt_disable();
 237	smp_callin();
 238
 239	enable_start_cpu0 = 0;
 240
 
 
 
 
 
 
 241	/* otherwise gcc will move up smp_processor_id before the cpu_init */
 242	barrier();
 243	/*
 244	 * Check TSC synchronization with the boot CPU:
 245	 */
 246	check_tsc_sync_target();
 247
 248	speculative_store_bypass_ht_init();
 249
 250	/*
 251	 * Lock vector_lock, set CPU online and bring the vector
 252	 * allocator online. Online must be set with vector_lock held
 253	 * to prevent a concurrent irq setup/teardown from seeing a
 254	 * half valid vector space.
 255	 */
 256	lock_vector_lock();
 257	set_cpu_online(smp_processor_id(), true);
 258	lapic_online();
 259	unlock_vector_lock();
 260	cpu_set_state_online(smp_processor_id());
 261	x86_platform.nmi_init();
 262
 263	/* enable local interrupts */
 264	local_irq_enable();
 265
 266	/* to prevent fake stack check failure in clock setup */
 267	boot_init_stack_canary();
 268
 269	x86_cpuinit.setup_percpu_clockev();
 270
 271	wmb();
 272	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
 273}
 274
 275/**
 276 * topology_phys_to_logical_pkg - Map a physical package id to a logical
 277 *
 278 * Returns logical package id or -1 if not found
 279 */
 280int topology_phys_to_logical_pkg(unsigned int phys_pkg)
 281{
 282	int cpu;
 283
 284	for_each_possible_cpu(cpu) {
 285		struct cpuinfo_x86 *c = &cpu_data(cpu);
 286
 287		if (c->initialized && c->phys_proc_id == phys_pkg)
 288			return c->logical_proc_id;
 289	}
 290	return -1;
 291}
 292EXPORT_SYMBOL(topology_phys_to_logical_pkg);
 293
 294/**
 295 * topology_update_package_map - Update the physical to logical package map
 296 * @pkg:	The physical package id as retrieved via CPUID
 297 * @cpu:	The cpu for which this is updated
 298 */
 299int topology_update_package_map(unsigned int pkg, unsigned int cpu)
 300{
 301	int new;
 302
 303	/* Already available somewhere? */
 304	new = topology_phys_to_logical_pkg(pkg);
 305	if (new >= 0)
 306		goto found;
 307
 308	new = logical_packages++;
 309	if (new != pkg) {
 310		pr_info("CPU %u Converting physical %u to logical package %u\n",
 311			cpu, pkg, new);
 312	}
 313found:
 314	cpu_data(cpu).logical_proc_id = new;
 315	return 0;
 316}
 317
 318void __init smp_store_boot_cpu_info(void)
 319{
 320	int id = 0; /* CPU 0 */
 321	struct cpuinfo_x86 *c = &cpu_data(id);
 322
 323	*c = boot_cpu_data;
 324	c->cpu_index = id;
 325	topology_update_package_map(c->phys_proc_id, id);
 326	c->initialized = true;
 327}
 328
 329/*
 330 * The bootstrap kernel entry code has set these up. Save them for
 331 * a given CPU
 332 */
 333void smp_store_cpu_info(int id)
 334{
 335	struct cpuinfo_x86 *c = &cpu_data(id);
 336
 337	/* Copy boot_cpu_data only on the first bringup */
 338	if (!c->initialized)
 339		*c = boot_cpu_data;
 340	c->cpu_index = id;
 341	/*
 342	 * During boot time, CPU0 has this setup already. Save the info when
 343	 * bringing up AP or offlined CPU0.
 344	 */
 345	identify_secondary_cpu(c);
 346	c->initialized = true;
 347}
 348
 349static bool
 350topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 351{
 352	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 353
 354	return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
 355}
 356
 357static bool
 358topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
 359{
 360	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 361
 362	return !WARN_ONCE(!topology_same_node(c, o),
 363		"sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
 364		"[node: %d != %d]. Ignoring dependency.\n",
 365		cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
 366}
 367
 368#define link_mask(mfunc, c1, c2)					\
 369do {									\
 370	cpumask_set_cpu((c1), mfunc(c2));				\
 371	cpumask_set_cpu((c2), mfunc(c1));				\
 372} while (0)
 373
 374static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 375{
 376	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
 377		int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 378
 379		if (c->phys_proc_id == o->phys_proc_id &&
 380		    per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
 381			if (c->cpu_core_id == o->cpu_core_id)
 382				return topology_sane(c, o, "smt");
 383
 384			if ((c->cu_id != 0xff) &&
 385			    (o->cu_id != 0xff) &&
 386			    (c->cu_id == o->cu_id))
 387				return topology_sane(c, o, "smt");
 388		}
 389
 390	} else if (c->phys_proc_id == o->phys_proc_id &&
 391		   c->cpu_core_id == o->cpu_core_id) {
 392		return topology_sane(c, o, "smt");
 393	}
 394
 395	return false;
 396}
 397
 398/*
 399 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
 400 *
 401 * These are Intel CPUs that enumerate an LLC that is shared by
 402 * multiple NUMA nodes. The LLC on these systems is shared for
 403 * off-package data access but private to the NUMA node (half
 404 * of the package) for on-package access.
 405 *
 406 * CPUID (the source of the information about the LLC) can only
 407 * enumerate the cache as being shared *or* unshared, but not
 408 * this particular configuration. The CPU in this case enumerates
 409 * the cache to be shared across the entire package (spanning both
 410 * NUMA nodes).
 411 */
 412
 413static const struct x86_cpu_id snc_cpu[] = {
 414	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
 415	{}
 416};
 417
 418static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 419{
 420	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 421
 422	/* Do not match if we do not have a valid APICID for cpu: */
 423	if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
 424		return false;
 425
 426	/* Do not match if LLC id does not match: */
 427	if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
 428		return false;
 429
 430	/*
 431	 * Allow the SNC topology without warning. Return of false
 432	 * means 'c' does not share the LLC of 'o'. This will be
 433	 * reflected to userspace.
 434	 */
 435	if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
 436		return false;
 437
 438	return topology_sane(c, o, "llc");
 439}
 440
 441/*
 442 * Unlike the other levels, we do not enforce keeping a
 443 * multicore group inside a NUMA node.  If this happens, we will
 444 * discard the MC level of the topology later.
 445 */
 446static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 447{
 448	if (c->phys_proc_id == o->phys_proc_id)
 449		return true;
 450	return false;
 451}
 452
 453#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
 454static inline int x86_sched_itmt_flags(void)
 455{
 456	return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
 457}
 
 458
 459#ifdef CONFIG_SCHED_MC
 460static int x86_core_flags(void)
 461{
 462	return cpu_core_flags() | x86_sched_itmt_flags();
 463}
 464#endif
 465#ifdef CONFIG_SCHED_SMT
 466static int x86_smt_flags(void)
 467{
 468	return cpu_smt_flags() | x86_sched_itmt_flags();
 469}
 470#endif
 471#endif
 472
 473static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
 474#ifdef CONFIG_SCHED_SMT
 475	{ cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
 476#endif
 477#ifdef CONFIG_SCHED_MC
 478	{ cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
 479#endif
 480	{ NULL, },
 481};
 482
 483static struct sched_domain_topology_level x86_topology[] = {
 484#ifdef CONFIG_SCHED_SMT
 485	{ cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
 486#endif
 487#ifdef CONFIG_SCHED_MC
 488	{ cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
 489#endif
 490	{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
 491	{ NULL, },
 492};
 493
 494/*
 495 * Set if a package/die has multiple NUMA nodes inside.
 496 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
 497 * Sub-NUMA Clustering have this.
 498 */
 499static bool x86_has_numa_in_package;
 500
 501void set_cpu_sibling_map(int cpu)
 502{
 503	bool has_smt = smp_num_siblings > 1;
 504	bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
 505	struct cpuinfo_x86 *c = &cpu_data(cpu);
 506	struct cpuinfo_x86 *o;
 507	int i, threads;
 508
 509	cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
 510
 511	if (!has_mp) {
 512		cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
 513		cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
 514		cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
 515		c->booted_cores = 1;
 516		return;
 517	}
 518
 519	for_each_cpu(i, cpu_sibling_setup_mask) {
 520		o = &cpu_data(i);
 521
 522		if ((i == cpu) || (has_smt && match_smt(c, o)))
 523			link_mask(topology_sibling_cpumask, cpu, i);
 524
 525		if ((i == cpu) || (has_mp && match_llc(c, o)))
 526			link_mask(cpu_llc_shared_mask, cpu, i);
 527
 528	}
 529
 530	/*
 531	 * This needs a separate iteration over the cpus because we rely on all
 532	 * topology_sibling_cpumask links to be set-up.
 533	 */
 534	for_each_cpu(i, cpu_sibling_setup_mask) {
 535		o = &cpu_data(i);
 536
 537		if ((i == cpu) || (has_mp && match_die(c, o))) {
 538			link_mask(topology_core_cpumask, cpu, i);
 539
 540			/*
 541			 *  Does this new cpu bringup a new core?
 542			 */
 543			if (cpumask_weight(
 544			    topology_sibling_cpumask(cpu)) == 1) {
 545				/*
 546				 * for each core in package, increment
 547				 * the booted_cores for this new cpu
 548				 */
 549				if (cpumask_first(
 550				    topology_sibling_cpumask(i)) == i)
 551					c->booted_cores++;
 552				/*
 553				 * increment the core count for all
 554				 * the other cpus in this package
 555				 */
 556				if (i != cpu)
 557					cpu_data(i).booted_cores++;
 558			} else if (i != cpu && !c->booted_cores)
 559				c->booted_cores = cpu_data(i).booted_cores;
 560		}
 561		if (match_die(c, o) && !topology_same_node(c, o))
 562			x86_has_numa_in_package = true;
 563	}
 564
 565	threads = cpumask_weight(topology_sibling_cpumask(cpu));
 566	if (threads > __max_smt_threads)
 567		__max_smt_threads = threads;
 568}
 569
 570/* maps the cpu to the sched domain representing multi-core */
 571const struct cpumask *cpu_coregroup_mask(int cpu)
 572{
 573	return cpu_llc_shared_mask(cpu);
 574}
 575
 576static void impress_friends(void)
 577{
 578	int cpu;
 579	unsigned long bogosum = 0;
 580	/*
 581	 * Allow the user to impress friends.
 582	 */
 583	pr_debug("Before bogomips\n");
 584	for_each_possible_cpu(cpu)
 585		if (cpumask_test_cpu(cpu, cpu_callout_mask))
 586			bogosum += cpu_data(cpu).loops_per_jiffy;
 587	pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
 588		num_online_cpus(),
 589		bogosum/(500000/HZ),
 590		(bogosum/(5000/HZ))%100);
 591
 592	pr_debug("Before bogocount - setting activated=1\n");
 593}
 594
 595void __inquire_remote_apic(int apicid)
 596{
 597	unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
 598	const char * const names[] = { "ID", "VERSION", "SPIV" };
 599	int timeout;
 600	u32 status;
 601
 602	pr_info("Inquiring remote APIC 0x%x...\n", apicid);
 603
 604	for (i = 0; i < ARRAY_SIZE(regs); i++) {
 605		pr_info("... APIC 0x%x %s: ", apicid, names[i]);
 606
 607		/*
 608		 * Wait for idle.
 609		 */
 610		status = safe_apic_wait_icr_idle();
 611		if (status)
 612			pr_cont("a previous APIC delivery may have failed\n");
 613
 614		apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
 615
 616		timeout = 0;
 617		do {
 618			udelay(100);
 619			status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
 620		} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
 621
 622		switch (status) {
 623		case APIC_ICR_RR_VALID:
 624			status = apic_read(APIC_RRR);
 625			pr_cont("%08x\n", status);
 626			break;
 627		default:
 628			pr_cont("failed\n");
 629		}
 630	}
 631}
 632
 633/*
 634 * The Multiprocessor Specification 1.4 (1997) example code suggests
 635 * that there should be a 10ms delay between the BSP asserting INIT
 636 * and de-asserting INIT, when starting a remote processor.
 637 * But that slows boot and resume on modern processors, which include
 638 * many cores and don't require that delay.
 639 *
 640 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
 641 * Modern processor families are quirked to remove the delay entirely.
 642 */
 643#define UDELAY_10MS_DEFAULT 10000
 644
 645static unsigned int init_udelay = UINT_MAX;
 646
 647static int __init cpu_init_udelay(char *str)
 648{
 649	get_option(&str, &init_udelay);
 650
 651	return 0;
 652}
 653early_param("cpu_init_udelay", cpu_init_udelay);
 654
 655static void __init smp_quirk_init_udelay(void)
 656{
 657	/* if cmdline changed it from default, leave it alone */
 658	if (init_udelay != UINT_MAX)
 659		return;
 660
 661	/* if modern processor, use no delay */
 662	if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
 663	    ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
 664		init_udelay = 0;
 665		return;
 666	}
 667	/* else, use legacy delay */
 668	init_udelay = UDELAY_10MS_DEFAULT;
 669}
 670
 671/*
 672 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
 673 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
 674 * won't ... remember to clear down the APIC, etc later.
 675 */
 676int
 677wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
 678{
 679	unsigned long send_status, accept_status = 0;
 680	int maxlvt;
 681
 682	/* Target chip */
 683	/* Boot on the stack */
 684	/* Kick the second */
 685	apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
 686
 687	pr_debug("Waiting for send to finish...\n");
 688	send_status = safe_apic_wait_icr_idle();
 689
 690	/*
 691	 * Give the other CPU some time to accept the IPI.
 692	 */
 693	udelay(200);
 694	if (APIC_INTEGRATED(boot_cpu_apic_version)) {
 695		maxlvt = lapic_get_maxlvt();
 696		if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
 697			apic_write(APIC_ESR, 0);
 698		accept_status = (apic_read(APIC_ESR) & 0xEF);
 699	}
 700	pr_debug("NMI sent\n");
 701
 702	if (send_status)
 703		pr_err("APIC never delivered???\n");
 704	if (accept_status)
 705		pr_err("APIC delivery error (%lx)\n", accept_status);
 706
 707	return (send_status | accept_status);
 708}
 709
 710static int
 711wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
 712{
 713	unsigned long send_status = 0, accept_status = 0;
 714	int maxlvt, num_starts, j;
 715
 716	maxlvt = lapic_get_maxlvt();
 717
 718	/*
 719	 * Be paranoid about clearing APIC errors.
 720	 */
 721	if (APIC_INTEGRATED(boot_cpu_apic_version)) {
 722		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
 723			apic_write(APIC_ESR, 0);
 724		apic_read(APIC_ESR);
 725	}
 726
 727	pr_debug("Asserting INIT\n");
 728
 729	/*
 730	 * Turn INIT on target chip
 731	 */
 732	/*
 733	 * Send IPI
 734	 */
 735	apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
 736		       phys_apicid);
 737
 738	pr_debug("Waiting for send to finish...\n");
 739	send_status = safe_apic_wait_icr_idle();
 740
 741	udelay(init_udelay);
 742
 743	pr_debug("Deasserting INIT\n");
 744
 745	/* Target chip */
 746	/* Send IPI */
 747	apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
 748
 749	pr_debug("Waiting for send to finish...\n");
 750	send_status = safe_apic_wait_icr_idle();
 751
 752	mb();
 
 753
 754	/*
 755	 * Should we send STARTUP IPIs ?
 756	 *
 757	 * Determine this based on the APIC version.
 758	 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
 759	 */
 760	if (APIC_INTEGRATED(boot_cpu_apic_version))
 761		num_starts = 2;
 762	else
 763		num_starts = 0;
 764
 765	/*
 
 
 
 
 
 
 
 766	 * Run STARTUP IPI loop.
 767	 */
 768	pr_debug("#startup loops: %d\n", num_starts);
 769
 770	for (j = 1; j <= num_starts; j++) {
 771		pr_debug("Sending STARTUP #%d\n", j);
 772		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
 773			apic_write(APIC_ESR, 0);
 774		apic_read(APIC_ESR);
 775		pr_debug("After apic_write\n");
 776
 777		/*
 778		 * STARTUP IPI
 779		 */
 780
 781		/* Target chip */
 782		/* Boot on the stack */
 783		/* Kick the second */
 784		apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
 785			       phys_apicid);
 786
 787		/*
 788		 * Give the other CPU some time to accept the IPI.
 789		 */
 790		if (init_udelay == 0)
 791			udelay(10);
 792		else
 793			udelay(300);
 794
 795		pr_debug("Startup point 1\n");
 796
 797		pr_debug("Waiting for send to finish...\n");
 798		send_status = safe_apic_wait_icr_idle();
 799
 800		/*
 801		 * Give the other CPU some time to accept the IPI.
 802		 */
 803		if (init_udelay == 0)
 804			udelay(10);
 805		else
 806			udelay(200);
 807
 808		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
 809			apic_write(APIC_ESR, 0);
 810		accept_status = (apic_read(APIC_ESR) & 0xEF);
 811		if (send_status || accept_status)
 812			break;
 813	}
 814	pr_debug("After Startup\n");
 815
 816	if (send_status)
 817		pr_err("APIC never delivered???\n");
 818	if (accept_status)
 819		pr_err("APIC delivery error (%lx)\n", accept_status);
 820
 821	return (send_status | accept_status);
 822}
 823
 
 
 
 
 
 
 
 
 824/* reduce the number of lines printed when booting a large cpu count system */
 825static void announce_cpu(int cpu, int apicid)
 826{
 827	static int current_node = -1;
 828	int node = early_cpu_to_node(cpu);
 829	static int width, node_width;
 830
 831	if (!width)
 832		width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
 833
 834	if (!node_width)
 835		node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
 836
 837	if (cpu == 1)
 838		printk(KERN_INFO "x86: Booting SMP configuration:\n");
 839
 840	if (system_state < SYSTEM_RUNNING) {
 841		if (node != current_node) {
 842			if (current_node > (-1))
 843				pr_cont("\n");
 844			current_node = node;
 845
 846			printk(KERN_INFO ".... node %*s#%d, CPUs:  ",
 847			       node_width - num_digits(node), " ", node);
 848		}
 849
 850		/* Add padding for the BSP */
 851		if (cpu == 1)
 852			pr_cont("%*s", width + 1, " ");
 853
 854		pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
 855
 856	} else
 857		pr_info("Booting Node %d Processor %d APIC 0x%x\n",
 858			node, cpu, apicid);
 859}
 860
 861static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
 862{
 863	int cpu;
 864
 865	cpu = smp_processor_id();
 866	if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
 867		return NMI_HANDLED;
 868
 869	return NMI_DONE;
 870}
 871
 872/*
 873 * Wake up AP by INIT, INIT, STARTUP sequence.
 874 *
 875 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
 876 * boot-strap code which is not a desired behavior for waking up BSP. To
 877 * void the boot-strap code, wake up CPU0 by NMI instead.
 878 *
 879 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
 880 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
 881 * We'll change this code in the future to wake up hard offlined CPU0 if
 882 * real platform and request are available.
 883 */
 884static int
 885wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
 886	       int *cpu0_nmi_registered)
 887{
 888	int id;
 889	int boot_error;
 890
 891	preempt_disable();
 892
 893	/*
 894	 * Wake up AP by INIT, INIT, STARTUP sequence.
 895	 */
 896	if (cpu) {
 897		boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
 898		goto out;
 899	}
 900
 901	/*
 902	 * Wake up BSP by nmi.
 903	 *
 904	 * Register a NMI handler to help wake up CPU0.
 905	 */
 906	boot_error = register_nmi_handler(NMI_LOCAL,
 907					  wakeup_cpu0_nmi, 0, "wake_cpu0");
 908
 909	if (!boot_error) {
 910		enable_start_cpu0 = 1;
 911		*cpu0_nmi_registered = 1;
 912		if (apic->dest_logical == APIC_DEST_LOGICAL)
 913			id = cpu0_logical_apicid;
 914		else
 915			id = apicid;
 916		boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
 917	}
 918
 919out:
 920	preempt_enable();
 921
 922	return boot_error;
 923}
 924
 925void common_cpu_up(unsigned int cpu, struct task_struct *idle)
 926{
 927	/* Just in case we booted with a single CPU. */
 928	alternatives_enable_smp();
 929
 930	per_cpu(current_task, cpu) = idle;
 931
 932#ifdef CONFIG_X86_32
 933	/* Stack for startup_32 can be just as for start_secondary onwards */
 934	irq_ctx_init(cpu);
 935	per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
 936#else
 937	initial_gs = per_cpu_offset(cpu);
 938#endif
 939}
 940
 941/*
 942 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
 943 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
 944 * Returns zero if CPU booted OK, else error code from
 945 * ->wakeup_secondary_cpu.
 946 */
 947static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
 948		       int *cpu0_nmi_registered)
 949{
 950	volatile u32 *trampoline_status =
 951		(volatile u32 *) __va(real_mode_header->trampoline_status);
 952	/* start_ip had better be page-aligned! */
 953	unsigned long start_ip = real_mode_header->trampoline_start;
 954
 955	unsigned long boot_error = 0;
 956	unsigned long timeout;
 
 957
 958	idle->thread.sp = (unsigned long)task_pt_regs(idle);
 959	early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
 960	initial_code = (unsigned long)start_secondary;
 961	initial_stack  = idle->thread.sp;
 
 
 962
 963	/* Enable the espfix hack for this CPU */
 964	init_espfix_ap(cpu);
 
 
 
 
 
 
 
 
 
 
 
 965
 966	/* So we see what's up */
 967	announce_cpu(cpu, apicid);
 968
 969	/*
 970	 * This grunge runs the startup process for
 971	 * the targeted processor.
 972	 */
 973
 974	if (x86_platform.legacy.warm_reset) {
 
 
 975
 976		pr_debug("Setting warm reset code and vector.\n");
 977
 978		smpboot_setup_warm_reset_vector(start_ip);
 979		/*
 980		 * Be paranoid about clearing APIC errors.
 981		*/
 982		if (APIC_INTEGRATED(boot_cpu_apic_version)) {
 983			apic_write(APIC_ESR, 0);
 984			apic_read(APIC_ESR);
 985		}
 986	}
 987
 988	/*
 989	 * AP might wait on cpu_callout_mask in cpu_init() with
 990	 * cpu_initialized_mask set if previous attempt to online
 991	 * it timed-out. Clear cpu_initialized_mask so that after
 992	 * INIT/SIPI it could start with a clean state.
 993	 */
 994	cpumask_clear_cpu(cpu, cpu_initialized_mask);
 995	smp_mb();
 996
 997	/*
 998	 * Wake up a CPU in difference cases:
 999	 * - Use the method in the APIC driver if it's defined
1000	 * Otherwise,
1001	 * - Use an INIT boot APIC message for APs or NMI for BSP.
1002	 */
1003	if (apic->wakeup_secondary_cpu)
1004		boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1005	else
1006		boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1007						     cpu0_nmi_registered);
1008
1009	if (!boot_error) {
1010		/*
1011		 * Wait 10s total for first sign of life from AP
1012		 */
1013		boot_error = -1;
1014		timeout = jiffies + 10*HZ;
1015		while (time_before(jiffies, timeout)) {
1016			if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1017				/*
1018				 * Tell AP to proceed with initialization
1019				 */
1020				cpumask_set_cpu(cpu, cpu_callout_mask);
1021				boot_error = 0;
1022				break;
1023			}
1024			schedule();
1025		}
1026	}
1027
1028	if (!boot_error) {
1029		/*
1030		 * Wait till AP completes initial initialization
1031		 */
1032		while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
 
 
 
1033			/*
1034			 * Allow other tasks to run while we wait for the
1035			 * AP to come online. This also gives a chance
1036			 * for the MTRR work(triggered by the AP coming online)
1037			 * to be completed in the stop machine context.
1038			 */
1039			schedule();
1040		}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1041	}
1042
1043	/* mark "stuck" area as not stuck */
1044	*trampoline_status = 0;
1045
1046	if (x86_platform.legacy.warm_reset) {
1047		/*
1048		 * Cleanup possible dangling ends...
1049		 */
1050		smpboot_restore_warm_reset_vector();
1051	}
 
 
 
 
 
 
1052
1053	return boot_error;
1054}
1055
1056int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1057{
1058	int apicid = apic->cpu_present_to_apicid(cpu);
1059	int cpu0_nmi_registered = 0;
1060	unsigned long flags;
1061	int err, ret = 0;
1062
1063	lockdep_assert_irqs_enabled();
1064
1065	pr_debug("++++++++++++++++++++=_---CPU UP  %u\n", cpu);
1066
1067	if (apicid == BAD_APICID ||
1068	    !physid_isset(apicid, phys_cpu_present_map) ||
1069	    !apic->apic_id_valid(apicid)) {
1070		pr_err("%s: bad cpu %d\n", __func__, cpu);
1071		return -EINVAL;
1072	}
1073
1074	/*
1075	 * Already booted CPU?
1076	 */
1077	if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1078		pr_debug("do_boot_cpu %d Already started\n", cpu);
1079		return -ENOSYS;
1080	}
1081
1082	/*
1083	 * Save current MTRR state in case it was changed since early boot
1084	 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1085	 */
1086	mtrr_save_state();
1087
1088	/* x86 CPUs take themselves offline, so delayed offline is OK. */
1089	err = cpu_check_up_prepare(cpu);
1090	if (err && err != -EBUSY)
1091		return err;
1092
1093	/* the FPU context is blank, nobody can own it */
1094	per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1095
1096	common_cpu_up(cpu, tidle);
1097
1098	err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1099	if (err) {
1100		pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1101		ret = -EIO;
1102		goto unreg_nmi;
1103	}
1104
1105	/*
1106	 * Check TSC synchronization with the AP (keep irqs disabled
1107	 * while doing so):
1108	 */
1109	local_irq_save(flags);
1110	check_tsc_sync_source(cpu);
1111	local_irq_restore(flags);
1112
1113	while (!cpu_online(cpu)) {
1114		cpu_relax();
1115		touch_nmi_watchdog();
1116	}
1117
1118unreg_nmi:
1119	/*
1120	 * Clean up the nmi handler. Do this after the callin and callout sync
1121	 * to avoid impact of possible long unregister time.
1122	 */
1123	if (cpu0_nmi_registered)
1124		unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1125
1126	return ret;
1127}
1128
1129/**
1130 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1131 */
1132void arch_disable_smp_support(void)
1133{
1134	disable_ioapic_support();
1135}
1136
1137/*
1138 * Fall back to non SMP mode after errors.
1139 *
1140 * RED-PEN audit/test this more. I bet there is more state messed up here.
1141 */
1142static __init void disable_smp(void)
1143{
1144	pr_info("SMP disabled\n");
1145
1146	disable_ioapic_support();
1147
1148	init_cpu_present(cpumask_of(0));
1149	init_cpu_possible(cpumask_of(0));
 
1150
1151	if (smp_found_config)
1152		physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1153	else
1154		physid_set_mask_of_physid(0, &phys_cpu_present_map);
1155	cpumask_set_cpu(0, topology_sibling_cpumask(0));
1156	cpumask_set_cpu(0, topology_core_cpumask(0));
1157}
1158
1159/*
1160 * Various sanity checks.
1161 */
1162static void __init smp_sanity_check(void)
1163{
1164	preempt_disable();
1165
1166#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1167	if (def_to_bigsmp && nr_cpu_ids > 8) {
1168		unsigned int cpu;
1169		unsigned nr;
1170
1171		pr_warn("More than 8 CPUs detected - skipping them\n"
1172			"Use CONFIG_X86_BIGSMP\n");
1173
1174		nr = 0;
1175		for_each_present_cpu(cpu) {
1176			if (nr >= 8)
1177				set_cpu_present(cpu, false);
1178			nr++;
1179		}
1180
1181		nr = 0;
1182		for_each_possible_cpu(cpu) {
1183			if (nr >= 8)
1184				set_cpu_possible(cpu, false);
1185			nr++;
1186		}
1187
1188		nr_cpu_ids = 8;
1189	}
1190#endif
1191
1192	if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1193		pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1194			hard_smp_processor_id());
1195
1196		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1197	}
1198
1199	/*
 
 
 
 
 
 
 
 
 
 
 
 
 
1200	 * Should not be necessary because the MP table should list the boot
1201	 * CPU too, but we do it for the sake of robustness anyway.
1202	 */
1203	if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1204		pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1205			  boot_cpu_physical_apicid);
1206		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1207	}
1208	preempt_enable();
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1209}
1210
1211static void __init smp_cpu_index_default(void)
1212{
1213	int i;
1214	struct cpuinfo_x86 *c;
1215
1216	for_each_possible_cpu(i) {
1217		c = &cpu_data(i);
1218		/* mark all to hotplug */
1219		c->cpu_index = nr_cpu_ids;
1220	}
1221}
1222
1223static void __init smp_get_logical_apicid(void)
1224{
1225	if (x2apic_mode)
1226		cpu0_logical_apicid = apic_read(APIC_LDR);
1227	else
1228		cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1229}
1230
1231/*
1232 * Prepare for SMP bootup.
1233 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1234 *            for common interface support.
1235 */
1236void __init native_smp_prepare_cpus(unsigned int max_cpus)
1237{
1238	unsigned int i;
1239
 
1240	smp_cpu_index_default();
1241
1242	/*
1243	 * Setup boot CPU information
1244	 */
1245	smp_store_boot_cpu_info(); /* Final full version of the data */
1246	cpumask_copy(cpu_callin_mask, cpumask_of(0));
1247	mb();
1248
 
1249	for_each_possible_cpu(i) {
1250		zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1251		zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1252		zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1253	}
1254
1255	/*
1256	 * Set 'default' x86 topology, this matches default_topology() in that
1257	 * it has NUMA nodes as a topology level. See also
1258	 * native_smp_cpus_done().
1259	 *
1260	 * Must be done before set_cpus_sibling_map() is ran.
1261	 */
1262	set_sched_topology(x86_topology);
1263
1264	set_cpu_sibling_map(0);
1265
1266	smp_sanity_check();
1267
1268	switch (apic_intr_mode) {
1269	case APIC_PIC:
1270	case APIC_VIRTUAL_WIRE_NO_CONFIG:
1271		disable_smp();
1272		return;
1273	case APIC_SYMMETRIC_IO_NO_ROUTING:
1274		disable_smp();
1275		/* Setup local timer */
1276		x86_init.timers.setup_percpu_clockev();
1277		return;
1278	case APIC_VIRTUAL_WIRE:
1279	case APIC_SYMMETRIC_IO:
1280		break;
1281	}
1282
1283	/* Setup local timer */
1284	x86_init.timers.setup_percpu_clockev();
1285
1286	smp_get_logical_apicid();
 
 
 
 
 
 
1287
1288	pr_info("CPU0: ");
1289	print_cpu_info(&cpu_data(0));
1290
1291	native_pv_lock_init();
 
 
 
1292
1293	uv_system_init();
 
 
 
1294
1295	set_mtrr_aps_delayed_init();
 
 
 
 
1296
1297	smp_quirk_init_udelay();
1298
1299	speculative_store_bypass_ht_init();
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1300}
1301
1302void arch_enable_nonboot_cpus_begin(void)
1303{
1304	set_mtrr_aps_delayed_init();
1305}
1306
1307void arch_enable_nonboot_cpus_end(void)
1308{
1309	mtrr_aps_init();
1310}
1311
1312/*
1313 * Early setup to make printk work.
1314 */
1315void __init native_smp_prepare_boot_cpu(void)
1316{
1317	int me = smp_processor_id();
1318	switch_to_new_gdt(me);
1319	/* already set me in cpu_online_mask in boot_cpu_init() */
1320	cpumask_set_cpu(me, cpu_callout_mask);
1321	cpu_set_state_online(me);
1322}
1323
1324void __init calculate_max_logical_packages(void)
1325{
1326	int ncpus;
1327
1328	/*
1329	 * Today neither Intel nor AMD support heterogenous systems so
1330	 * extrapolate the boot cpu's data to all packages.
1331	 */
1332	ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1333	__max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
1334	pr_info("Max logical packages: %u\n", __max_logical_packages);
1335}
1336
1337void __init native_smp_cpus_done(unsigned int max_cpus)
1338{
1339	pr_debug("Boot done\n");
1340
1341	calculate_max_logical_packages();
1342
1343	if (x86_has_numa_in_package)
1344		set_sched_topology(x86_numa_in_package_topology);
1345
1346	nmi_selftest();
1347	impress_friends();
 
 
 
1348	mtrr_aps_init();
1349}
1350
1351static int __initdata setup_possible_cpus = -1;
1352static int __init _setup_possible_cpus(char *str)
1353{
1354	get_option(&str, &setup_possible_cpus);
1355	return 0;
1356}
1357early_param("possible_cpus", _setup_possible_cpus);
1358
1359
1360/*
1361 * cpu_possible_mask should be static, it cannot change as cpu's
1362 * are onlined, or offlined. The reason is per-cpu data-structures
1363 * are allocated by some modules at init time, and dont expect to
1364 * do this dynamically on cpu arrival/departure.
1365 * cpu_present_mask on the other hand can change dynamically.
1366 * In case when cpu_hotplug is not compiled, then we resort to current
1367 * behaviour, which is cpu_possible == cpu_present.
1368 * - Ashok Raj
1369 *
1370 * Three ways to find out the number of additional hotplug CPUs:
1371 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1372 * - The user can overwrite it with possible_cpus=NUM
1373 * - Otherwise don't reserve additional CPUs.
1374 * We do this because additional CPUs waste a lot of memory.
1375 * -AK
1376 */
1377__init void prefill_possible_map(void)
1378{
1379	int i, possible;
1380
1381	/* No boot processor was found in mptable or ACPI MADT */
1382	if (!num_processors) {
1383		if (boot_cpu_has(X86_FEATURE_APIC)) {
1384			int apicid = boot_cpu_physical_apicid;
1385			int cpu = hard_smp_processor_id();
1386
1387			pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1388
1389			/* Make sure boot cpu is enumerated */
1390			if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1391			    apic->apic_id_valid(apicid))
1392				generic_processor_info(apicid, boot_cpu_apic_version);
1393		}
1394
1395		if (!num_processors)
1396			num_processors = 1;
1397	}
1398
1399	i = setup_max_cpus ?: 1;
1400	if (setup_possible_cpus == -1) {
1401		possible = num_processors;
1402#ifdef CONFIG_HOTPLUG_CPU
1403		if (setup_max_cpus)
1404			possible += disabled_cpus;
1405#else
1406		if (possible > i)
1407			possible = i;
1408#endif
1409	} else
1410		possible = setup_possible_cpus;
1411
1412	total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1413
1414	/* nr_cpu_ids could be reduced via nr_cpus= */
1415	if (possible > nr_cpu_ids) {
1416		pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1417			possible, nr_cpu_ids);
1418		possible = nr_cpu_ids;
1419	}
1420
1421#ifdef CONFIG_HOTPLUG_CPU
1422	if (!setup_max_cpus)
1423#endif
1424	if (possible > i) {
1425		pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1426			possible, setup_max_cpus);
1427		possible = i;
1428	}
1429
1430	nr_cpu_ids = possible;
1431
1432	pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1433		possible, max_t(int, possible - num_processors, 0));
1434
1435	reset_cpu_possible_mask();
1436
1437	for (i = 0; i < possible; i++)
1438		set_cpu_possible(i, true);
 
 
 
 
1439}
1440
1441#ifdef CONFIG_HOTPLUG_CPU
1442
1443/* Recompute SMT state for all CPUs on offline */
1444static void recompute_smt_state(void)
1445{
1446	int max_threads, cpu;
1447
1448	max_threads = 0;
1449	for_each_online_cpu (cpu) {
1450		int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1451
1452		if (threads > max_threads)
1453			max_threads = threads;
1454	}
1455	__max_smt_threads = max_threads;
1456}
1457
1458static void remove_siblinginfo(int cpu)
1459{
1460	int sibling;
1461	struct cpuinfo_x86 *c = &cpu_data(cpu);
1462
1463	for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1464		cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1465		/*/
1466		 * last thread sibling in this cpu core going down
1467		 */
1468		if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1469			cpu_data(sibling).booted_cores--;
1470	}
1471
1472	for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1473		cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1474	for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1475		cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1476	cpumask_clear(cpu_llc_shared_mask(cpu));
1477	cpumask_clear(topology_sibling_cpumask(cpu));
1478	cpumask_clear(topology_core_cpumask(cpu));
1479	c->cpu_core_id = 0;
1480	c->booted_cores = 0;
1481	cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1482	recompute_smt_state();
1483}
1484
1485static void remove_cpu_from_maps(int cpu)
1486{
1487	set_cpu_online(cpu, false);
1488	cpumask_clear_cpu(cpu, cpu_callout_mask);
1489	cpumask_clear_cpu(cpu, cpu_callin_mask);
1490	/* was set by cpu_init() */
1491	cpumask_clear_cpu(cpu, cpu_initialized_mask);
1492	numa_remove_cpu(cpu);
1493}
1494
1495void cpu_disable_common(void)
1496{
1497	int cpu = smp_processor_id();
1498
1499	remove_siblinginfo(cpu);
1500
1501	/* It's now safe to remove this processor from the online map */
1502	lock_vector_lock();
1503	remove_cpu_from_maps(cpu);
1504	unlock_vector_lock();
1505	fixup_irqs();
1506	lapic_offline();
1507}
1508
1509int native_cpu_disable(void)
1510{
1511	int ret;
1512
1513	ret = lapic_can_unplug_cpu();
1514	if (ret)
1515		return ret;
1516
1517	clear_local_APIC();
1518	cpu_disable_common();
1519
 
1520	return 0;
1521}
1522
1523int common_cpu_die(unsigned int cpu)
1524{
1525	int ret = 0;
1526
1527	/* We don't do anything here: idle task is faking death itself. */
 
1528
1529	/* They ack this in play_dead() by setting CPU_DEAD */
1530	if (cpu_wait_death(cpu, 5)) {
1531		if (system_state == SYSTEM_RUNNING)
1532			pr_info("CPU %u is now offline\n", cpu);
1533	} else {
1534		pr_err("CPU %u didn't die...\n", cpu);
1535		ret = -1;
 
1536	}
1537
1538	return ret;
1539}
1540
1541void native_cpu_die(unsigned int cpu)
1542{
1543	common_cpu_die(cpu);
1544}
1545
1546void play_dead_common(void)
1547{
1548	idle_task_exit();
 
 
1549
 
1550	/* Ack it */
1551	(void)cpu_report_death();
1552
1553	/*
1554	 * With physical CPU hotplug, we should halt the cpu
1555	 */
1556	local_irq_disable();
1557}
1558
1559static bool wakeup_cpu0(void)
1560{
1561	if (smp_processor_id() == 0 && enable_start_cpu0)
1562		return true;
1563
1564	return false;
1565}
1566
1567/*
1568 * We need to flush the caches before going to sleep, lest we have
1569 * dirty data in our caches when we come back up.
1570 */
1571static inline void mwait_play_dead(void)
1572{
1573	unsigned int eax, ebx, ecx, edx;
1574	unsigned int highest_cstate = 0;
1575	unsigned int highest_subcstate = 0;
1576	void *mwait_ptr;
1577	int i;
1578
1579	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1580		return;
1581	if (!this_cpu_has(X86_FEATURE_MWAIT))
1582		return;
1583	if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1584		return;
1585	if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1586		return;
1587
1588	eax = CPUID_MWAIT_LEAF;
1589	ecx = 0;
1590	native_cpuid(&eax, &ebx, &ecx, &edx);
1591
1592	/*
1593	 * eax will be 0 if EDX enumeration is not valid.
1594	 * Initialized below to cstate, sub_cstate value when EDX is valid.
1595	 */
1596	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1597		eax = 0;
1598	} else {
1599		edx >>= MWAIT_SUBSTATE_SIZE;
1600		for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1601			if (edx & MWAIT_SUBSTATE_MASK) {
1602				highest_cstate = i;
1603				highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1604			}
1605		}
1606		eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1607			(highest_subcstate - 1);
1608	}
1609
1610	/*
1611	 * This should be a memory location in a cache line which is
1612	 * unlikely to be touched by other processors.  The actual
1613	 * content is immaterial as it is not actually modified in any way.
1614	 */
1615	mwait_ptr = &current_thread_info()->flags;
1616
1617	wbinvd();
1618
1619	while (1) {
1620		/*
1621		 * The CLFLUSH is a workaround for erratum AAI65 for
1622		 * the Xeon 7400 series.  It's not clear it is actually
1623		 * needed, but it should be harmless in either case.
1624		 * The WBINVD is insufficient due to the spurious-wakeup
1625		 * case where we return around the loop.
1626		 */
1627		mb();
1628		clflush(mwait_ptr);
1629		mb();
1630		__monitor(mwait_ptr, 0, 0);
1631		mb();
1632		__mwait(eax, 0);
1633		/*
1634		 * If NMI wants to wake up CPU0, start CPU0.
1635		 */
1636		if (wakeup_cpu0())
1637			start_cpu0();
1638	}
1639}
1640
1641void hlt_play_dead(void)
1642{
1643	if (__this_cpu_read(cpu_info.x86) >= 4)
1644		wbinvd();
1645
1646	while (1) {
1647		native_halt();
1648		/*
1649		 * If NMI wants to wake up CPU0, start CPU0.
1650		 */
1651		if (wakeup_cpu0())
1652			start_cpu0();
1653	}
1654}
1655
1656void native_play_dead(void)
1657{
1658	play_dead_common();
1659	tboot_shutdown(TB_SHUTDOWN_WFS);
1660
1661	mwait_play_dead();	/* Only returns on failure */
1662	if (cpuidle_play_dead())
1663		hlt_play_dead();
1664}
1665
1666#else /* ... !CONFIG_HOTPLUG_CPU */
1667int native_cpu_disable(void)
1668{
1669	return -ENOSYS;
1670}
1671
1672void native_cpu_die(unsigned int cpu)
1673{
1674	/* We said "no" in __cpu_disable */
1675	BUG();
1676}
1677
1678void native_play_dead(void)
1679{
1680	BUG();
1681}
1682
1683#endif