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1/*
2 * STx/Freescale ADS5125 MPC5125 silicon
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
5 *
6 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
7 * Copyright (C) 2013 Sirius Electronic Systems
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <dt-bindings/clock/mpc512x-clock.h>
16
17/dts-v1/;
18
19/ {
20 model = "mpc5125twr"; // In BSP "mpc5125ads"
21 compatible = "fsl,mpc5125ads", "fsl,mpc5125";
22 #address-cells = <1>;
23 #size-cells = <1>;
24 interrupt-parent = <&ipic>;
25
26 aliases {
27 gpio0 = &gpio0;
28 gpio1 = &gpio1;
29 ethernet0 = ð0;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5125@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
44 bus-frequency = <198000000>; // 198 MHz csb bus
45 clock-frequency = <396000000>; // 396 MHz ppc core
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x10000000>; // 256MB at 0
52 };
53
54 sram@30000000 {
55 compatible = "fsl,mpc5121-sram";
56 reg = <0x30000000 0x08000>; // 32K at 0x30000000
57 };
58
59 clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 osc: osc {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <33000000>;
67 };
68 };
69
70 soc@80000000 {
71 compatible = "fsl,mpc5121-immr";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges = <0x0 0x80000000 0x400000>;
75 reg = <0x80000000 0x400000>;
76 bus-frequency = <66000000>; // 66 MHz ips bus
77
78 // IPIC
79 // interrupts cell = <intr #, sense>
80 // sense values match linux IORESOURCE_IRQ_* defines:
81 // sense == 8: Level, low assertion
82 // sense == 2: Edge, high-to-low change
83 //
84 ipic: interrupt-controller@c00 {
85 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
86 interrupt-controller;
87 #address-cells = <0>;
88 #interrupt-cells = <2>;
89 reg = <0xc00 0x100>;
90 };
91
92 rtc@a00 { // Real time clock
93 compatible = "fsl,mpc5121-rtc";
94 reg = <0xa00 0x100>;
95 interrupts = <79 0x8 80 0x8>;
96 };
97
98 reset@e00 { // Reset module
99 compatible = "fsl,mpc5125-reset";
100 reg = <0xe00 0x100>;
101 };
102
103 clks: clock@f00 { // Clock control
104 compatible = "fsl,mpc5121-clock";
105 reg = <0xf00 0x100>;
106 #clock-cells = <1>;
107 clocks = <&osc>;
108 clock-names = "osc";
109 };
110
111 pmc@1000{ // Power Management Controller
112 compatible = "fsl,mpc5121-pmc";
113 reg = <0x1000 0x100>;
114 interrupts = <83 0x2>;
115 };
116
117 gpio0: gpio@1100 {
118 compatible = "fsl,mpc5125-gpio";
119 reg = <0x1100 0x080>;
120 interrupts = <78 0x8>;
121 };
122
123 gpio1: gpio@1180 {
124 compatible = "fsl,mpc5125-gpio";
125 reg = <0x1180 0x080>;
126 interrupts = <86 0x8>;
127 };
128
129 can@1300 { // CAN rev.2
130 compatible = "fsl,mpc5121-mscan";
131 interrupts = <12 0x8>;
132 reg = <0x1300 0x80>;
133 clocks = <&clks MPC512x_CLK_BDLC>,
134 <&clks MPC512x_CLK_IPS>,
135 <&clks MPC512x_CLK_SYS>,
136 <&clks MPC512x_CLK_REF>,
137 <&clks MPC512x_CLK_MSCAN0_MCLK>;
138 clock-names = "ipg", "ips", "sys", "ref", "mclk";
139 };
140
141 can@1380 {
142 compatible = "fsl,mpc5121-mscan";
143 interrupts = <13 0x8>;
144 reg = <0x1380 0x80>;
145 clocks = <&clks MPC512x_CLK_BDLC>,
146 <&clks MPC512x_CLK_IPS>,
147 <&clks MPC512x_CLK_SYS>,
148 <&clks MPC512x_CLK_REF>,
149 <&clks MPC512x_CLK_MSCAN1_MCLK>;
150 clock-names = "ipg", "ips", "sys", "ref", "mclk";
151 };
152
153 sdhc@1500 {
154 compatible = "fsl,mpc5121-sdhc";
155 interrupts = <8 0x8>;
156 reg = <0x1500 0x100>;
157 clocks = <&clks MPC512x_CLK_IPS>,
158 <&clks MPC512x_CLK_SDHC>;
159 clock-names = "ipg", "per";
160 };
161
162 i2c@1700 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
166 reg = <0x1700 0x20>;
167 interrupts = <0x9 0x8>;
168 clocks = <&clks MPC512x_CLK_I2C>;
169 clock-names = "ipg";
170 };
171
172 i2c@1720 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
176 reg = <0x1720 0x20>;
177 interrupts = <0xa 0x8>;
178 clocks = <&clks MPC512x_CLK_I2C>;
179 clock-names = "ipg";
180 };
181
182 i2c@1740 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
186 reg = <0x1740 0x20>;
187 interrupts = <0xb 0x8>;
188 clocks = <&clks MPC512x_CLK_I2C>;
189 clock-names = "ipg";
190 };
191
192 i2ccontrol@1760 {
193 compatible = "fsl,mpc5121-i2c-ctrl";
194 reg = <0x1760 0x8>;
195 };
196
197 diu@2100 {
198 compatible = "fsl,mpc5121-diu";
199 reg = <0x2100 0x100>;
200 interrupts = <64 0x8>;
201 clocks = <&clks MPC512x_CLK_DIU>;
202 clock-names = "ipg";
203 };
204
205 mdio@2800 {
206 compatible = "fsl,mpc5121-fec-mdio";
207 reg = <0x2800 0x800>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 phy0: ethernet-phy@0 {
211 reg = <1>;
212 };
213 };
214
215 eth0: ethernet@2800 {
216 compatible = "fsl,mpc5125-fec";
217 reg = <0x2800 0x800>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <4 0x8>;
220 phy-handle = < &phy0 >;
221 phy-connection-type = "rmii";
222 clocks = <&clks MPC512x_CLK_FEC>;
223 clock-names = "per";
224 };
225
226 // IO control
227 ioctl@a000 {
228 compatible = "fsl,mpc5125-ioctl";
229 reg = <0xA000 0x1000>;
230 };
231
232 // disable USB1 port
233 // TODO:
234 // correct pinmux config and fix USB3320 ulpi dependency
235 // before re-enabling it
236 usb@3000 {
237 compatible = "fsl,mpc5121-usb2-dr";
238 reg = <0x3000 0x400>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 interrupts = <43 0x8>;
242 dr_mode = "host";
243 phy_type = "ulpi";
244 clocks = <&clks MPC512x_CLK_USB1>;
245 clock-names = "ipg";
246 status = "disabled";
247 };
248
249 sclpc@10100 {
250 compatible = "fsl,mpc512x-lpbfifo";
251 reg = <0x10100 0x50>;
252 interrupts = <7 0x8>;
253 dmas = <&dma0 26>;
254 dma-names = "rx-tx";
255 };
256
257 // 5125 PSCs are not 52xx or 5121 PSC compatible
258 // PSC1 uart0 aka ttyPSC0
259 serial@11100 {
260 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
261 reg = <0x11100 0x100>;
262 interrupts = <40 0x8>;
263 fsl,rx-fifo-size = <16>;
264 fsl,tx-fifo-size = <16>;
265 clocks = <&clks MPC512x_CLK_PSC1>,
266 <&clks MPC512x_CLK_PSC1_MCLK>;
267 clock-names = "ipg", "mclk";
268 };
269
270 // PSC9 uart1 aka ttyPSC1
271 serial@11900 {
272 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
273 reg = <0x11900 0x100>;
274 interrupts = <40 0x8>;
275 fsl,rx-fifo-size = <16>;
276 fsl,tx-fifo-size = <16>;
277 clocks = <&clks MPC512x_CLK_PSC9>,
278 <&clks MPC512x_CLK_PSC9_MCLK>;
279 clock-names = "ipg", "mclk";
280 };
281
282 pscfifo@11f00 {
283 compatible = "fsl,mpc5121-psc-fifo";
284 reg = <0x11f00 0x100>;
285 interrupts = <40 0x8>;
286 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
287 clock-names = "ipg";
288 };
289
290 dma0: dma@14000 {
291 compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
292 reg = <0x14000 0x1800>;
293 interrupts = <65 0x8>;
294 #dma-cells = <1>;
295 };
296 };
297};
1/*
2 * STx/Freescale ADS5125 MPC5125 silicon
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
5 *
6 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
7 * Copyright (C) 2013 Sirius Electronic Systems
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <dt-bindings/clock/mpc512x-clock.h>
16
17/dts-v1/;
18
19/ {
20 model = "mpc5125twr"; // In BSP "mpc5125ads"
21 compatible = "fsl,mpc5125ads", "fsl,mpc5125";
22 #address-cells = <1>;
23 #size-cells = <1>;
24 interrupt-parent = <&ipic>;
25
26 aliases {
27 gpio0 = &gpio0;
28 gpio1 = &gpio1;
29 ethernet0 = ð0;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5125@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
44 bus-frequency = <198000000>; // 198 MHz csb bus
45 clock-frequency = <396000000>; // 396 MHz ppc core
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x10000000>; // 256MB at 0
52 };
53
54 sram@30000000 {
55 compatible = "fsl,mpc5121-sram";
56 reg = <0x30000000 0x08000>; // 32K at 0x30000000
57 };
58
59 clocks {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 osc: osc {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <33000000>;
67 };
68 };
69
70 soc@80000000 {
71 compatible = "fsl,mpc5121-immr";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges = <0x0 0x80000000 0x400000>;
75 reg = <0x80000000 0x400000>;
76 bus-frequency = <66000000>; // 66 MHz ips bus
77
78 // IPIC
79 // interrupts cell = <intr #, sense>
80 // sense values match linux IORESOURCE_IRQ_* defines:
81 // sense == 8: Level, low assertion
82 // sense == 2: Edge, high-to-low change
83 //
84 ipic: interrupt-controller@c00 {
85 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
86 interrupt-controller;
87 #address-cells = <0>;
88 #interrupt-cells = <2>;
89 reg = <0xc00 0x100>;
90 };
91
92 rtc@a00 { // Real time clock
93 compatible = "fsl,mpc5121-rtc";
94 reg = <0xa00 0x100>;
95 interrupts = <79 0x8 80 0x8>;
96 };
97
98 reset@e00 { // Reset module
99 compatible = "fsl,mpc5125-reset";
100 reg = <0xe00 0x100>;
101 };
102
103 clks: clock@f00 { // Clock control
104 compatible = "fsl,mpc5121-clock";
105 reg = <0xf00 0x100>;
106 #clock-cells = <1>;
107 clocks = <&osc>;
108 clock-names = "osc";
109 };
110
111 pmc@1000{ // Power Management Controller
112 compatible = "fsl,mpc5121-pmc";
113 reg = <0x1000 0x100>;
114 interrupts = <83 0x2>;
115 };
116
117 gpio0: gpio@1100 {
118 compatible = "fsl,mpc5125-gpio";
119 reg = <0x1100 0x080>;
120 interrupts = <78 0x8>;
121 };
122
123 gpio1: gpio@1180 {
124 compatible = "fsl,mpc5125-gpio";
125 reg = <0x1180 0x080>;
126 interrupts = <86 0x8>;
127 };
128
129 can@1300 { // CAN rev.2
130 compatible = "fsl,mpc5121-mscan";
131 interrupts = <12 0x8>;
132 reg = <0x1300 0x80>;
133 clocks = <&clks MPC512x_CLK_BDLC>,
134 <&clks MPC512x_CLK_IPS>,
135 <&clks MPC512x_CLK_SYS>,
136 <&clks MPC512x_CLK_REF>,
137 <&clks MPC512x_CLK_MSCAN0_MCLK>;
138 clock-names = "ipg", "ips", "sys", "ref", "mclk";
139 };
140
141 can@1380 {
142 compatible = "fsl,mpc5121-mscan";
143 interrupts = <13 0x8>;
144 reg = <0x1380 0x80>;
145 clocks = <&clks MPC512x_CLK_BDLC>,
146 <&clks MPC512x_CLK_IPS>,
147 <&clks MPC512x_CLK_SYS>,
148 <&clks MPC512x_CLK_REF>,
149 <&clks MPC512x_CLK_MSCAN1_MCLK>;
150 clock-names = "ipg", "ips", "sys", "ref", "mclk";
151 };
152
153 sdhc@1500 {
154 compatible = "fsl,mpc5121-sdhc";
155 interrupts = <8 0x8>;
156 reg = <0x1500 0x100>;
157 clocks = <&clks MPC512x_CLK_IPS>,
158 <&clks MPC512x_CLK_SDHC>;
159 clock-names = "ipg", "per";
160 };
161
162 i2c@1700 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
166 reg = <0x1700 0x20>;
167 interrupts = <0x9 0x8>;
168 clocks = <&clks MPC512x_CLK_I2C>;
169 clock-names = "ipg";
170 };
171
172 i2c@1720 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
176 reg = <0x1720 0x20>;
177 interrupts = <0xa 0x8>;
178 clocks = <&clks MPC512x_CLK_I2C>;
179 clock-names = "ipg";
180 };
181
182 i2c@1740 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
186 reg = <0x1740 0x20>;
187 interrupts = <0xb 0x8>;
188 clocks = <&clks MPC512x_CLK_I2C>;
189 clock-names = "ipg";
190 };
191
192 i2ccontrol@1760 {
193 compatible = "fsl,mpc5121-i2c-ctrl";
194 reg = <0x1760 0x8>;
195 };
196
197 diu@2100 {
198 compatible = "fsl,mpc5121-diu";
199 reg = <0x2100 0x100>;
200 interrupts = <64 0x8>;
201 clocks = <&clks MPC512x_CLK_DIU>;
202 clock-names = "ipg";
203 };
204
205 mdio@2800 {
206 compatible = "fsl,mpc5121-fec-mdio";
207 reg = <0x2800 0x800>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210 phy0: ethernet-phy@0 {
211 reg = <1>;
212 };
213 };
214
215 eth0: ethernet@2800 {
216 compatible = "fsl,mpc5125-fec";
217 reg = <0x2800 0x800>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <4 0x8>;
220 phy-handle = < &phy0 >;
221 phy-connection-type = "rmii";
222 clocks = <&clks MPC512x_CLK_FEC>;
223 clock-names = "per";
224 };
225
226 // IO control
227 ioctl@a000 {
228 compatible = "fsl,mpc5125-ioctl";
229 reg = <0xA000 0x1000>;
230 };
231
232 // disable USB1 port
233 // TODO:
234 // correct pinmux config and fix USB3320 ulpi dependency
235 // before re-enabling it
236 usb@3000 {
237 compatible = "fsl,mpc5121-usb2-dr";
238 reg = <0x3000 0x400>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 interrupts = <43 0x8>;
242 dr_mode = "host";
243 phy_type = "ulpi";
244 clocks = <&clks MPC512x_CLK_USB1>;
245 clock-names = "ipg";
246 status = "disabled";
247 };
248
249 // 5125 PSCs are not 52xx or 5121 PSC compatible
250 // PSC1 uart0 aka ttyPSC0
251 serial@11100 {
252 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
253 reg = <0x11100 0x100>;
254 interrupts = <40 0x8>;
255 fsl,rx-fifo-size = <16>;
256 fsl,tx-fifo-size = <16>;
257 clocks = <&clks MPC512x_CLK_PSC1>,
258 <&clks MPC512x_CLK_PSC1_MCLK>;
259 clock-names = "ipg", "mclk";
260 };
261
262 // PSC9 uart1 aka ttyPSC1
263 serial@11900 {
264 compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
265 reg = <0x11900 0x100>;
266 interrupts = <40 0x8>;
267 fsl,rx-fifo-size = <16>;
268 fsl,tx-fifo-size = <16>;
269 clocks = <&clks MPC512x_CLK_PSC9>,
270 <&clks MPC512x_CLK_PSC9_MCLK>;
271 clock-names = "ipg", "mclk";
272 };
273
274 pscfifo@11f00 {
275 compatible = "fsl,mpc5121-psc-fifo";
276 reg = <0x11f00 0x100>;
277 interrupts = <40 0x8>;
278 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
279 clock-names = "ipg";
280 };
281
282 dma@14000 {
283 compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
284 reg = <0x14000 0x1800>;
285 interrupts = <65 0x8>;
286 };
287 };
288};