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1# SPDX-License-Identifier: GPL-2.0
2comment "Processor Type"
3
4# Select CPU types depending on the architecture selected. This selects
5# which CPUs we support in the kernel image, and the compiler instruction
6# optimiser behaviour.
7
8# ARM7TDMI
9config CPU_ARM7TDMI
10 bool
11 depends on !MMU
12 select CPU_32v4T
13 select CPU_ABRT_LV4T
14 select CPU_CACHE_V4
15 select CPU_PABRT_LEGACY
16 help
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
19
20 Say Y if you want support for the ARM7TDMI processor.
21 Otherwise, say N.
22
23# ARM720T
24config CPU_ARM720T
25 bool
26 select CPU_32v4T
27 select CPU_ABRT_LV4T
28 select CPU_CACHE_V4
29 select CPU_CACHE_VIVT
30 select CPU_COPY_V4WT if MMU
31 select CPU_CP15_MMU
32 select CPU_PABRT_LEGACY
33 select CPU_THUMB_CAPABLE
34 select CPU_TLB_V4WT if MMU
35 help
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
37 MMU built around an ARM7TDMI core.
38
39 Say Y if you want support for the ARM720T processor.
40 Otherwise, say N.
41
42# ARM740T
43config CPU_ARM740T
44 bool
45 depends on !MMU
46 select CPU_32v4T
47 select CPU_ABRT_LV4T
48 select CPU_CACHE_V4
49 select CPU_CP15_MPU
50 select CPU_PABRT_LEGACY
51 select CPU_THUMB_CAPABLE
52 help
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
55 an ARM7TDMI core.
56
57 Say Y if you want support for the ARM740T processor.
58 Otherwise, say N.
59
60# ARM9TDMI
61config CPU_ARM9TDMI
62 bool
63 depends on !MMU
64 select CPU_32v4T
65 select CPU_ABRT_NOMMU
66 select CPU_CACHE_V4
67 select CPU_PABRT_LEGACY
68 help
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
71
72 Say Y if you want support for the ARM9TDMI processor.
73 Otherwise, say N.
74
75# ARM920T
76config CPU_ARM920T
77 bool
78 select CPU_32v4T
79 select CPU_ABRT_EV4T
80 select CPU_CACHE_V4WT
81 select CPU_CACHE_VIVT
82 select CPU_COPY_V4WB if MMU
83 select CPU_CP15_MMU
84 select CPU_PABRT_LEGACY
85 select CPU_THUMB_CAPABLE
86 select CPU_TLB_V4WBI if MMU
87 help
88 The ARM920T is licensed to be produced by numerous vendors,
89 and is used in the Cirrus EP93xx and the Samsung S3C2410.
90
91 Say Y if you want support for the ARM920T processor.
92 Otherwise, say N.
93
94# ARM922T
95config CPU_ARM922T
96 bool
97 select CPU_32v4T
98 select CPU_ABRT_EV4T
99 select CPU_CACHE_V4WT
100 select CPU_CACHE_VIVT
101 select CPU_COPY_V4WB if MMU
102 select CPU_CP15_MMU
103 select CPU_PABRT_LEGACY
104 select CPU_THUMB_CAPABLE
105 select CPU_TLB_V4WBI if MMU
106 help
107 The ARM922T is a version of the ARM920T, but with smaller
108 instruction and data caches. It is used in Altera's
109 Excalibur XA device family and Micrel's KS8695 Centaur.
110
111 Say Y if you want support for the ARM922T processor.
112 Otherwise, say N.
113
114# ARM925T
115config CPU_ARM925T
116 bool
117 select CPU_32v4T
118 select CPU_ABRT_EV4T
119 select CPU_CACHE_V4WT
120 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_CP15_MMU
123 select CPU_PABRT_LEGACY
124 select CPU_THUMB_CAPABLE
125 select CPU_TLB_V4WBI if MMU
126 help
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
128 different instruction and data caches. It is used in TI's OMAP
129 device family.
130
131 Say Y if you want support for the ARM925T processor.
132 Otherwise, say N.
133
134# ARM926T
135config CPU_ARM926T
136 bool
137 select CPU_32v5
138 select CPU_ABRT_EV5TJ
139 select CPU_CACHE_VIVT
140 select CPU_COPY_V4WB if MMU
141 select CPU_CP15_MMU
142 select CPU_PABRT_LEGACY
143 select CPU_THUMB_CAPABLE
144 select CPU_TLB_V4WBI if MMU
145 help
146 This is a variant of the ARM920. It has slightly different
147 instruction sequences for cache and TLB operations. Curiously,
148 there is no documentation on it at the ARM corporate website.
149
150 Say Y if you want support for the ARM926T processor.
151 Otherwise, say N.
152
153# FA526
154config CPU_FA526
155 bool
156 select CPU_32v4
157 select CPU_ABRT_EV4
158 select CPU_CACHE_FA
159 select CPU_CACHE_VIVT
160 select CPU_COPY_FA if MMU
161 select CPU_CP15_MMU
162 select CPU_PABRT_LEGACY
163 select CPU_TLB_FA if MMU
164 help
165 The FA526 is a version of the ARMv4 compatible processor with
166 Branch Target Buffer, Unified TLB and cache line size 16.
167
168 Say Y if you want support for the FA526 processor.
169 Otherwise, say N.
170
171# ARM940T
172config CPU_ARM940T
173 bool
174 depends on !MMU
175 select CPU_32v4T
176 select CPU_ABRT_NOMMU
177 select CPU_CACHE_VIVT
178 select CPU_CP15_MPU
179 select CPU_PABRT_LEGACY
180 select CPU_THUMB_CAPABLE
181 help
182 ARM940T is a member of the ARM9TDMI family of general-
183 purpose microprocessors with MPU and separate 4KB
184 instruction and 4KB data cases, each with a 4-word line
185 length.
186
187 Say Y if you want support for the ARM940T processor.
188 Otherwise, say N.
189
190# ARM946E-S
191config CPU_ARM946E
192 bool
193 depends on !MMU
194 select CPU_32v5
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 select CPU_PABRT_LEGACY
199 select CPU_THUMB_CAPABLE
200 help
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
204
205 Say Y if you want support for the ARM946E-S processor.
206 Otherwise, say N.
207
208# ARM1020 - needs validating
209config CPU_ARM1020
210 bool
211 select CPU_32v5
212 select CPU_ABRT_EV4T
213 select CPU_CACHE_V4WT
214 select CPU_CACHE_VIVT
215 select CPU_COPY_V4WB if MMU
216 select CPU_CP15_MMU
217 select CPU_PABRT_LEGACY
218 select CPU_THUMB_CAPABLE
219 select CPU_TLB_V4WBI if MMU
220 help
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
223
224 Say Y if you want support for the ARM1020 processor.
225 Otherwise, say N.
226
227# ARM1020E - needs validating
228config CPU_ARM1020E
229 bool
230 depends on n
231 select CPU_32v5
232 select CPU_ABRT_EV4T
233 select CPU_CACHE_V4WT
234 select CPU_CACHE_VIVT
235 select CPU_COPY_V4WB if MMU
236 select CPU_CP15_MMU
237 select CPU_PABRT_LEGACY
238 select CPU_THUMB_CAPABLE
239 select CPU_TLB_V4WBI if MMU
240
241# ARM1022E
242config CPU_ARM1022
243 bool
244 select CPU_32v5
245 select CPU_ABRT_EV4T
246 select CPU_CACHE_VIVT
247 select CPU_COPY_V4WB if MMU # can probably do better
248 select CPU_CP15_MMU
249 select CPU_PABRT_LEGACY
250 select CPU_THUMB_CAPABLE
251 select CPU_TLB_V4WBI if MMU
252 help
253 The ARM1022E is an implementation of the ARMv5TE architecture
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
256
257 Say Y if you want support for the ARM1022E processor.
258 Otherwise, say N.
259
260# ARM1026EJ-S
261config CPU_ARM1026
262 bool
263 select CPU_32v5
264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
265 select CPU_CACHE_VIVT
266 select CPU_COPY_V4WB if MMU # can probably do better
267 select CPU_CP15_MMU
268 select CPU_PABRT_LEGACY
269 select CPU_THUMB_CAPABLE
270 select CPU_TLB_V4WBI if MMU
271 help
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
273 based upon the ARM10 integer core.
274
275 Say Y if you want support for the ARM1026EJ-S processor.
276 Otherwise, say N.
277
278# SA110
279config CPU_SA110
280 bool
281 select CPU_32v3 if ARCH_RPC
282 select CPU_32v4 if !ARCH_RPC
283 select CPU_ABRT_EV4
284 select CPU_CACHE_V4WB
285 select CPU_CACHE_VIVT
286 select CPU_COPY_V4WB if MMU
287 select CPU_CP15_MMU
288 select CPU_PABRT_LEGACY
289 select CPU_TLB_V4WB if MMU
290 help
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
292 is available at five speeds ranging from 100 MHz to 233 MHz.
293 More information is available at
294 <http://developer.intel.com/design/strong/sa110.htm>.
295
296 Say Y if you want support for the SA-110 processor.
297 Otherwise, say N.
298
299# SA1100
300config CPU_SA1100
301 bool
302 select CPU_32v4
303 select CPU_ABRT_EV4
304 select CPU_CACHE_V4WB
305 select CPU_CACHE_VIVT
306 select CPU_CP15_MMU
307 select CPU_PABRT_LEGACY
308 select CPU_TLB_V4WB if MMU
309
310# XScale
311config CPU_XSCALE
312 bool
313 select CPU_32v5
314 select CPU_ABRT_EV5T
315 select CPU_CACHE_VIVT
316 select CPU_CP15_MMU
317 select CPU_PABRT_LEGACY
318 select CPU_THUMB_CAPABLE
319 select CPU_TLB_V4WBI if MMU
320
321# XScale Core Version 3
322config CPU_XSC3
323 bool
324 select CPU_32v5
325 select CPU_ABRT_EV5T
326 select CPU_CACHE_VIVT
327 select CPU_CP15_MMU
328 select CPU_PABRT_LEGACY
329 select CPU_THUMB_CAPABLE
330 select CPU_TLB_V4WBI if MMU
331 select IO_36
332
333# Marvell PJ1 (Mohawk)
334config CPU_MOHAWK
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_CACHE_VIVT
339 select CPU_COPY_V4WB if MMU
340 select CPU_CP15_MMU
341 select CPU_PABRT_LEGACY
342 select CPU_THUMB_CAPABLE
343 select CPU_TLB_V4WBI if MMU
344
345# Feroceon
346config CPU_FEROCEON
347 bool
348 select CPU_32v5
349 select CPU_ABRT_EV5T
350 select CPU_CACHE_VIVT
351 select CPU_COPY_FEROCEON if MMU
352 select CPU_CP15_MMU
353 select CPU_PABRT_LEGACY
354 select CPU_THUMB_CAPABLE
355 select CPU_TLB_FEROCEON if MMU
356
357config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
365
366# Marvell PJ4
367config CPU_PJ4
368 bool
369 select ARM_THUMBEE
370 select CPU_V7
371
372config CPU_PJ4B
373 bool
374 select CPU_V7
375
376# ARMv6
377config CPU_V6
378 bool
379 select CPU_32v6
380 select CPU_ABRT_EV6
381 select CPU_CACHE_V6
382 select CPU_CACHE_VIPT
383 select CPU_COPY_V6 if MMU
384 select CPU_CP15_MMU
385 select CPU_HAS_ASID if MMU
386 select CPU_PABRT_V6
387 select CPU_THUMB_CAPABLE
388 select CPU_TLB_V6 if MMU
389
390# ARMv6k
391config CPU_V6K
392 bool
393 select CPU_32v6
394 select CPU_32v6K
395 select CPU_ABRT_EV6
396 select CPU_CACHE_V6
397 select CPU_CACHE_VIPT
398 select CPU_COPY_V6 if MMU
399 select CPU_CP15_MMU
400 select CPU_HAS_ASID if MMU
401 select CPU_PABRT_V6
402 select CPU_THUMB_CAPABLE
403 select CPU_TLB_V6 if MMU
404
405# ARMv7
406config CPU_V7
407 bool
408 select CPU_32v6K
409 select CPU_32v7
410 select CPU_ABRT_EV7
411 select CPU_CACHE_V7
412 select CPU_CACHE_VIPT
413 select CPU_COPY_V6 if MMU
414 select CPU_CP15_MMU if MMU
415 select CPU_CP15_MPU if !MMU
416 select CPU_HAS_ASID if MMU
417 select CPU_PABRT_V7
418 select CPU_THUMB_CAPABLE
419 select CPU_TLB_V7 if MMU
420
421# ARMv7M
422config CPU_V7M
423 bool
424 select CPU_32v7M
425 select CPU_ABRT_NOMMU
426 select CPU_CACHE_V7M
427 select CPU_CACHE_NOP
428 select CPU_PABRT_LEGACY
429 select CPU_THUMBONLY
430
431config CPU_THUMBONLY
432 bool
433 select CPU_THUMB_CAPABLE
434 # There are no CPUs available with MMU that don't implement an ARM ISA:
435 depends on !MMU
436 help
437 Select this if your CPU doesn't support the 32 bit ARM instructions.
438
439config CPU_THUMB_CAPABLE
440 bool
441 help
442 Select this if your CPU can support Thumb mode.
443
444# Figure out what processor architecture version we should be using.
445# This defines the compiler instruction set which depends on the machine type.
446config CPU_32v3
447 bool
448 select CPU_USE_DOMAINS if MMU
449 select NEED_KUSER_HELPERS
450 select TLS_REG_EMUL if SMP || !MMU
451 select CPU_NO_EFFICIENT_FFS
452
453config CPU_32v4
454 bool
455 select CPU_USE_DOMAINS if MMU
456 select NEED_KUSER_HELPERS
457 select TLS_REG_EMUL if SMP || !MMU
458 select CPU_NO_EFFICIENT_FFS
459
460config CPU_32v4T
461 bool
462 select CPU_USE_DOMAINS if MMU
463 select NEED_KUSER_HELPERS
464 select TLS_REG_EMUL if SMP || !MMU
465 select CPU_NO_EFFICIENT_FFS
466
467config CPU_32v5
468 bool
469 select CPU_USE_DOMAINS if MMU
470 select NEED_KUSER_HELPERS
471 select TLS_REG_EMUL if SMP || !MMU
472
473config CPU_32v6
474 bool
475 select TLS_REG_EMUL if !CPU_32v6K && !MMU
476
477config CPU_32v6K
478 bool
479
480config CPU_32v7
481 bool
482
483config CPU_32v7M
484 bool
485
486# The abort model
487config CPU_ABRT_NOMMU
488 bool
489
490config CPU_ABRT_EV4
491 bool
492
493config CPU_ABRT_EV4T
494 bool
495
496config CPU_ABRT_LV4T
497 bool
498
499config CPU_ABRT_EV5T
500 bool
501
502config CPU_ABRT_EV5TJ
503 bool
504
505config CPU_ABRT_EV6
506 bool
507
508config CPU_ABRT_EV7
509 bool
510
511config CPU_PABRT_LEGACY
512 bool
513
514config CPU_PABRT_V6
515 bool
516
517config CPU_PABRT_V7
518 bool
519
520# The cache model
521config CPU_CACHE_V4
522 bool
523
524config CPU_CACHE_V4WT
525 bool
526
527config CPU_CACHE_V4WB
528 bool
529
530config CPU_CACHE_V6
531 bool
532
533config CPU_CACHE_V7
534 bool
535
536config CPU_CACHE_NOP
537 bool
538
539config CPU_CACHE_VIVT
540 bool
541
542config CPU_CACHE_VIPT
543 bool
544
545config CPU_CACHE_FA
546 bool
547
548config CPU_CACHE_V7M
549 bool
550
551if MMU
552# The copy-page model
553config CPU_COPY_V4WT
554 bool
555
556config CPU_COPY_V4WB
557 bool
558
559config CPU_COPY_FEROCEON
560 bool
561
562config CPU_COPY_FA
563 bool
564
565config CPU_COPY_V6
566 bool
567
568# This selects the TLB model
569config CPU_TLB_V4WT
570 bool
571 help
572 ARM Architecture Version 4 TLB with writethrough cache.
573
574config CPU_TLB_V4WB
575 bool
576 help
577 ARM Architecture Version 4 TLB with writeback cache.
578
579config CPU_TLB_V4WBI
580 bool
581 help
582 ARM Architecture Version 4 TLB with writeback cache and invalidate
583 instruction cache entry.
584
585config CPU_TLB_FEROCEON
586 bool
587 help
588 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
589
590config CPU_TLB_FA
591 bool
592 help
593 Faraday ARM FA526 architecture, unified TLB with writeback cache
594 and invalidate instruction cache entry. Branch target buffer is
595 also supported.
596
597config CPU_TLB_V6
598 bool
599
600config CPU_TLB_V7
601 bool
602
603config VERIFY_PERMISSION_FAULT
604 bool
605endif
606
607config CPU_HAS_ASID
608 bool
609 help
610 This indicates whether the CPU has the ASID register; used to
611 tag TLB and possibly cache entries.
612
613config CPU_CP15
614 bool
615 help
616 Processor has the CP15 register.
617
618config CPU_CP15_MMU
619 bool
620 select CPU_CP15
621 help
622 Processor has the CP15 register, which has MMU related registers.
623
624config CPU_CP15_MPU
625 bool
626 select CPU_CP15
627 help
628 Processor has the CP15 register, which has MPU related registers.
629
630config CPU_USE_DOMAINS
631 bool
632 help
633 This option enables or disables the use of domain switching
634 via the set_fs() function.
635
636config CPU_V7M_NUM_IRQ
637 int "Number of external interrupts connected to the NVIC"
638 depends on CPU_V7M
639 default 90 if ARCH_STM32
640 default 38 if ARCH_EFM32
641 default 112 if SOC_VF610
642 default 240
643 help
644 This option indicates the number of interrupts connected to the NVIC.
645 The value can be larger than the real number of interrupts supported
646 by the system, but must not be lower.
647 The default value is 240, corresponding to the maximum number of
648 interrupts supported by the NVIC on Cortex-M family.
649
650 If unsure, keep default value.
651
652#
653# CPU supports 36-bit I/O
654#
655config IO_36
656 bool
657
658comment "Processor Features"
659
660config ARM_LPAE
661 bool "Support for the Large Physical Address Extension"
662 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
663 !CPU_32v4 && !CPU_32v3
664 help
665 Say Y if you have an ARMv7 processor supporting the LPAE page
666 table format and you would like to access memory beyond the
667 4GB limit. The resulting kernel image will not run on
668 processors without the LPA extension.
669
670 If unsure, say N.
671
672config ARM_PV_FIXUP
673 def_bool y
674 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
675
676config ARCH_PHYS_ADDR_T_64BIT
677 def_bool ARM_LPAE
678
679config ARCH_DMA_ADDR_T_64BIT
680 bool
681
682config ARM_THUMB
683 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
684 depends on CPU_THUMB_CAPABLE
685 default y
686 help
687 Say Y if you want to include kernel support for running user space
688 Thumb binaries.
689
690 The Thumb instruction set is a compressed form of the standard ARM
691 instruction set resulting in smaller binaries at the expense of
692 slightly less efficient code.
693
694 If this option is disabled, and you run userspace that switches to
695 Thumb mode, signal handling will not work correctly, resulting in
696 segmentation faults or illegal instruction aborts.
697
698 If you don't know what this all is, saying Y is a safe choice.
699
700config ARM_THUMBEE
701 bool "Enable ThumbEE CPU extension"
702 depends on CPU_V7
703 help
704 Say Y here if you have a CPU with the ThumbEE extension and code to
705 make use of it. Say N for code that can run on CPUs without ThumbEE.
706
707config ARM_VIRT_EXT
708 bool
709 depends on MMU
710 default y if CPU_V7
711 help
712 Enable the kernel to make use of the ARM Virtualization
713 Extensions to install hypervisors without run-time firmware
714 assistance.
715
716 A compliant bootloader is required in order to make maximum
717 use of this feature. Refer to Documentation/arm/Booting for
718 details.
719
720config SWP_EMULATE
721 bool "Emulate SWP/SWPB instructions" if !SMP
722 depends on CPU_V7
723 default y if SMP
724 select HAVE_PROC_CPU if PROC_FS
725 help
726 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
727 ARMv7 multiprocessing extensions introduce the ability to disable
728 these instructions, triggering an undefined instruction exception
729 when executed. Say Y here to enable software emulation of these
730 instructions for userspace (not kernel) using LDREX/STREX.
731 Also creates /proc/cpu/swp_emulation for statistics.
732
733 In some older versions of glibc [<=2.8] SWP is used during futex
734 trylock() operations with the assumption that the code will not
735 be preempted. This invalid assumption may be more likely to fail
736 with SWP emulation enabled, leading to deadlock of the user
737 application.
738
739 NOTE: when accessing uncached shared regions, LDREX/STREX rely
740 on an external transaction monitoring block called a global
741 monitor to maintain update atomicity. If your system does not
742 implement a global monitor, this option can cause programs that
743 perform SWP operations to uncached memory to deadlock.
744
745 If unsure, say Y.
746
747config CPU_BIG_ENDIAN
748 bool "Build big-endian kernel"
749 depends on ARCH_SUPPORTS_BIG_ENDIAN
750 help
751 Say Y if you plan on running a kernel in big-endian mode.
752 Note that your board must be properly built and your board
753 port must properly enable any big-endian related features
754 of your chipset/board/processor.
755
756config CPU_ENDIAN_BE8
757 bool
758 depends on CPU_BIG_ENDIAN
759 default CPU_V6 || CPU_V6K || CPU_V7
760 help
761 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
762
763config CPU_ENDIAN_BE32
764 bool
765 depends on CPU_BIG_ENDIAN
766 default !CPU_ENDIAN_BE8
767 help
768 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
769
770config CPU_HIGH_VECTOR
771 depends on !MMU && CPU_CP15 && !CPU_ARM740T
772 bool "Select the High exception vector"
773 help
774 Say Y here to select high exception vector(0xFFFF0000~).
775 The exception vector can vary depending on the platform
776 design in nommu mode. If your platform needs to select
777 high exception vector, say Y.
778 Otherwise or if you are unsure, say N, and the low exception
779 vector (0x00000000~) will be used.
780
781config CPU_ICACHE_DISABLE
782 bool "Disable I-Cache (I-bit)"
783 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
784 help
785 Say Y here to disable the processor instruction cache. Unless
786 you have a reason not to or are unsure, say N.
787
788config CPU_DCACHE_DISABLE
789 bool "Disable D-Cache (C-bit)"
790 depends on (CPU_CP15 && !SMP) || CPU_V7M
791 help
792 Say Y here to disable the processor data cache. Unless
793 you have a reason not to or are unsure, say N.
794
795config CPU_DCACHE_SIZE
796 hex
797 depends on CPU_ARM740T || CPU_ARM946E
798 default 0x00001000 if CPU_ARM740T
799 default 0x00002000 # default size for ARM946E-S
800 help
801 Some cores are synthesizable to have various sized cache. For
802 ARM946E-S case, it can vary from 0KB to 1MB.
803 To support such cache operations, it is efficient to know the size
804 before compile time.
805 If your SoC is configured to have a different size, define the value
806 here with proper conditions.
807
808config CPU_DCACHE_WRITETHROUGH
809 bool "Force write through D-cache"
810 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
811 default y if CPU_ARM925T
812 help
813 Say Y here to use the data cache in writethrough mode. Unless you
814 specifically require this or are unsure, say N.
815
816config CPU_CACHE_ROUND_ROBIN
817 bool "Round robin I and D cache replacement algorithm"
818 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
819 help
820 Say Y here to use the predictable round-robin cache replacement
821 policy. Unless you specifically require this or are unsure, say N.
822
823config CPU_BPREDICT_DISABLE
824 bool "Disable branch prediction"
825 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
826 help
827 Say Y here to disable branch prediction. If unsure, say N.
828
829config TLS_REG_EMUL
830 bool
831 select NEED_KUSER_HELPERS
832 help
833 An SMP system using a pre-ARMv6 processor (there are apparently
834 a few prototypes like that in existence) and therefore access to
835 that required register must be emulated.
836
837config NEED_KUSER_HELPERS
838 bool
839
840config KUSER_HELPERS
841 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
842 depends on MMU
843 default y
844 help
845 Warning: disabling this option may break user programs.
846
847 Provide kuser helpers in the vector page. The kernel provides
848 helper code to userspace in read only form at a fixed location
849 in the high vector page to allow userspace to be independent of
850 the CPU type fitted to the system. This permits binaries to be
851 run on ARMv4 through to ARMv7 without modification.
852
853 See Documentation/arm/kernel_user_helpers.txt for details.
854
855 However, the fixed address nature of these helpers can be used
856 by ROP (return orientated programming) authors when creating
857 exploits.
858
859 If all of the binaries and libraries which run on your platform
860 are built specifically for your platform, and make no use of
861 these helpers, then you can turn this option off to hinder
862 such exploits. However, in that case, if a binary or library
863 relying on those helpers is run, it will receive a SIGILL signal,
864 which will terminate the program.
865
866 Say N here only if you are absolutely certain that you do not
867 need these helpers; otherwise, the safe option is to say Y.
868
869config VDSO
870 bool "Enable VDSO for acceleration of some system calls"
871 depends on AEABI && MMU && CPU_V7
872 default y if ARM_ARCH_TIMER
873 select GENERIC_TIME_VSYSCALL
874 help
875 Place in the process address space an ELF shared object
876 providing fast implementations of gettimeofday and
877 clock_gettime. Systems that implement the ARM architected
878 timer will receive maximum benefit.
879
880 You must have glibc 2.22 or later for programs to seamlessly
881 take advantage of this.
882
883config DMA_CACHE_RWFO
884 bool "Enable read/write for ownership DMA cache maintenance"
885 depends on CPU_V6K && SMP
886 default y
887 help
888 The Snoop Control Unit on ARM11MPCore does not detect the
889 cache maintenance operations and the dma_{map,unmap}_area()
890 functions may leave stale cache entries on other CPUs. By
891 enabling this option, Read or Write For Ownership in the ARMv6
892 DMA cache maintenance functions is performed. These LDR/STR
893 instructions change the cache line state to shared or modified
894 so that the cache operation has the desired effect.
895
896 Note that the workaround is only valid on processors that do
897 not perform speculative loads into the D-cache. For such
898 processors, if cache maintenance operations are not broadcast
899 in hardware, other workarounds are needed (e.g. cache
900 maintenance broadcasting in software via FIQ).
901
902config OUTER_CACHE
903 bool
904
905config OUTER_CACHE_SYNC
906 bool
907 select ARM_HEAVY_MB
908 help
909 The outer cache has a outer_cache_fns.sync function pointer
910 that can be used to drain the write buffer of the outer cache.
911
912config CACHE_B15_RAC
913 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
914 depends on ARCH_BRCMSTB
915 default y
916 help
917 This option enables the Broadcom Brahma-B15 read-ahead cache
918 controller. If disabled, the read-ahead cache remains off.
919
920config CACHE_FEROCEON_L2
921 bool "Enable the Feroceon L2 cache controller"
922 depends on ARCH_MV78XX0 || ARCH_MVEBU
923 default y
924 select OUTER_CACHE
925 help
926 This option enables the Feroceon L2 cache controller.
927
928config CACHE_FEROCEON_L2_WRITETHROUGH
929 bool "Force Feroceon L2 cache write through"
930 depends on CACHE_FEROCEON_L2
931 help
932 Say Y here to use the Feroceon L2 cache in writethrough mode.
933 Unless you specifically require this, say N for writeback mode.
934
935config MIGHT_HAVE_CACHE_L2X0
936 bool
937 help
938 This option should be selected by machines which have a L2x0
939 or PL310 cache controller, but where its use is optional.
940
941 The only effect of this option is to make CACHE_L2X0 and
942 related options available to the user for configuration.
943
944 Boards or SoCs which always require the cache controller
945 support to be present should select CACHE_L2X0 directly
946 instead of this option, thus preventing the user from
947 inadvertently configuring a broken kernel.
948
949config CACHE_L2X0
950 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
951 default MIGHT_HAVE_CACHE_L2X0
952 select OUTER_CACHE
953 select OUTER_CACHE_SYNC
954 help
955 This option enables the L2x0 PrimeCell.
956
957config CACHE_L2X0_PMU
958 bool "L2x0 performance monitor support" if CACHE_L2X0
959 depends on PERF_EVENTS
960 help
961 This option enables support for the performance monitoring features
962 of the L220 and PL310 outer cache controllers.
963
964if CACHE_L2X0
965
966config PL310_ERRATA_588369
967 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
968 help
969 The PL310 L2 cache controller implements three types of Clean &
970 Invalidate maintenance operations: by Physical Address
971 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
972 They are architecturally defined to behave as the execution of a
973 clean operation followed immediately by an invalidate operation,
974 both performing to the same memory location. This functionality
975 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
976 as clean lines are not invalidated as a result of these operations.
977
978config PL310_ERRATA_727915
979 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
980 help
981 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
982 operation (offset 0x7FC). This operation runs in background so that
983 PL310 can handle normal accesses while it is in progress. Under very
984 rare circumstances, due to this erratum, write data can be lost when
985 PL310 treats a cacheable write transaction during a Clean &
986 Invalidate by Way operation. Revisions prior to r3p1 are affected by
987 this errata (fixed in r3p1).
988
989config PL310_ERRATA_753970
990 bool "PL310 errata: cache sync operation may be faulty"
991 help
992 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
993
994 Under some condition the effect of cache sync operation on
995 the store buffer still remains when the operation completes.
996 This means that the store buffer is always asked to drain and
997 this prevents it from merging any further writes. The workaround
998 is to replace the normal offset of cache sync operation (0x730)
999 by another offset targeting an unmapped PL310 register 0x740.
1000 This has the same effect as the cache sync operation: store buffer
1001 drain and waiting for all buffers empty.
1002
1003config PL310_ERRATA_769419
1004 bool "PL310 errata: no automatic Store Buffer drain"
1005 help
1006 On revisions of the PL310 prior to r3p2, the Store Buffer does
1007 not automatically drain. This can cause normal, non-cacheable
1008 writes to be retained when the memory system is idle, leading
1009 to suboptimal I/O performance for drivers using coherent DMA.
1010 This option adds a write barrier to the cpu_idle loop so that,
1011 on systems with an outer cache, the store buffer is drained
1012 explicitly.
1013
1014endif
1015
1016config CACHE_TAUROS2
1017 bool "Enable the Tauros2 L2 cache controller"
1018 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
1019 default y
1020 select OUTER_CACHE
1021 help
1022 This option enables the Tauros2 L2 cache controller (as
1023 found on PJ1/PJ4).
1024
1025config CACHE_UNIPHIER
1026 bool "Enable the UniPhier outer cache controller"
1027 depends on ARCH_UNIPHIER
1028 select ARM_L1_CACHE_SHIFT_7
1029 select OUTER_CACHE
1030 select OUTER_CACHE_SYNC
1031 help
1032 This option enables the UniPhier outer cache (system cache)
1033 controller.
1034
1035config CACHE_XSC3L2
1036 bool "Enable the L2 cache on XScale3"
1037 depends on CPU_XSC3
1038 default y
1039 select OUTER_CACHE
1040 help
1041 This option enables the L2 cache on XScale3.
1042
1043config ARM_L1_CACHE_SHIFT_6
1044 bool
1045 default y if CPU_V7
1046 help
1047 Setting ARM L1 cache line size to 64 Bytes.
1048
1049config ARM_L1_CACHE_SHIFT_7
1050 bool
1051 help
1052 Setting ARM L1 cache line size to 128 Bytes.
1053
1054config ARM_L1_CACHE_SHIFT
1055 int
1056 default 7 if ARM_L1_CACHE_SHIFT_7
1057 default 6 if ARM_L1_CACHE_SHIFT_6
1058 default 5
1059
1060config ARM_DMA_MEM_BUFFERABLE
1061 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1062 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1063 help
1064 Historically, the kernel has used strongly ordered mappings to
1065 provide DMA coherent memory. With the advent of ARMv7, mapping
1066 memory with differing types results in unpredictable behaviour,
1067 so on these CPUs, this option is forced on.
1068
1069 Multiple mappings with differing attributes is also unpredictable
1070 on ARMv6 CPUs, but since they do not have aggressive speculative
1071 prefetch, no harm appears to occur.
1072
1073 However, drivers may be missing the necessary barriers for ARMv6,
1074 and therefore turning this on may result in unpredictable driver
1075 behaviour. Therefore, we offer this as an option.
1076
1077 On some of the beefier ARMv7-M machines (with DMA and write
1078 buffers) you likely want this enabled, while those that
1079 didn't need it until now also won't need it in the future.
1080
1081 You are recommended say 'Y' here and debug any affected drivers.
1082
1083config ARM_HEAVY_MB
1084 bool
1085
1086config ARCH_SUPPORTS_BIG_ENDIAN
1087 bool
1088 help
1089 This option specifies the architecture can support big endian
1090 operation.
1091
1092config DEBUG_ALIGN_RODATA
1093 bool "Make rodata strictly non-executable"
1094 depends on STRICT_KERNEL_RWX
1095 default y
1096 help
1097 If this is set, rodata will be made explicitly non-executable. This
1098 provides protection on the rare chance that attackers might find and
1099 use ROP gadgets that exist in the rodata section. This adds an
1100 additional section-aligned split of rodata from kernel text so it
1101 can be made explicitly non-executable. This padding may waste memory
1102 space to gain the additional protection.
1comment "Processor Type"
2
3# Select CPU types depending on the architecture selected. This selects
4# which CPUs we support in the kernel image, and the compiler instruction
5# optimiser behaviour.
6
7# ARM7TDMI
8config CPU_ARM7TDMI
9 bool "Support ARM7TDMI processor"
10 depends on !MMU
11 select CPU_32v4T
12 select CPU_ABRT_LV4T
13 select CPU_CACHE_V4
14 select CPU_PABRT_LEGACY
15 help
16 A 32-bit RISC microprocessor based on the ARM7 processor core
17 which has no memory control unit and cache.
18
19 Say Y if you want support for the ARM7TDMI processor.
20 Otherwise, say N.
21
22# ARM720T
23config CPU_ARM720T
24 bool "Support ARM720T processor" if ARCH_INTEGRATOR
25 select CPU_32v4T
26 select CPU_ABRT_LV4T
27 select CPU_CACHE_V4
28 select CPU_CACHE_VIVT
29 select CPU_COPY_V4WT if MMU
30 select CPU_CP15_MMU
31 select CPU_PABRT_LEGACY
32 select CPU_TLB_V4WT if MMU
33 help
34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
35 MMU built around an ARM7TDMI core.
36
37 Say Y if you want support for the ARM720T processor.
38 Otherwise, say N.
39
40# ARM740T
41config CPU_ARM740T
42 bool "Support ARM740T processor" if ARCH_INTEGRATOR
43 depends on !MMU
44 select CPU_32v4T
45 select CPU_ABRT_LV4T
46 select CPU_CACHE_V4
47 select CPU_CP15_MPU
48 select CPU_PABRT_LEGACY
49 help
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
51 write buffer and MPU(Protection Unit) built around
52 an ARM7TDMI core.
53
54 Say Y if you want support for the ARM740T processor.
55 Otherwise, say N.
56
57# ARM9TDMI
58config CPU_ARM9TDMI
59 bool "Support ARM9TDMI processor"
60 depends on !MMU
61 select CPU_32v4T
62 select CPU_ABRT_NOMMU
63 select CPU_CACHE_V4
64 select CPU_PABRT_LEGACY
65 help
66 A 32-bit RISC microprocessor based on the ARM9 processor core
67 which has no memory control unit and cache.
68
69 Say Y if you want support for the ARM9TDMI processor.
70 Otherwise, say N.
71
72# ARM920T
73config CPU_ARM920T
74 bool "Support ARM920T processor" if ARCH_INTEGRATOR
75 select CPU_32v4T
76 select CPU_ABRT_EV4T
77 select CPU_CACHE_V4WT
78 select CPU_CACHE_VIVT
79 select CPU_COPY_V4WB if MMU
80 select CPU_CP15_MMU
81 select CPU_PABRT_LEGACY
82 select CPU_TLB_V4WBI if MMU
83 help
84 The ARM920T is licensed to be produced by numerous vendors,
85 and is used in the Cirrus EP93xx and the Samsung S3C2410.
86
87 Say Y if you want support for the ARM920T processor.
88 Otherwise, say N.
89
90# ARM922T
91config CPU_ARM922T
92 bool "Support ARM922T processor" if ARCH_INTEGRATOR
93 select CPU_32v4T
94 select CPU_ABRT_EV4T
95 select CPU_CACHE_V4WT
96 select CPU_CACHE_VIVT
97 select CPU_COPY_V4WB if MMU
98 select CPU_CP15_MMU
99 select CPU_PABRT_LEGACY
100 select CPU_TLB_V4WBI if MMU
101 help
102 The ARM922T is a version of the ARM920T, but with smaller
103 instruction and data caches. It is used in Altera's
104 Excalibur XA device family and Micrel's KS8695 Centaur.
105
106 Say Y if you want support for the ARM922T processor.
107 Otherwise, say N.
108
109# ARM925T
110config CPU_ARM925T
111 bool "Support ARM925T processor" if ARCH_OMAP1
112 select CPU_32v4T
113 select CPU_ABRT_EV4T
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
116 select CPU_COPY_V4WB if MMU
117 select CPU_CP15_MMU
118 select CPU_PABRT_LEGACY
119 select CPU_TLB_V4WBI if MMU
120 help
121 The ARM925T is a mix between the ARM920T and ARM926T, but with
122 different instruction and data caches. It is used in TI's OMAP
123 device family.
124
125 Say Y if you want support for the ARM925T processor.
126 Otherwise, say N.
127
128# ARM926T
129config CPU_ARM926T
130 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
131 select CPU_32v5
132 select CPU_ABRT_EV5TJ
133 select CPU_CACHE_VIVT
134 select CPU_COPY_V4WB if MMU
135 select CPU_CP15_MMU
136 select CPU_PABRT_LEGACY
137 select CPU_TLB_V4WBI if MMU
138 help
139 This is a variant of the ARM920. It has slightly different
140 instruction sequences for cache and TLB operations. Curiously,
141 there is no documentation on it at the ARM corporate website.
142
143 Say Y if you want support for the ARM926T processor.
144 Otherwise, say N.
145
146# FA526
147config CPU_FA526
148 bool
149 select CPU_32v4
150 select CPU_ABRT_EV4
151 select CPU_CACHE_FA
152 select CPU_CACHE_VIVT
153 select CPU_COPY_FA if MMU
154 select CPU_CP15_MMU
155 select CPU_PABRT_LEGACY
156 select CPU_TLB_FA if MMU
157 help
158 The FA526 is a version of the ARMv4 compatible processor with
159 Branch Target Buffer, Unified TLB and cache line size 16.
160
161 Say Y if you want support for the FA526 processor.
162 Otherwise, say N.
163
164# ARM940T
165config CPU_ARM940T
166 bool "Support ARM940T processor" if ARCH_INTEGRATOR
167 depends on !MMU
168 select CPU_32v4T
169 select CPU_ABRT_NOMMU
170 select CPU_CACHE_VIVT
171 select CPU_CP15_MPU
172 select CPU_PABRT_LEGACY
173 help
174 ARM940T is a member of the ARM9TDMI family of general-
175 purpose microprocessors with MPU and separate 4KB
176 instruction and 4KB data cases, each with a 4-word line
177 length.
178
179 Say Y if you want support for the ARM940T processor.
180 Otherwise, say N.
181
182# ARM946E-S
183config CPU_ARM946E
184 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
185 depends on !MMU
186 select CPU_32v5
187 select CPU_ABRT_NOMMU
188 select CPU_CACHE_VIVT
189 select CPU_CP15_MPU
190 select CPU_PABRT_LEGACY
191 help
192 ARM946E-S is a member of the ARM9E-S family of high-
193 performance, 32-bit system-on-chip processor solutions.
194 The TCM and ARMv5TE 32-bit instruction set is supported.
195
196 Say Y if you want support for the ARM946E-S processor.
197 Otherwise, say N.
198
199# ARM1020 - needs validating
200config CPU_ARM1020
201 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
202 select CPU_32v5
203 select CPU_ABRT_EV4T
204 select CPU_CACHE_V4WT
205 select CPU_CACHE_VIVT
206 select CPU_COPY_V4WB if MMU
207 select CPU_CP15_MMU
208 select CPU_PABRT_LEGACY
209 select CPU_TLB_V4WBI if MMU
210 help
211 The ARM1020 is the 32K cached version of the ARM10 processor,
212 with an addition of a floating-point unit.
213
214 Say Y if you want support for the ARM1020 processor.
215 Otherwise, say N.
216
217# ARM1020E - needs validating
218config CPU_ARM1020E
219 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
220 depends on n
221 select CPU_32v5
222 select CPU_ABRT_EV4T
223 select CPU_CACHE_V4WT
224 select CPU_CACHE_VIVT
225 select CPU_COPY_V4WB if MMU
226 select CPU_CP15_MMU
227 select CPU_PABRT_LEGACY
228 select CPU_TLB_V4WBI if MMU
229
230# ARM1022E
231config CPU_ARM1022
232 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
233 select CPU_32v5
234 select CPU_ABRT_EV4T
235 select CPU_CACHE_VIVT
236 select CPU_COPY_V4WB if MMU # can probably do better
237 select CPU_CP15_MMU
238 select CPU_PABRT_LEGACY
239 select CPU_TLB_V4WBI if MMU
240 help
241 The ARM1022E is an implementation of the ARMv5TE architecture
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243 embedded trace macrocell, and a floating-point unit.
244
245 Say Y if you want support for the ARM1022E processor.
246 Otherwise, say N.
247
248# ARM1026EJ-S
249config CPU_ARM1026
250 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
251 select CPU_32v5
252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253 select CPU_CACHE_VIVT
254 select CPU_COPY_V4WB if MMU # can probably do better
255 select CPU_CP15_MMU
256 select CPU_PABRT_LEGACY
257 select CPU_TLB_V4WBI if MMU
258 help
259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260 based upon the ARM10 integer core.
261
262 Say Y if you want support for the ARM1026EJ-S processor.
263 Otherwise, say N.
264
265# SA110
266config CPU_SA110
267 bool
268 select CPU_32v3 if ARCH_RPC
269 select CPU_32v4 if !ARCH_RPC
270 select CPU_ABRT_EV4
271 select CPU_CACHE_V4WB
272 select CPU_CACHE_VIVT
273 select CPU_COPY_V4WB if MMU
274 select CPU_CP15_MMU
275 select CPU_PABRT_LEGACY
276 select CPU_TLB_V4WB if MMU
277 help
278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279 is available at five speeds ranging from 100 MHz to 233 MHz.
280 More information is available at
281 <http://developer.intel.com/design/strong/sa110.htm>.
282
283 Say Y if you want support for the SA-110 processor.
284 Otherwise, say N.
285
286# SA1100
287config CPU_SA1100
288 bool
289 select CPU_32v4
290 select CPU_ABRT_EV4
291 select CPU_CACHE_V4WB
292 select CPU_CACHE_VIVT
293 select CPU_CP15_MMU
294 select CPU_PABRT_LEGACY
295 select CPU_TLB_V4WB if MMU
296
297# XScale
298config CPU_XSCALE
299 bool
300 select CPU_32v5
301 select CPU_ABRT_EV5T
302 select CPU_CACHE_VIVT
303 select CPU_CP15_MMU
304 select CPU_PABRT_LEGACY
305 select CPU_TLB_V4WBI if MMU
306
307# XScale Core Version 3
308config CPU_XSC3
309 bool
310 select CPU_32v5
311 select CPU_ABRT_EV5T
312 select CPU_CACHE_VIVT
313 select CPU_CP15_MMU
314 select CPU_PABRT_LEGACY
315 select CPU_TLB_V4WBI if MMU
316 select IO_36
317
318# Marvell PJ1 (Mohawk)
319config CPU_MOHAWK
320 bool
321 select CPU_32v5
322 select CPU_ABRT_EV5T
323 select CPU_CACHE_VIVT
324 select CPU_COPY_V4WB if MMU
325 select CPU_CP15_MMU
326 select CPU_PABRT_LEGACY
327 select CPU_TLB_V4WBI if MMU
328
329# Feroceon
330config CPU_FEROCEON
331 bool
332 select CPU_32v5
333 select CPU_ABRT_EV5T
334 select CPU_CACHE_VIVT
335 select CPU_COPY_FEROCEON if MMU
336 select CPU_CP15_MMU
337 select CPU_PABRT_LEGACY
338 select CPU_TLB_FEROCEON if MMU
339
340config CPU_FEROCEON_OLD_ID
341 bool "Accept early Feroceon cores with an ARM926 ID"
342 depends on CPU_FEROCEON && !CPU_ARM926T
343 default y
344 help
345 This enables the usage of some old Feroceon cores
346 for which the CPU ID is equal to the ARM926 ID.
347 Relevant for Feroceon-1850 and early Feroceon-2850.
348
349# Marvell PJ4
350config CPU_PJ4
351 bool
352 select ARM_THUMBEE
353 select CPU_V7
354
355config CPU_PJ4B
356 bool
357 select CPU_V7
358
359# ARMv6
360config CPU_V6
361 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
362 select CPU_32v6
363 select CPU_ABRT_EV6
364 select CPU_CACHE_V6
365 select CPU_CACHE_VIPT
366 select CPU_COPY_V6 if MMU
367 select CPU_CP15_MMU
368 select CPU_HAS_ASID if MMU
369 select CPU_PABRT_V6
370 select CPU_TLB_V6 if MMU
371
372# ARMv6k
373config CPU_V6K
374 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
375 select CPU_32v6
376 select CPU_32v6K
377 select CPU_ABRT_EV6
378 select CPU_CACHE_V6
379 select CPU_CACHE_VIPT
380 select CPU_COPY_V6 if MMU
381 select CPU_CP15_MMU
382 select CPU_HAS_ASID if MMU
383 select CPU_PABRT_V6
384 select CPU_TLB_V6 if MMU
385
386# ARMv7
387config CPU_V7
388 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
389 select CPU_32v6K
390 select CPU_32v7
391 select CPU_ABRT_EV7
392 select CPU_CACHE_V7
393 select CPU_CACHE_VIPT
394 select CPU_COPY_V6 if MMU
395 select CPU_CP15_MMU if MMU
396 select CPU_CP15_MPU if !MMU
397 select CPU_HAS_ASID if MMU
398 select CPU_PABRT_V7
399 select CPU_TLB_V7 if MMU
400
401# ARMv7M
402config CPU_V7M
403 bool
404 select CPU_32v7M
405 select CPU_ABRT_NOMMU
406 select CPU_CACHE_NOP
407 select CPU_PABRT_LEGACY
408 select CPU_THUMBONLY
409
410config CPU_THUMBONLY
411 bool
412 # There are no CPUs available with MMU that don't implement an ARM ISA:
413 depends on !MMU
414 help
415 Select this if your CPU doesn't support the 32 bit ARM instructions.
416
417# Figure out what processor architecture version we should be using.
418# This defines the compiler instruction set which depends on the machine type.
419config CPU_32v3
420 bool
421 select CPU_USE_DOMAINS if MMU
422 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
423 select NEED_KUSER_HELPERS
424 select TLS_REG_EMUL if SMP || !MMU
425
426config CPU_32v4
427 bool
428 select CPU_USE_DOMAINS if MMU
429 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
430 select NEED_KUSER_HELPERS
431 select TLS_REG_EMUL if SMP || !MMU
432
433config CPU_32v4T
434 bool
435 select CPU_USE_DOMAINS if MMU
436 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
437 select NEED_KUSER_HELPERS
438 select TLS_REG_EMUL if SMP || !MMU
439
440config CPU_32v5
441 bool
442 select CPU_USE_DOMAINS if MMU
443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select NEED_KUSER_HELPERS
445 select TLS_REG_EMUL if SMP || !MMU
446
447config CPU_32v6
448 bool
449 select TLS_REG_EMUL if !CPU_32v6K && !MMU
450
451config CPU_32v6K
452 bool
453
454config CPU_32v7
455 bool
456
457config CPU_32v7M
458 bool
459
460# The abort model
461config CPU_ABRT_NOMMU
462 bool
463
464config CPU_ABRT_EV4
465 bool
466
467config CPU_ABRT_EV4T
468 bool
469
470config CPU_ABRT_LV4T
471 bool
472
473config CPU_ABRT_EV5T
474 bool
475
476config CPU_ABRT_EV5TJ
477 bool
478
479config CPU_ABRT_EV6
480 bool
481
482config CPU_ABRT_EV7
483 bool
484
485config CPU_PABRT_LEGACY
486 bool
487
488config CPU_PABRT_V6
489 bool
490
491config CPU_PABRT_V7
492 bool
493
494# The cache model
495config CPU_CACHE_V4
496 bool
497
498config CPU_CACHE_V4WT
499 bool
500
501config CPU_CACHE_V4WB
502 bool
503
504config CPU_CACHE_V6
505 bool
506
507config CPU_CACHE_V7
508 bool
509
510config CPU_CACHE_NOP
511 bool
512
513config CPU_CACHE_VIVT
514 bool
515
516config CPU_CACHE_VIPT
517 bool
518
519config CPU_CACHE_FA
520 bool
521
522if MMU
523# The copy-page model
524config CPU_COPY_V4WT
525 bool
526
527config CPU_COPY_V4WB
528 bool
529
530config CPU_COPY_FEROCEON
531 bool
532
533config CPU_COPY_FA
534 bool
535
536config CPU_COPY_V6
537 bool
538
539# This selects the TLB model
540config CPU_TLB_V4WT
541 bool
542 help
543 ARM Architecture Version 4 TLB with writethrough cache.
544
545config CPU_TLB_V4WB
546 bool
547 help
548 ARM Architecture Version 4 TLB with writeback cache.
549
550config CPU_TLB_V4WBI
551 bool
552 help
553 ARM Architecture Version 4 TLB with writeback cache and invalidate
554 instruction cache entry.
555
556config CPU_TLB_FEROCEON
557 bool
558 help
559 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
560
561config CPU_TLB_FA
562 bool
563 help
564 Faraday ARM FA526 architecture, unified TLB with writeback cache
565 and invalidate instruction cache entry. Branch target buffer is
566 also supported.
567
568config CPU_TLB_V6
569 bool
570
571config CPU_TLB_V7
572 bool
573
574config VERIFY_PERMISSION_FAULT
575 bool
576endif
577
578config CPU_HAS_ASID
579 bool
580 help
581 This indicates whether the CPU has the ASID register; used to
582 tag TLB and possibly cache entries.
583
584config CPU_CP15
585 bool
586 help
587 Processor has the CP15 register.
588
589config CPU_CP15_MMU
590 bool
591 select CPU_CP15
592 help
593 Processor has the CP15 register, which has MMU related registers.
594
595config CPU_CP15_MPU
596 bool
597 select CPU_CP15
598 help
599 Processor has the CP15 register, which has MPU related registers.
600
601config CPU_USE_DOMAINS
602 bool
603 help
604 This option enables or disables the use of domain switching
605 via the set_fs() function.
606
607#
608# CPU supports 36-bit I/O
609#
610config IO_36
611 bool
612
613comment "Processor Features"
614
615config ARM_LPAE
616 bool "Support for the Large Physical Address Extension"
617 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
618 !CPU_32v4 && !CPU_32v3
619 help
620 Say Y if you have an ARMv7 processor supporting the LPAE page
621 table format and you would like to access memory beyond the
622 4GB limit. The resulting kernel image will not run on
623 processors without the LPA extension.
624
625 If unsure, say N.
626
627config ARCH_PHYS_ADDR_T_64BIT
628 def_bool ARM_LPAE
629
630config ARCH_DMA_ADDR_T_64BIT
631 bool
632
633config ARM_THUMB
634 bool "Support Thumb user binaries" if !CPU_THUMBONLY
635 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
636 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
637 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
638 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
639 CPU_V7 || CPU_FEROCEON || CPU_V7M
640 default y
641 help
642 Say Y if you want to include kernel support for running user space
643 Thumb binaries.
644
645 The Thumb instruction set is a compressed form of the standard ARM
646 instruction set resulting in smaller binaries at the expense of
647 slightly less efficient code.
648
649 If you don't know what this all is, saying Y is a safe choice.
650
651config ARM_THUMBEE
652 bool "Enable ThumbEE CPU extension"
653 depends on CPU_V7
654 help
655 Say Y here if you have a CPU with the ThumbEE extension and code to
656 make use of it. Say N for code that can run on CPUs without ThumbEE.
657
658config ARM_VIRT_EXT
659 bool
660 depends on MMU
661 default y if CPU_V7
662 help
663 Enable the kernel to make use of the ARM Virtualization
664 Extensions to install hypervisors without run-time firmware
665 assistance.
666
667 A compliant bootloader is required in order to make maximum
668 use of this feature. Refer to Documentation/arm/Booting for
669 details.
670
671config SWP_EMULATE
672 bool "Emulate SWP/SWPB instructions"
673 depends on CPU_V7
674 default y if SMP
675 select HAVE_PROC_CPU if PROC_FS
676 help
677 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
678 ARMv7 multiprocessing extensions introduce the ability to disable
679 these instructions, triggering an undefined instruction exception
680 when executed. Say Y here to enable software emulation of these
681 instructions for userspace (not kernel) using LDREX/STREX.
682 Also creates /proc/cpu/swp_emulation for statistics.
683
684 In some older versions of glibc [<=2.8] SWP is used during futex
685 trylock() operations with the assumption that the code will not
686 be preempted. This invalid assumption may be more likely to fail
687 with SWP emulation enabled, leading to deadlock of the user
688 application.
689
690 NOTE: when accessing uncached shared regions, LDREX/STREX rely
691 on an external transaction monitoring block called a global
692 monitor to maintain update atomicity. If your system does not
693 implement a global monitor, this option can cause programs that
694 perform SWP operations to uncached memory to deadlock.
695
696 If unsure, say Y.
697
698config CPU_BIG_ENDIAN
699 bool "Build big-endian kernel"
700 depends on ARCH_SUPPORTS_BIG_ENDIAN
701 help
702 Say Y if you plan on running a kernel in big-endian mode.
703 Note that your board must be properly built and your board
704 port must properly enable any big-endian related features
705 of your chipset/board/processor.
706
707config CPU_ENDIAN_BE8
708 bool
709 depends on CPU_BIG_ENDIAN
710 default CPU_V6 || CPU_V6K || CPU_V7
711 help
712 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
713
714config CPU_ENDIAN_BE32
715 bool
716 depends on CPU_BIG_ENDIAN
717 default !CPU_ENDIAN_BE8
718 help
719 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
720
721config CPU_HIGH_VECTOR
722 depends on !MMU && CPU_CP15 && !CPU_ARM740T
723 bool "Select the High exception vector"
724 help
725 Say Y here to select high exception vector(0xFFFF0000~).
726 The exception vector can vary depending on the platform
727 design in nommu mode. If your platform needs to select
728 high exception vector, say Y.
729 Otherwise or if you are unsure, say N, and the low exception
730 vector (0x00000000~) will be used.
731
732config CPU_ICACHE_DISABLE
733 bool "Disable I-Cache (I-bit)"
734 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
735 help
736 Say Y here to disable the processor instruction cache. Unless
737 you have a reason not to or are unsure, say N.
738
739config CPU_DCACHE_DISABLE
740 bool "Disable D-Cache (C-bit)"
741 depends on CPU_CP15
742 help
743 Say Y here to disable the processor data cache. Unless
744 you have a reason not to or are unsure, say N.
745
746config CPU_DCACHE_SIZE
747 hex
748 depends on CPU_ARM740T || CPU_ARM946E
749 default 0x00001000 if CPU_ARM740T
750 default 0x00002000 # default size for ARM946E-S
751 help
752 Some cores are synthesizable to have various sized cache. For
753 ARM946E-S case, it can vary from 0KB to 1MB.
754 To support such cache operations, it is efficient to know the size
755 before compile time.
756 If your SoC is configured to have a different size, define the value
757 here with proper conditions.
758
759config CPU_DCACHE_WRITETHROUGH
760 bool "Force write through D-cache"
761 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
762 default y if CPU_ARM925T
763 help
764 Say Y here to use the data cache in writethrough mode. Unless you
765 specifically require this or are unsure, say N.
766
767config CPU_CACHE_ROUND_ROBIN
768 bool "Round robin I and D cache replacement algorithm"
769 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
770 help
771 Say Y here to use the predictable round-robin cache replacement
772 policy. Unless you specifically require this or are unsure, say N.
773
774config CPU_BPREDICT_DISABLE
775 bool "Disable branch prediction"
776 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
777 help
778 Say Y here to disable branch prediction. If unsure, say N.
779
780config TLS_REG_EMUL
781 bool
782 select NEED_KUSER_HELPERS
783 help
784 An SMP system using a pre-ARMv6 processor (there are apparently
785 a few prototypes like that in existence) and therefore access to
786 that required register must be emulated.
787
788config NEEDS_SYSCALL_FOR_CMPXCHG
789 bool
790 select NEED_KUSER_HELPERS
791 help
792 SMP on a pre-ARMv6 processor? Well OK then.
793 Forget about fast user space cmpxchg support.
794 It is just not possible.
795
796config NEED_KUSER_HELPERS
797 bool
798
799config KUSER_HELPERS
800 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
801 default y
802 help
803 Warning: disabling this option may break user programs.
804
805 Provide kuser helpers in the vector page. The kernel provides
806 helper code to userspace in read only form at a fixed location
807 in the high vector page to allow userspace to be independent of
808 the CPU type fitted to the system. This permits binaries to be
809 run on ARMv4 through to ARMv7 without modification.
810
811 See Documentation/arm/kernel_user_helpers.txt for details.
812
813 However, the fixed address nature of these helpers can be used
814 by ROP (return orientated programming) authors when creating
815 exploits.
816
817 If all of the binaries and libraries which run on your platform
818 are built specifically for your platform, and make no use of
819 these helpers, then you can turn this option off to hinder
820 such exploits. However, in that case, if a binary or library
821 relying on those helpers is run, it will receive a SIGILL signal,
822 which will terminate the program.
823
824 Say N here only if you are absolutely certain that you do not
825 need these helpers; otherwise, the safe option is to say Y.
826
827config DMA_CACHE_RWFO
828 bool "Enable read/write for ownership DMA cache maintenance"
829 depends on CPU_V6K && SMP
830 default y
831 help
832 The Snoop Control Unit on ARM11MPCore does not detect the
833 cache maintenance operations and the dma_{map,unmap}_area()
834 functions may leave stale cache entries on other CPUs. By
835 enabling this option, Read or Write For Ownership in the ARMv6
836 DMA cache maintenance functions is performed. These LDR/STR
837 instructions change the cache line state to shared or modified
838 so that the cache operation has the desired effect.
839
840 Note that the workaround is only valid on processors that do
841 not perform speculative loads into the D-cache. For such
842 processors, if cache maintenance operations are not broadcast
843 in hardware, other workarounds are needed (e.g. cache
844 maintenance broadcasting in software via FIQ).
845
846config OUTER_CACHE
847 bool
848
849config OUTER_CACHE_SYNC
850 bool
851 help
852 The outer cache has a outer_cache_fns.sync function pointer
853 that can be used to drain the write buffer of the outer cache.
854
855config CACHE_FEROCEON_L2
856 bool "Enable the Feroceon L2 cache controller"
857 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU
858 default y
859 select OUTER_CACHE
860 help
861 This option enables the Feroceon L2 cache controller.
862
863config CACHE_FEROCEON_L2_WRITETHROUGH
864 bool "Force Feroceon L2 cache write through"
865 depends on CACHE_FEROCEON_L2
866 help
867 Say Y here to use the Feroceon L2 cache in writethrough mode.
868 Unless you specifically require this, say N for writeback mode.
869
870config MIGHT_HAVE_CACHE_L2X0
871 bool
872 help
873 This option should be selected by machines which have a L2x0
874 or PL310 cache controller, but where its use is optional.
875
876 The only effect of this option is to make CACHE_L2X0 and
877 related options available to the user for configuration.
878
879 Boards or SoCs which always require the cache controller
880 support to be present should select CACHE_L2X0 directly
881 instead of this option, thus preventing the user from
882 inadvertently configuring a broken kernel.
883
884config CACHE_L2X0
885 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
886 default MIGHT_HAVE_CACHE_L2X0
887 select OUTER_CACHE
888 select OUTER_CACHE_SYNC
889 help
890 This option enables the L2x0 PrimeCell.
891
892config CACHE_PL310
893 bool
894 depends on CACHE_L2X0
895 default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
896 help
897 This option enables optimisations for the PL310 cache
898 controller.
899
900config CACHE_TAUROS2
901 bool "Enable the Tauros2 L2 cache controller"
902 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
903 default y
904 select OUTER_CACHE
905 help
906 This option enables the Tauros2 L2 cache controller (as
907 found on PJ1/PJ4).
908
909config CACHE_XSC3L2
910 bool "Enable the L2 cache on XScale3"
911 depends on CPU_XSC3
912 default y
913 select OUTER_CACHE
914 help
915 This option enables the L2 cache on XScale3.
916
917config ARM_L1_CACHE_SHIFT_6
918 bool
919 default y if CPU_V7
920 help
921 Setting ARM L1 cache line size to 64 Bytes.
922
923config ARM_L1_CACHE_SHIFT
924 int
925 default 6 if ARM_L1_CACHE_SHIFT_6
926 default 5
927
928config ARM_DMA_MEM_BUFFERABLE
929 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
930 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
931 MACH_REALVIEW_PB11MP)
932 default y if CPU_V6 || CPU_V6K || CPU_V7
933 help
934 Historically, the kernel has used strongly ordered mappings to
935 provide DMA coherent memory. With the advent of ARMv7, mapping
936 memory with differing types results in unpredictable behaviour,
937 so on these CPUs, this option is forced on.
938
939 Multiple mappings with differing attributes is also unpredictable
940 on ARMv6 CPUs, but since they do not have aggressive speculative
941 prefetch, no harm appears to occur.
942
943 However, drivers may be missing the necessary barriers for ARMv6,
944 and therefore turning this on may result in unpredictable driver
945 behaviour. Therefore, we offer this as an option.
946
947 You are recommended say 'Y' here and debug any affected drivers.
948
949config ARCH_HAS_BARRIERS
950 bool
951 help
952 This option allows the use of custom mandatory barriers
953 included via the mach/barriers.h file.
954
955config ARCH_SUPPORTS_BIG_ENDIAN
956 bool
957 help
958 This option specifies the architecture can support big endian
959 operation.