1/*
  2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  3 * Author: Tony Xie <tony.xie@rock-chips.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms and conditions of the GNU General Public License,
  7 * version 2, as published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope it will be useful, but WITHOUT
 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12 * more details.
 13 */
 14
 15#ifndef __MACH_ROCKCHIP_PM_H
 16#define __MACH_ROCKCHIP_PM_H
 17
 18extern unsigned long rkpm_bootdata_cpusp;
 19extern unsigned long rkpm_bootdata_cpu_code;
 20extern unsigned long rkpm_bootdata_l2ctlr_f;
 21extern unsigned long rkpm_bootdata_l2ctlr;
 22extern unsigned long rkpm_bootdata_ddr_code;
 23extern unsigned long rkpm_bootdata_ddr_data;
 24extern unsigned long rk3288_bootram_sz;
 25
 26void rockchip_slp_cpu_resume(void);
 27#ifdef CONFIG_PM_SLEEP
 28void __init rockchip_suspend_init(void);
 29#else
 30static inline void rockchip_suspend_init(void)
 31{
 32}
 33#endif
 34
 35/****** following is rk3288 defined **********/
 36#define RK3288_PMU_WAKEUP_CFG0		0x00
 37#define RK3288_PMU_WAKEUP_CFG1		0x04
 38#define RK3288_PMU_PWRMODE_CON		0x18
 39#define RK3288_PMU_OSC_CNT		0x20
 40#define RK3288_PMU_PLL_CNT		0x24
 41#define RK3288_PMU_STABL_CNT		0x28
 42#define RK3288_PMU_DDR0IO_PWRON_CNT	0x2c
 43#define RK3288_PMU_DDR1IO_PWRON_CNT	0x30
 44#define RK3288_PMU_CORE_PWRDWN_CNT	0x34
 45#define RK3288_PMU_CORE_PWRUP_CNT	0x38
 46#define RK3288_PMU_GPU_PWRDWN_CNT	0x3c
 47#define RK3288_PMU_GPU_PWRUP_CNT	0x40
 48#define RK3288_PMU_WAKEUP_RST_CLR_CNT	0x44
 49#define RK3288_PMU_PWRMODE_CON1		0x90
 50
 51#define RK3288_SGRF_SOC_CON0		(0x0000)
 52#define RK3288_SGRF_FAST_BOOT_ADDR	(0x0120)
 53#define SGRF_PCLK_WDT_GATE		BIT(6)
 54#define SGRF_PCLK_WDT_GATE_WRITE	BIT(22)
 55#define SGRF_FAST_BOOT_EN		BIT(8)
 56#define SGRF_FAST_BOOT_EN_WRITE		BIT(24)
 57
 58#define RK3288_SGRF_CPU_CON0		(0x40)
 59#define SGRF_DAPDEVICEEN		BIT(0)
 60#define SGRF_DAPDEVICEEN_WRITE		BIT(16)
 61
 62/* PMU_WAKEUP_CFG1 bits */
 63#define PMU_ARMINT_WAKEUP_EN		BIT(0)
 64#define PMU_GPIOINT_WAKEUP_EN		BIT(3)
 65
 66enum rk3288_pwr_mode_con {
 67	PMU_PWR_MODE_EN = 0,
 68	PMU_CLK_CORE_SRC_GATE_EN,
 69	PMU_GLOBAL_INT_DISABLE,
 70	PMU_L2FLUSH_EN,
 71	PMU_BUS_PD_EN,
 72	PMU_A12_0_PD_EN,
 73	PMU_SCU_EN,
 74	PMU_PLL_PD_EN,
 75	PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
 76	PMU_PWROFF_COMB,
 77	PMU_ALIVE_USE_LF,
 78	PMU_PMU_USE_LF,
 79	PMU_OSC_24M_DIS,
 80	PMU_INPUT_CLAMP_EN,
 81	PMU_WAKEUP_RESET_EN,
 82	PMU_SREF0_ENTER_EN,
 83	PMU_SREF1_ENTER_EN,
 84	PMU_DDR0IO_RET_EN,
 85	PMU_DDR1IO_RET_EN,
 86	PMU_DDR0_GATING_EN,
 87	PMU_DDR1_GATING_EN,
 88	PMU_DDR0IO_RET_DE_REQ,
 89	PMU_DDR1IO_RET_DE_REQ
 90};
 91
 92enum rk3288_pwr_mode_con1 {
 93	PMU_CLR_BUS = 0,
 94	PMU_CLR_CORE,
 95	PMU_CLR_CPUP,
 96	PMU_CLR_ALIVE,
 97	PMU_CLR_DMA,
 98	PMU_CLR_PERI,
 99	PMU_CLR_GPU,
100	PMU_CLR_VIDEO,
101	PMU_CLR_HEVC,
102	PMU_CLR_VIO,
103};
104
105#endif /* __MACH_ROCKCHIP_PM_H */