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1/*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/clockchips.h>
27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/err.h>
30#include <linux/sched_clock.h>
31
32#include <asm/mach/time.h>
33
34#include "common.h"
35#include "hardware.h"
36
37/*
38 * There are 2 versions of the timer hardware on Freescale MXC hardware.
39 * Version 1: MX1/MXL, MX21, MX27.
40 * Version 2: MX25, MX31, MX35, MX37, MX51
41 */
42
43/* defines common for all i.MX */
44#define MXC_TCTL 0x00
45#define MXC_TCTL_TEN (1 << 0) /* Enable module */
46#define MXC_TPRER 0x04
47
48/* MX1, MX21, MX27 */
49#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
50#define MX1_2_TCTL_IRQEN (1 << 4)
51#define MX1_2_TCTL_FRR (1 << 8)
52#define MX1_2_TCMP 0x08
53#define MX1_2_TCN 0x10
54#define MX1_2_TSTAT 0x14
55
56/* MX21, MX27 */
57#define MX2_TSTAT_CAPT (1 << 1)
58#define MX2_TSTAT_COMP (1 << 0)
59
60/* MX31, MX35, MX25, MX5 */
61#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
62#define V2_TCTL_CLK_IPG (1 << 6)
63#define V2_TCTL_CLK_PER (2 << 6)
64#define V2_TCTL_FRR (1 << 9)
65#define V2_IR 0x0c
66#define V2_TSTAT 0x08
67#define V2_TSTAT_OF1 (1 << 0)
68#define V2_TCN 0x24
69#define V2_TCMP 0x10
70
71#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
72#define timer_is_v2() (!timer_is_v1())
73
74static struct clock_event_device clockevent_mxc;
75static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
76
77static void __iomem *timer_base;
78
79static inline void gpt_irq_disable(void)
80{
81 unsigned int tmp;
82
83 if (timer_is_v2())
84 __raw_writel(0, timer_base + V2_IR);
85 else {
86 tmp = __raw_readl(timer_base + MXC_TCTL);
87 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
88 }
89}
90
91static inline void gpt_irq_enable(void)
92{
93 if (timer_is_v2())
94 __raw_writel(1<<0, timer_base + V2_IR);
95 else {
96 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
97 timer_base + MXC_TCTL);
98 }
99}
100
101static void gpt_irq_acknowledge(void)
102{
103 if (timer_is_v1()) {
104 if (cpu_is_mx1())
105 __raw_writel(0, timer_base + MX1_2_TSTAT);
106 else
107 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
108 timer_base + MX1_2_TSTAT);
109 } else if (timer_is_v2())
110 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
111}
112
113static void __iomem *sched_clock_reg;
114
115static u64 notrace mxc_read_sched_clock(void)
116{
117 return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
118}
119
120static struct delay_timer imx_delay_timer;
121
122static unsigned long imx_read_current_timer(void)
123{
124 return __raw_readl(sched_clock_reg);
125}
126
127static int __init mxc_clocksource_init(struct clk *timer_clk)
128{
129 unsigned int c = clk_get_rate(timer_clk);
130 void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
131
132 imx_delay_timer.read_current_timer = &imx_read_current_timer;
133 imx_delay_timer.freq = c;
134 register_current_timer_delay(&imx_delay_timer);
135
136 sched_clock_reg = reg;
137
138 sched_clock_register(mxc_read_sched_clock, 32, c);
139 return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
140 clocksource_mmio_readl_up);
141}
142
143/* clock event */
144
145static int mx1_2_set_next_event(unsigned long evt,
146 struct clock_event_device *unused)
147{
148 unsigned long tcmp;
149
150 tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
151
152 __raw_writel(tcmp, timer_base + MX1_2_TCMP);
153
154 return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
155 -ETIME : 0;
156}
157
158static int v2_set_next_event(unsigned long evt,
159 struct clock_event_device *unused)
160{
161 unsigned long tcmp;
162
163 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
164
165 __raw_writel(tcmp, timer_base + V2_TCMP);
166
167 return evt < 0x7fffffff &&
168 (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
169 -ETIME : 0;
170}
171
172#ifdef DEBUG
173static const char *clock_event_mode_label[] = {
174 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
175 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
176 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
177 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
178 [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
179};
180#endif /* DEBUG */
181
182static void mxc_set_mode(enum clock_event_mode mode,
183 struct clock_event_device *evt)
184{
185 unsigned long flags;
186
187 /*
188 * The timer interrupt generation is disabled at least
189 * for enough time to call mxc_set_next_event()
190 */
191 local_irq_save(flags);
192
193 /* Disable interrupt in GPT module */
194 gpt_irq_disable();
195
196 if (mode != clockevent_mode) {
197 /* Set event time into far-far future */
198 if (timer_is_v2())
199 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
200 timer_base + V2_TCMP);
201 else
202 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
203 timer_base + MX1_2_TCMP);
204
205 /* Clear pending interrupt */
206 gpt_irq_acknowledge();
207 }
208
209#ifdef DEBUG
210 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
211 clock_event_mode_label[clockevent_mode],
212 clock_event_mode_label[mode]);
213#endif /* DEBUG */
214
215 /* Remember timer mode */
216 clockevent_mode = mode;
217 local_irq_restore(flags);
218
219 switch (mode) {
220 case CLOCK_EVT_MODE_PERIODIC:
221 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
222 "supported for i.MX\n");
223 break;
224 case CLOCK_EVT_MODE_ONESHOT:
225 /*
226 * Do not put overhead of interrupt enable/disable into
227 * mxc_set_next_event(), the core has about 4 minutes
228 * to call mxc_set_next_event() or shutdown clock after
229 * mode switching
230 */
231 local_irq_save(flags);
232 gpt_irq_enable();
233 local_irq_restore(flags);
234 break;
235 case CLOCK_EVT_MODE_SHUTDOWN:
236 case CLOCK_EVT_MODE_UNUSED:
237 case CLOCK_EVT_MODE_RESUME:
238 /* Left event sources disabled, no more interrupts appear */
239 break;
240 }
241}
242
243/*
244 * IRQ handler for the timer
245 */
246static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
247{
248 struct clock_event_device *evt = &clockevent_mxc;
249 uint32_t tstat;
250
251 if (timer_is_v2())
252 tstat = __raw_readl(timer_base + V2_TSTAT);
253 else
254 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
255
256 gpt_irq_acknowledge();
257
258 evt->event_handler(evt);
259
260 return IRQ_HANDLED;
261}
262
263static struct irqaction mxc_timer_irq = {
264 .name = "i.MX Timer Tick",
265 .flags = IRQF_TIMER | IRQF_IRQPOLL,
266 .handler = mxc_timer_interrupt,
267};
268
269static struct clock_event_device clockevent_mxc = {
270 .name = "mxc_timer1",
271 .features = CLOCK_EVT_FEAT_ONESHOT,
272 .set_mode = mxc_set_mode,
273 .set_next_event = mx1_2_set_next_event,
274 .rating = 200,
275};
276
277static int __init mxc_clockevent_init(struct clk *timer_clk)
278{
279 if (timer_is_v2())
280 clockevent_mxc.set_next_event = v2_set_next_event;
281
282 clockevent_mxc.cpumask = cpumask_of(0);
283 clockevents_config_and_register(&clockevent_mxc,
284 clk_get_rate(timer_clk),
285 0xff, 0xfffffffe);
286
287 return 0;
288}
289
290void __init mxc_timer_init(void __iomem *base, int irq)
291{
292 uint32_t tctl_val;
293 struct clk *timer_clk;
294 struct clk *timer_ipg_clk;
295
296 timer_clk = clk_get_sys("imx-gpt.0", "per");
297 if (IS_ERR(timer_clk)) {
298 pr_err("i.MX timer: unable to get clk\n");
299 return;
300 }
301
302 timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
303 if (!IS_ERR(timer_ipg_clk))
304 clk_prepare_enable(timer_ipg_clk);
305
306 clk_prepare_enable(timer_clk);
307
308 timer_base = base;
309
310 /*
311 * Initialise to a known state (all timers off, and timing reset)
312 */
313
314 __raw_writel(0, timer_base + MXC_TCTL);
315 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
316
317 if (timer_is_v2())
318 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
319 else
320 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
321
322 __raw_writel(tctl_val, timer_base + MXC_TCTL);
323
324 /* init and register the timer to the framework */
325 mxc_clocksource_init(timer_clk);
326 mxc_clockevent_init(timer_clk);
327
328 /* Make irqs happen */
329 setup_irq(irq, &mxc_timer_irq);
330}