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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 - 2014 Xilinx
4 * Copyright (C) 2012 National Instruments Corp.
5 */
6/dts-v1/;
7#include "zynq-7000.dtsi"
8
9/ {
10 model = "Zynq ZC702 Development Board";
11 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
12
13 aliases {
14 ethernet0 = &gem0;
15 i2c0 = &i2c0;
16 serial0 = &uart1;
17 };
18
19 memory@0 {
20 device_type = "memory";
21 reg = <0x0 0x40000000>;
22 };
23
24 chosen {
25 bootargs = "";
26 stdout-path = "serial0:115200n8";
27 };
28
29 gpio-keys {
30 compatible = "gpio-keys";
31 #address-cells = <1>;
32 #size-cells = <0>;
33 autorepeat;
34 sw14 {
35 label = "sw14";
36 gpios = <&gpio0 12 0>;
37 linux,code = <108>; /* down */
38 wakeup-source;
39 autorepeat;
40 };
41 sw13 {
42 label = "sw13";
43 gpios = <&gpio0 14 0>;
44 linux,code = <103>; /* up */
45 wakeup-source;
46 autorepeat;
47 };
48 };
49
50 leds {
51 compatible = "gpio-leds";
52
53 ds23 {
54 label = "ds23";
55 gpios = <&gpio0 10 0>;
56 linux,default-trigger = "heartbeat";
57 };
58 };
59
60 usb_phy0: phy0 {
61 compatible = "usb-nop-xceiv";
62 #phy-cells = <0>;
63 };
64};
65
66&amba {
67 ocm: sram@fffc0000 {
68 compatible = "mmio-sram";
69 reg = <0xfffc0000 0x10000>;
70 };
71};
72
73&can0 {
74 status = "okay";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_can0_default>;
77};
78
79&clkc {
80 ps-clk-frequency = <33333333>;
81};
82
83&gem0 {
84 status = "okay";
85 phy-mode = "rgmii-id";
86 phy-handle = <ðernet_phy>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_gem0_default>;
89
90 ethernet_phy: ethernet-phy@7 {
91 reg = <7>;
92 device_type = "ethernet-phy";
93 };
94};
95
96&gpio0 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_gpio0_default>;
99};
100
101&i2c0 {
102 status = "okay";
103 clock-frequency = <400000>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_i2c0_default>;
106
107 i2c-mux@74 {
108 compatible = "nxp,pca9548";
109 #address-cells = <1>;
110 #size-cells = <0>;
111 reg = <0x74>;
112
113 i2c@0 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 reg = <0>;
117 si570: clock-generator@5d {
118 #clock-cells = <0>;
119 compatible = "silabs,si570";
120 temperature-stability = <50>;
121 reg = <0x5d>;
122 factory-fout = <156250000>;
123 clock-frequency = <148500000>;
124 };
125 };
126
127 i2c@1 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <1>;
131 adv7511: hdmi-tx@39 {
132 compatible = "adi,adv7511";
133 reg = <0x39>;
134 adi,input-depth = <8>;
135 adi,input-colorspace = "yuv422";
136 adi,input-clock = "1x";
137 adi,input-style = <3>;
138 adi,input-justification = "right";
139 };
140 };
141
142 i2c@2 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 reg = <2>;
146 eeprom@54 {
147 compatible = "atmel,24c08";
148 reg = <0x54>;
149 };
150 };
151
152 i2c@3 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 reg = <3>;
156 gpio@21 {
157 compatible = "ti,tca6416";
158 reg = <0x21>;
159 gpio-controller;
160 #gpio-cells = <2>;
161 };
162 };
163
164 i2c@4 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <4>;
168 rtc@51 {
169 compatible = "nxp,pcf8563";
170 reg = <0x51>;
171 };
172 };
173
174 i2c@7 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 reg = <7>;
178 hwmon@52 {
179 compatible = "ti,ucd9248";
180 reg = <52>;
181 };
182 hwmon@53 {
183 compatible = "ti,ucd9248";
184 reg = <53>;
185 };
186 hwmon@54 {
187 compatible = "ti,ucd9248";
188 reg = <54>;
189 };
190 };
191 };
192};
193
194&pinctrl0 {
195 pinctrl_can0_default: can0-default {
196 mux {
197 function = "can0";
198 groups = "can0_9_grp";
199 };
200
201 conf {
202 groups = "can0_9_grp";
203 slew-rate = <0>;
204 io-standard = <1>;
205 };
206
207 conf-rx {
208 pins = "MIO46";
209 bias-high-impedance;
210 };
211
212 conf-tx {
213 pins = "MIO47";
214 bias-disable;
215 };
216 };
217
218 pinctrl_gem0_default: gem0-default {
219 mux {
220 function = "ethernet0";
221 groups = "ethernet0_0_grp";
222 };
223
224 conf {
225 groups = "ethernet0_0_grp";
226 slew-rate = <0>;
227 io-standard = <4>;
228 };
229
230 conf-rx {
231 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
232 bias-high-impedance;
233 low-power-disable;
234 };
235
236 conf-tx {
237 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
238 bias-disable;
239 low-power-enable;
240 };
241
242 mux-mdio {
243 function = "mdio0";
244 groups = "mdio0_0_grp";
245 };
246
247 conf-mdio {
248 groups = "mdio0_0_grp";
249 slew-rate = <0>;
250 io-standard = <1>;
251 bias-disable;
252 };
253 };
254
255 pinctrl_gpio0_default: gpio0-default {
256 mux {
257 function = "gpio0";
258 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
259 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
260 "gpio0_13_grp", "gpio0_14_grp";
261 };
262
263 conf {
264 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
265 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
266 "gpio0_13_grp", "gpio0_14_grp";
267 slew-rate = <0>;
268 io-standard = <1>;
269 };
270
271 conf-pull-up {
272 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
273 bias-pull-up;
274 };
275
276 conf-pull-none {
277 pins = "MIO7", "MIO8";
278 bias-disable;
279 };
280 };
281
282 pinctrl_i2c0_default: i2c0-default {
283 mux {
284 groups = "i2c0_10_grp";
285 function = "i2c0";
286 };
287
288 conf {
289 groups = "i2c0_10_grp";
290 bias-pull-up;
291 slew-rate = <0>;
292 io-standard = <1>;
293 };
294 };
295
296 pinctrl_sdhci0_default: sdhci0-default {
297 mux {
298 groups = "sdio0_2_grp";
299 function = "sdio0";
300 };
301
302 conf {
303 groups = "sdio0_2_grp";
304 slew-rate = <0>;
305 io-standard = <1>;
306 bias-disable;
307 };
308
309 mux-cd {
310 groups = "gpio0_0_grp";
311 function = "sdio0_cd";
312 };
313
314 conf-cd {
315 groups = "gpio0_0_grp";
316 bias-high-impedance;
317 bias-pull-up;
318 slew-rate = <0>;
319 io-standard = <1>;
320 };
321
322 mux-wp {
323 groups = "gpio0_15_grp";
324 function = "sdio0_wp";
325 };
326
327 conf-wp {
328 groups = "gpio0_15_grp";
329 bias-high-impedance;
330 bias-pull-up;
331 slew-rate = <0>;
332 io-standard = <1>;
333 };
334 };
335
336 pinctrl_uart1_default: uart1-default {
337 mux {
338 groups = "uart1_10_grp";
339 function = "uart1";
340 };
341
342 conf {
343 groups = "uart1_10_grp";
344 slew-rate = <0>;
345 io-standard = <1>;
346 };
347
348 conf-rx {
349 pins = "MIO49";
350 bias-high-impedance;
351 };
352
353 conf-tx {
354 pins = "MIO48";
355 bias-disable;
356 };
357 };
358
359 pinctrl_usb0_default: usb0-default {
360 mux {
361 groups = "usb0_0_grp";
362 function = "usb0";
363 };
364
365 conf {
366 groups = "usb0_0_grp";
367 slew-rate = <0>;
368 io-standard = <1>;
369 };
370
371 conf-rx {
372 pins = "MIO29", "MIO31", "MIO36";
373 bias-high-impedance;
374 };
375
376 conf-tx {
377 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
378 "MIO35", "MIO37", "MIO38", "MIO39";
379 bias-disable;
380 };
381 };
382};
383
384&sdhci0 {
385 status = "okay";
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_sdhci0_default>;
388};
389
390&uart1 {
391 status = "okay";
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_uart1_default>;
394};
395
396&usb0 {
397 status = "okay";
398 dr_mode = "host";
399 usb-phy = <&usb_phy0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_usb0_default>;
402};
1/*
2 * Copyright (C) 2011 Xilinx
3 * Copyright (C) 2012 National Instruments Corp.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14/dts-v1/;
15/include/ "zynq-7000.dtsi"
16
17/ {
18 model = "Zynq ZC702 Development Board";
19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20
21 memory {
22 device_type = "memory";
23 reg = <0x0 0x40000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyPS0,115200 earlyprintk";
28 };
29
30};
31
32&gem0 {
33 status = "okay";
34 phy-mode = "rgmii";
35};
36
37&i2c0 {
38 status = "okay";
39 clock-frequency = <400000>;
40
41 i2cswitch@74 {
42 compatible = "nxp,pca9548";
43 #address-cells = <1>;
44 #size-cells = <0>;
45 reg = <0x74>;
46
47 i2c@0 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 reg = <0>;
51 si570: clock-generator@5d {
52 #clock-cells = <0>;
53 compatible = "silabs,si570";
54 temperature-stability = <50>;
55 reg = <0x5d>;
56 factory-fout = <156250000>;
57 clock-frequency = <148500000>;
58 };
59 };
60
61 i2c@2 {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 reg = <2>;
65 eeprom@54 {
66 compatible = "at,24c08";
67 reg = <0x54>;
68 };
69 };
70
71 i2c@3 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 reg = <3>;
75 gpio@21 {
76 compatible = "ti,tca6416";
77 reg = <0x21>;
78 gpio-controller;
79 #gpio-cells = <2>;
80 };
81 };
82
83 i2c@4 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <4>;
87 rtc@51 {
88 compatible = "nxp,pcf8563";
89 reg = <0x51>;
90 };
91 };
92
93 i2c@7 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 reg = <7>;
97 hwmon@52 {
98 compatible = "ti,ucd9248";
99 reg = <52>;
100 };
101 hwmon@53 {
102 compatible = "ti,ucd9248";
103 reg = <53>;
104 };
105 hwmon@54 {
106 compatible = "ti,ucd9248";
107 reg = <54>;
108 };
109 };
110 };
111};
112
113&sdhci0 {
114 status = "okay";
115};
116
117&uart1 {
118 status = "okay";
119};