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1// SPDX-License-Identifier: GPL-2.0
2#include "tegra20.dtsi"
3
4/ {
5 model = "Avionic Design Tamonten SOM";
6 compatible = "ad,tamonten", "nvidia,tegra20";
7
8 aliases {
9 rtc0 = "/i2c@7000d000/tps6586x@34";
10 rtc1 = "/rtc@7000e000";
11 serial0 = &uartd;
12 };
13
14 chosen {
15 stdout-path = "serial0:115200n8";
16 };
17
18 memory {
19 reg = <0x00000000 0x20000000>;
20 };
21
22 host1x@50000000 {
23 hdmi@54280000 {
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
26
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
29 GPIO_ACTIVE_HIGH>;
30 };
31 };
32
33 pinmux@70000014 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
36
37 state_default: pinmux {
38 ata {
39 nvidia,pins = "ata";
40 nvidia,function = "ide";
41 };
42 atb {
43 nvidia,pins = "atb", "gma", "gme";
44 nvidia,function = "sdio4";
45 };
46 atc {
47 nvidia,pins = "atc";
48 nvidia,function = "nand";
49 };
50 atd {
51 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
52 "spia", "spib", "spic";
53 nvidia,function = "gmi";
54 };
55 cdev1 {
56 nvidia,pins = "cdev1";
57 nvidia,function = "plla_out";
58 };
59 cdev2 {
60 nvidia,pins = "cdev2";
61 nvidia,function = "pllp_out4";
62 };
63 crtp {
64 nvidia,pins = "crtp";
65 nvidia,function = "crt";
66 };
67 csus {
68 nvidia,pins = "csus";
69 nvidia,function = "vi_sensor_clk";
70 };
71 dap1 {
72 nvidia,pins = "dap1";
73 nvidia,function = "dap1";
74 };
75 dap2 {
76 nvidia,pins = "dap2";
77 nvidia,function = "dap2";
78 };
79 dap3 {
80 nvidia,pins = "dap3";
81 nvidia,function = "dap3";
82 };
83 dap4 {
84 nvidia,pins = "dap4";
85 nvidia,function = "dap4";
86 };
87 dta {
88 nvidia,pins = "dta", "dtd";
89 nvidia,function = "sdio2";
90 };
91 dtb {
92 nvidia,pins = "dtb", "dtc", "dte";
93 nvidia,function = "rsvd1";
94 };
95 dtf {
96 nvidia,pins = "dtf";
97 nvidia,function = "i2c3";
98 };
99 gmc {
100 nvidia,pins = "gmc";
101 nvidia,function = "uartd";
102 };
103 gpu7 {
104 nvidia,pins = "gpu7";
105 nvidia,function = "rtck";
106 };
107 gpv {
108 nvidia,pins = "gpv", "slxa", "slxk";
109 nvidia,function = "pcie";
110 };
111 hdint {
112 nvidia,pins = "hdint";
113 nvidia,function = "hdmi";
114 };
115 i2cp {
116 nvidia,pins = "i2cp";
117 nvidia,function = "i2cp";
118 };
119 irrx {
120 nvidia,pins = "irrx", "irtx";
121 nvidia,function = "uarta";
122 };
123 kbca {
124 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
125 "kbce", "kbcf";
126 nvidia,function = "kbc";
127 };
128 lcsn {
129 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
130 "ld3", "ld4", "ld5", "ld6", "ld7",
131 "ld8", "ld9", "ld10", "ld11", "ld12",
132 "ld13", "ld14", "ld15", "ld16", "ld17",
133 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
134 "lhs", "lm0", "lm1", "lpp", "lpw0",
135 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
136 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
137 "lvs";
138 nvidia,function = "displaya";
139 };
140 owc {
141 nvidia,pins = "owc", "spdi", "spdo", "uac";
142 nvidia,function = "rsvd2";
143 };
144 pmc {
145 nvidia,pins = "pmc";
146 nvidia,function = "pwr_on";
147 };
148 rm {
149 nvidia,pins = "rm";
150 nvidia,function = "i2c1";
151 };
152 sdb {
153 nvidia,pins = "sdb", "sdc", "sdd";
154 nvidia,function = "pwm";
155 };
156 sdio1 {
157 nvidia,pins = "sdio1";
158 nvidia,function = "sdio1";
159 };
160 slxc {
161 nvidia,pins = "slxc", "slxd";
162 nvidia,function = "spdif";
163 };
164 spid {
165 nvidia,pins = "spid", "spie", "spif";
166 nvidia,function = "spi1";
167 };
168 spig {
169 nvidia,pins = "spig", "spih";
170 nvidia,function = "spi2_alt";
171 };
172 uaa {
173 nvidia,pins = "uaa", "uab", "uda";
174 nvidia,function = "ulpi";
175 };
176 uad {
177 nvidia,pins = "uad";
178 nvidia,function = "irda";
179 };
180 uca {
181 nvidia,pins = "uca", "ucb";
182 nvidia,function = "uartc";
183 };
184 conf_ata {
185 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
186 "cdev1", "cdev2", "dap1", "dtb", "gma",
187 "gmb", "gmc", "gmd", "gme", "gpu7",
188 "gpv", "i2cp", "pta", "rm", "slxa",
189 "slxk", "spia", "spib", "uac";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
192 };
193 conf_ck32 {
194 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
195 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 };
198 conf_csus {
199 nvidia,pins = "csus", "spid", "spif";
200 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
201 nvidia,tristate = <TEGRA_PIN_ENABLE>;
202 };
203 conf_crtp {
204 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
205 "dtc", "dte", "dtf", "gpu", "sdio1",
206 "slxc", "slxd", "spdi", "spdo", "spig",
207 "uda";
208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristate = <TEGRA_PIN_ENABLE>;
210 };
211 conf_ddc {
212 nvidia,pins = "ddc", "dta", "dtd", "kbca",
213 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
214 "sdc";
215 nvidia,pull = <TEGRA_PIN_PULL_UP>;
216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 };
218 conf_hdint {
219 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
220 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
221 "lvp0", "owc", "sdb";
222 nvidia,tristate = <TEGRA_PIN_ENABLE>;
223 };
224 conf_irrx {
225 nvidia,pins = "irrx", "irtx", "sdd", "spic",
226 "spie", "spih", "uaa", "uab", "uad",
227 "uca", "ucb";
228 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <TEGRA_PIN_ENABLE>;
230 };
231 conf_lc {
232 nvidia,pins = "lc", "ls";
233 nvidia,pull = <TEGRA_PIN_PULL_UP>;
234 };
235 conf_ld0 {
236 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
237 "ld5", "ld6", "ld7", "ld8", "ld9",
238 "ld10", "ld11", "ld12", "ld13", "ld14",
239 "ld15", "ld16", "ld17", "ldi", "lhp0",
240 "lhp1", "lhp2", "lhs", "lm0", "lpp",
241 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
242 "lvs", "pmc";
243 nvidia,tristate = <TEGRA_PIN_DISABLE>;
244 };
245 conf_ld17_0 {
246 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
247 "ld23_22";
248 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
249 };
250 };
251
252 state_i2cmux_ddc: pinmux_i2cmux_ddc {
253 ddc {
254 nvidia,pins = "ddc";
255 nvidia,function = "i2c2";
256 };
257 pta {
258 nvidia,pins = "pta";
259 nvidia,function = "rsvd4";
260 };
261 };
262
263 state_i2cmux_pta: pinmux_i2cmux_pta {
264 ddc {
265 nvidia,pins = "ddc";
266 nvidia,function = "rsvd4";
267 };
268 pta {
269 nvidia,pins = "pta";
270 nvidia,function = "i2c2";
271 };
272 };
273
274 state_i2cmux_idle: pinmux_i2cmux_idle {
275 ddc {
276 nvidia,pins = "ddc";
277 nvidia,function = "rsvd4";
278 };
279 pta {
280 nvidia,pins = "pta";
281 nvidia,function = "rsvd4";
282 };
283 };
284 };
285
286 i2s@70002800 {
287 status = "okay";
288 };
289
290 serial@70006300 {
291 status = "okay";
292 };
293
294 i2c@7000c000 {
295 clock-frequency = <400000>;
296 status = "okay";
297 };
298
299 i2c@7000c400 {
300 clock-frequency = <100000>;
301 status = "okay";
302 };
303
304 i2cmux {
305 compatible = "i2c-mux-pinctrl";
306 #address-cells = <1>;
307 #size-cells = <0>;
308
309 i2c-parent = <&{/i2c@7000c400}>;
310
311 pinctrl-names = "ddc", "pta", "idle";
312 pinctrl-0 = <&state_i2cmux_ddc>;
313 pinctrl-1 = <&state_i2cmux_pta>;
314 pinctrl-2 = <&state_i2cmux_idle>;
315
316 hdmi_ddc: i2c@0 {
317 reg = <0>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 };
321
322 i2c@1 {
323 reg = <1>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 };
327 };
328
329 i2c@7000d000 {
330 clock-frequency = <400000>;
331 status = "okay";
332
333 pmic: tps6586x@34 {
334 compatible = "ti,tps6586x";
335 reg = <0x34>;
336 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
337
338 ti,system-power-controller;
339
340 #gpio-cells = <2>;
341 gpio-controller;
342
343 /* vdd_5v0_reg must be provided by the base board */
344 sys-supply = <&vdd_5v0_reg>;
345 vin-sm0-supply = <&sys_reg>;
346 vin-sm1-supply = <&sys_reg>;
347 vin-sm2-supply = <&sys_reg>;
348 vinldo01-supply = <&sm2_reg>;
349 vinldo23-supply = <&sm2_reg>;
350 vinldo4-supply = <&sm2_reg>;
351 vinldo678-supply = <&sm2_reg>;
352 vinldo9-supply = <&sm2_reg>;
353
354 regulators {
355 sys_reg: sys {
356 regulator-name = "vdd_sys";
357 regulator-always-on;
358 };
359
360 sm0 {
361 regulator-name = "vdd_sys_sm0,vdd_core";
362 regulator-min-microvolt = <1200000>;
363 regulator-max-microvolt = <1200000>;
364 regulator-always-on;
365 };
366
367 sm1 {
368 regulator-name = "vdd_sys_sm1,vdd_cpu";
369 regulator-min-microvolt = <1000000>;
370 regulator-max-microvolt = <1000000>;
371 regulator-always-on;
372 };
373
374 sm2_reg: sm2 {
375 regulator-name = "vdd_sys_sm2,vin_ldo*";
376 regulator-min-microvolt = <3700000>;
377 regulator-max-microvolt = <3700000>;
378 regulator-always-on;
379 };
380
381 pci_clk_reg: ldo0 {
382 regulator-name = "vdd_ldo0,vddio_pex_clk";
383 regulator-min-microvolt = <3300000>;
384 regulator-max-microvolt = <3300000>;
385 };
386
387 ldo1 {
388 regulator-name = "vdd_ldo1,avdd_pll*";
389 regulator-min-microvolt = <1100000>;
390 regulator-max-microvolt = <1100000>;
391 regulator-always-on;
392 };
393
394 ldo2 {
395 regulator-name = "vdd_ldo2,vdd_rtc";
396 regulator-min-microvolt = <1200000>;
397 regulator-max-microvolt = <1200000>;
398 };
399
400 ldo3 {
401 regulator-name = "vdd_ldo3,avdd_usb*";
402 regulator-min-microvolt = <3300000>;
403 regulator-max-microvolt = <3300000>;
404 regulator-always-on;
405 };
406
407 ldo4 {
408 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
409 regulator-min-microvolt = <1800000>;
410 regulator-max-microvolt = <1800000>;
411 regulator-always-on;
412 };
413
414 ldo5 {
415 regulator-name = "vdd_ldo5,vcore_mmc";
416 regulator-min-microvolt = <2850000>;
417 regulator-max-microvolt = <2850000>;
418 };
419
420 ldo6 {
421 regulator-name = "vdd_ldo6,avdd_vdac";
422 /*
423 * According to the Tegra 2 Automotive
424 * DataSheet, a typical value for this
425 * would be 2.8V, but the PMIC only
426 * supports 2.85V.
427 */
428 regulator-min-microvolt = <2850000>;
429 regulator-max-microvolt = <2850000>;
430 };
431
432 hdmi_vdd_reg: ldo7 {
433 regulator-name = "vdd_ldo7,avdd_hdmi";
434 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>;
436 };
437
438 hdmi_pll_reg: ldo8 {
439 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
440 regulator-min-microvolt = <1800000>;
441 regulator-max-microvolt = <1800000>;
442 };
443
444 ldo9 {
445 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
446 /*
447 * According to the Tegra 2 Automotive
448 * DataSheet, a typical value for this
449 * would be 2.8V, but the PMIC only
450 * supports 2.85V.
451 */
452 regulator-min-microvolt = <2850000>;
453 regulator-max-microvolt = <2850000>;
454 regulator-always-on;
455 };
456
457 ldo_rtc {
458 regulator-name = "vdd_rtc_out";
459 regulator-min-microvolt = <3300000>;
460 regulator-max-microvolt = <3300000>;
461 regulator-always-on;
462 };
463 };
464 };
465
466 temperature-sensor@4c {
467 compatible = "onnn,nct1008";
468 reg = <0x4c>;
469 };
470 };
471
472 pmc@7000e400 {
473 nvidia,invert-interrupt;
474 nvidia,suspend-mode = <1>;
475 nvidia,cpu-pwr-good-time = <5000>;
476 nvidia,cpu-pwr-off-time = <5000>;
477 nvidia,core-pwr-good-time = <3845 3845>;
478 nvidia,core-pwr-off-time = <3875>;
479 nvidia,sys-clock-req-active-high;
480 };
481
482 pcie@80003000 {
483 avdd-pex-supply = <&pci_vdd_reg>;
484 vdd-pex-supply = <&pci_vdd_reg>;
485 avdd-pex-pll-supply = <&pci_vdd_reg>;
486 avdd-plle-supply = <&pci_vdd_reg>;
487 vddio-pex-clk-supply = <&pci_clk_reg>;
488 };
489
490 usb@c5008000 {
491 status = "okay";
492 };
493
494 usb-phy@c5008000 {
495 status = "okay";
496 };
497
498 sdhci@c8000600 {
499 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
500 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
501 bus-width = <4>;
502 status = "okay";
503 };
504
505 clocks {
506 compatible = "simple-bus";
507 #address-cells = <1>;
508 #size-cells = <0>;
509
510 clk32k_in: clock@0 {
511 compatible = "fixed-clock";
512 reg = <0>;
513 #clock-cells = <0>;
514 clock-frequency = <32768>;
515 };
516 };
517
518 regulators {
519 compatible = "simple-bus";
520
521 #address-cells = <1>;
522 #size-cells = <0>;
523
524 pci_vdd_reg: regulator@1 {
525 compatible = "regulator-fixed";
526 reg = <1>;
527 regulator-name = "vdd_1v05";
528 regulator-min-microvolt = <1050000>;
529 regulator-max-microvolt = <1050000>;
530 gpio = <&pmic 2 0>;
531 enable-active-high;
532 };
533 };
534};
1#include "tegra20.dtsi"
2
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
7 aliases {
8 rtc0 = "/i2c@7000d000/tps6586x@34";
9 rtc1 = "/rtc@7000e000";
10 };
11
12 memory {
13 reg = <0x00000000 0x20000000>;
14 };
15
16 host1x@50000000 {
17 hdmi@54280000 {
18 vdd-supply = <&hdmi_vdd_reg>;
19 pll-supply = <&hdmi_pll_reg>;
20
21 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
22 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
23 GPIO_ACTIVE_HIGH>;
24 };
25 };
26
27 pinmux@70000014 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 ata {
33 nvidia,pins = "ata";
34 nvidia,function = "ide";
35 };
36 atb {
37 nvidia,pins = "atb", "gma", "gme";
38 nvidia,function = "sdio4";
39 };
40 atc {
41 nvidia,pins = "atc";
42 nvidia,function = "nand";
43 };
44 atd {
45 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
46 "spia", "spib", "spic";
47 nvidia,function = "gmi";
48 };
49 cdev1 {
50 nvidia,pins = "cdev1";
51 nvidia,function = "plla_out";
52 };
53 cdev2 {
54 nvidia,pins = "cdev2";
55 nvidia,function = "pllp_out4";
56 };
57 crtp {
58 nvidia,pins = "crtp";
59 nvidia,function = "crt";
60 };
61 csus {
62 nvidia,pins = "csus";
63 nvidia,function = "vi_sensor_clk";
64 };
65 dap1 {
66 nvidia,pins = "dap1";
67 nvidia,function = "dap1";
68 };
69 dap2 {
70 nvidia,pins = "dap2";
71 nvidia,function = "dap2";
72 };
73 dap3 {
74 nvidia,pins = "dap3";
75 nvidia,function = "dap3";
76 };
77 dap4 {
78 nvidia,pins = "dap4";
79 nvidia,function = "dap4";
80 };
81 dta {
82 nvidia,pins = "dta", "dtd";
83 nvidia,function = "sdio2";
84 };
85 dtb {
86 nvidia,pins = "dtb", "dtc", "dte";
87 nvidia,function = "rsvd1";
88 };
89 dtf {
90 nvidia,pins = "dtf";
91 nvidia,function = "i2c3";
92 };
93 gmc {
94 nvidia,pins = "gmc";
95 nvidia,function = "uartd";
96 };
97 gpu7 {
98 nvidia,pins = "gpu7";
99 nvidia,function = "rtck";
100 };
101 gpv {
102 nvidia,pins = "gpv", "slxa", "slxk";
103 nvidia,function = "pcie";
104 };
105 hdint {
106 nvidia,pins = "hdint";
107 nvidia,function = "hdmi";
108 };
109 i2cp {
110 nvidia,pins = "i2cp";
111 nvidia,function = "i2cp";
112 };
113 irrx {
114 nvidia,pins = "irrx", "irtx";
115 nvidia,function = "uarta";
116 };
117 kbca {
118 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
119 "kbce", "kbcf";
120 nvidia,function = "kbc";
121 };
122 lcsn {
123 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
124 "ld3", "ld4", "ld5", "ld6", "ld7",
125 "ld8", "ld9", "ld10", "ld11", "ld12",
126 "ld13", "ld14", "ld15", "ld16", "ld17",
127 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
128 "lhs", "lm0", "lm1", "lpp", "lpw0",
129 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
130 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
131 "lvs";
132 nvidia,function = "displaya";
133 };
134 owc {
135 nvidia,pins = "owc", "spdi", "spdo", "uac";
136 nvidia,function = "rsvd2";
137 };
138 pmc {
139 nvidia,pins = "pmc";
140 nvidia,function = "pwr_on";
141 };
142 rm {
143 nvidia,pins = "rm";
144 nvidia,function = "i2c1";
145 };
146 sdb {
147 nvidia,pins = "sdb", "sdc", "sdd";
148 nvidia,function = "pwm";
149 };
150 sdio1 {
151 nvidia,pins = "sdio1";
152 nvidia,function = "sdio1";
153 };
154 slxc {
155 nvidia,pins = "slxc", "slxd";
156 nvidia,function = "spdif";
157 };
158 spid {
159 nvidia,pins = "spid", "spie", "spif";
160 nvidia,function = "spi1";
161 };
162 spig {
163 nvidia,pins = "spig", "spih";
164 nvidia,function = "spi2_alt";
165 };
166 uaa {
167 nvidia,pins = "uaa", "uab", "uda";
168 nvidia,function = "ulpi";
169 };
170 uad {
171 nvidia,pins = "uad";
172 nvidia,function = "irda";
173 };
174 uca {
175 nvidia,pins = "uca", "ucb";
176 nvidia,function = "uartc";
177 };
178 conf_ata {
179 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
180 "cdev1", "cdev2", "dap1", "dtb", "gma",
181 "gmb", "gmc", "gmd", "gme", "gpu7",
182 "gpv", "i2cp", "pta", "rm", "slxa",
183 "slxk", "spia", "spib", "uac";
184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 };
187 conf_ck32 {
188 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
189 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 };
192 conf_csus {
193 nvidia,pins = "csus", "spid", "spif";
194 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
195 nvidia,tristate = <TEGRA_PIN_ENABLE>;
196 };
197 conf_crtp {
198 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
199 "dtc", "dte", "dtf", "gpu", "sdio1",
200 "slxc", "slxd", "spdi", "spdo", "spig",
201 "uda";
202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_ENABLE>;
204 };
205 conf_ddc {
206 nvidia,pins = "ddc", "dta", "dtd", "kbca",
207 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
208 "sdc";
209 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212 conf_hdint {
213 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
214 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
215 "lvp0", "owc", "sdb";
216 nvidia,tristate = <TEGRA_PIN_ENABLE>;
217 };
218 conf_irrx {
219 nvidia,pins = "irrx", "irtx", "sdd", "spic",
220 "spie", "spih", "uaa", "uab", "uad",
221 "uca", "ucb";
222 nvidia,pull = <TEGRA_PIN_PULL_UP>;
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
224 };
225 conf_lc {
226 nvidia,pins = "lc", "ls";
227 nvidia,pull = <TEGRA_PIN_PULL_UP>;
228 };
229 conf_ld0 {
230 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
231 "ld5", "ld6", "ld7", "ld8", "ld9",
232 "ld10", "ld11", "ld12", "ld13", "ld14",
233 "ld15", "ld16", "ld17", "ldi", "lhp0",
234 "lhp1", "lhp2", "lhs", "lm0", "lpp",
235 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
236 "lvs", "pmc";
237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
238 };
239 conf_ld17_0 {
240 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
241 "ld23_22";
242 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
243 };
244 };
245
246 state_i2cmux_ddc: pinmux_i2cmux_ddc {
247 ddc {
248 nvidia,pins = "ddc";
249 nvidia,function = "i2c2";
250 };
251 pta {
252 nvidia,pins = "pta";
253 nvidia,function = "rsvd4";
254 };
255 };
256
257 state_i2cmux_pta: pinmux_i2cmux_pta {
258 ddc {
259 nvidia,pins = "ddc";
260 nvidia,function = "rsvd4";
261 };
262 pta {
263 nvidia,pins = "pta";
264 nvidia,function = "i2c2";
265 };
266 };
267
268 state_i2cmux_idle: pinmux_i2cmux_idle {
269 ddc {
270 nvidia,pins = "ddc";
271 nvidia,function = "rsvd4";
272 };
273 pta {
274 nvidia,pins = "pta";
275 nvidia,function = "rsvd4";
276 };
277 };
278 };
279
280 i2s@70002800 {
281 status = "okay";
282 };
283
284 serial@70006300 {
285 status = "okay";
286 };
287
288 i2c@7000c000 {
289 clock-frequency = <400000>;
290 status = "okay";
291 };
292
293 i2c@7000c400 {
294 clock-frequency = <100000>;
295 status = "okay";
296 };
297
298 i2cmux {
299 compatible = "i2c-mux-pinctrl";
300 #address-cells = <1>;
301 #size-cells = <0>;
302
303 i2c-parent = <&{/i2c@7000c400}>;
304
305 pinctrl-names = "ddc", "pta", "idle";
306 pinctrl-0 = <&state_i2cmux_ddc>;
307 pinctrl-1 = <&state_i2cmux_pta>;
308 pinctrl-2 = <&state_i2cmux_idle>;
309
310 hdmi_ddc: i2c@0 {
311 reg = <0>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 };
315
316 i2c@1 {
317 reg = <1>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 };
321 };
322
323 i2c@7000d000 {
324 clock-frequency = <400000>;
325 status = "okay";
326
327 pmic: tps6586x@34 {
328 compatible = "ti,tps6586x";
329 reg = <0x34>;
330 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
331
332 ti,system-power-controller;
333
334 #gpio-cells = <2>;
335 gpio-controller;
336
337 sys-supply = <&vdd_5v0_reg>;
338 vin-sm0-supply = <&sys_reg>;
339 vin-sm1-supply = <&sys_reg>;
340 vin-sm2-supply = <&sys_reg>;
341 vinldo01-supply = <&sm2_reg>;
342 vinldo23-supply = <&sm2_reg>;
343 vinldo4-supply = <&sm2_reg>;
344 vinldo678-supply = <&sm2_reg>;
345 vinldo9-supply = <&sm2_reg>;
346
347 regulators {
348 sys_reg: sys {
349 regulator-name = "vdd_sys";
350 regulator-always-on;
351 };
352
353 sm0 {
354 regulator-name = "vdd_sys_sm0,vdd_core";
355 regulator-min-microvolt = <1200000>;
356 regulator-max-microvolt = <1200000>;
357 regulator-always-on;
358 };
359
360 sm1 {
361 regulator-name = "vdd_sys_sm1,vdd_cpu";
362 regulator-min-microvolt = <1000000>;
363 regulator-max-microvolt = <1000000>;
364 regulator-always-on;
365 };
366
367 sm2_reg: sm2 {
368 regulator-name = "vdd_sys_sm2,vin_ldo*";
369 regulator-min-microvolt = <3700000>;
370 regulator-max-microvolt = <3700000>;
371 regulator-always-on;
372 };
373
374 pci_clk_reg: ldo0 {
375 regulator-name = "vdd_ldo0,vddio_pex_clk";
376 regulator-min-microvolt = <3300000>;
377 regulator-max-microvolt = <3300000>;
378 };
379
380 ldo1 {
381 regulator-name = "vdd_ldo1,avdd_pll*";
382 regulator-min-microvolt = <1100000>;
383 regulator-max-microvolt = <1100000>;
384 regulator-always-on;
385 };
386
387 ldo2 {
388 regulator-name = "vdd_ldo2,vdd_rtc";
389 regulator-min-microvolt = <1200000>;
390 regulator-max-microvolt = <1200000>;
391 };
392
393 ldo3 {
394 regulator-name = "vdd_ldo3,avdd_usb*";
395 regulator-min-microvolt = <3300000>;
396 regulator-max-microvolt = <3300000>;
397 regulator-always-on;
398 };
399
400 ldo4 {
401 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
402 regulator-min-microvolt = <1800000>;
403 regulator-max-microvolt = <1800000>;
404 regulator-always-on;
405 };
406
407 ldo5 {
408 regulator-name = "vdd_ldo5,vcore_mmc";
409 regulator-min-microvolt = <2850000>;
410 regulator-max-microvolt = <2850000>;
411 };
412
413 ldo6 {
414 regulator-name = "vdd_ldo6,avdd_vdac";
415 /*
416 * According to the Tegra 2 Automotive
417 * DataSheet, a typical value for this
418 * would be 2.8V, but the PMIC only
419 * supports 2.85V.
420 */
421 regulator-min-microvolt = <2850000>;
422 regulator-max-microvolt = <2850000>;
423 };
424
425 hdmi_vdd_reg: ldo7 {
426 regulator-name = "vdd_ldo7,avdd_hdmi";
427 regulator-min-microvolt = <3300000>;
428 regulator-max-microvolt = <3300000>;
429 };
430
431 hdmi_pll_reg: ldo8 {
432 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
433 regulator-min-microvolt = <1800000>;
434 regulator-max-microvolt = <1800000>;
435 };
436
437 ldo9 {
438 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
439 /*
440 * According to the Tegra 2 Automotive
441 * DataSheet, a typical value for this
442 * would be 2.8V, but the PMIC only
443 * supports 2.85V.
444 */
445 regulator-min-microvolt = <2850000>;
446 regulator-max-microvolt = <2850000>;
447 regulator-always-on;
448 };
449
450 ldo_rtc {
451 regulator-name = "vdd_rtc_out";
452 regulator-min-microvolt = <3300000>;
453 regulator-max-microvolt = <3300000>;
454 regulator-always-on;
455 };
456 };
457 };
458
459 temperature-sensor@4c {
460 compatible = "onnn,nct1008";
461 reg = <0x4c>;
462 };
463 };
464
465 pmc@7000e400 {
466 nvidia,invert-interrupt;
467 nvidia,suspend-mode = <1>;
468 nvidia,cpu-pwr-good-time = <5000>;
469 nvidia,cpu-pwr-off-time = <5000>;
470 nvidia,core-pwr-good-time = <3845 3845>;
471 nvidia,core-pwr-off-time = <3875>;
472 nvidia,sys-clock-req-active-high;
473 };
474
475 pcie-controller@80003000 {
476 pex-clk-supply = <&pci_clk_reg>;
477 vdd-supply = <&pci_vdd_reg>;
478 };
479
480 usb@c5008000 {
481 status = "okay";
482 };
483
484 usb-phy@c5008000 {
485 status = "okay";
486 };
487
488 sdhci@c8000600 {
489 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
490 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
491 bus-width = <4>;
492 status = "okay";
493 };
494
495 clocks {
496 compatible = "simple-bus";
497 #address-cells = <1>;
498 #size-cells = <0>;
499
500 clk32k_in: clock@0 {
501 compatible = "fixed-clock";
502 reg=<0>;
503 #clock-cells = <0>;
504 clock-frequency = <32768>;
505 };
506 };
507
508 regulators {
509 compatible = "simple-bus";
510
511 #address-cells = <1>;
512 #size-cells = <0>;
513
514 vdd_5v0_reg: regulator@0 {
515 compatible = "regulator-fixed";
516 reg = <0>;
517 regulator-name = "vdd_5v0";
518 regulator-min-microvolt = <5000000>;
519 regulator-max-microvolt = <5000000>;
520 regulator-always-on;
521 };
522
523 pci_vdd_reg: regulator@1 {
524 compatible = "regulator-fixed";
525 reg = <1>;
526 regulator-name = "vdd_1v05";
527 regulator-min-microvolt = <1050000>;
528 regulator-max-microvolt = <1050000>;
529 gpio = <&pmic 2 0>;
530 enable-active-high;
531 };
532 };
533};