Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree for the ARM Integrator/AP platform
4 */
5
6/dts-v1/;
7/include/ "integrator.dtsi"
8
9/ {
10 model = "ARM Integrator/AP";
11 compatible = "arm,integrator-ap";
12 dma-ranges = <0x80000000 0x0 0x80000000>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 device_type = "cpu";
20 /*
21 * Since the board has pluggable CPU modules, we
22 * cannot define a proper compatible here. Let the
23 * boot loader fill in the apropriate compatible
24 * string if necessary.
25 */
26 /* compatible = "arm,arm926ej-s"; */
27 reg = <0>;
28 /*
29 * The documentation in ARM DUI 0138E page 3-12 states
30 * that the maximum frequency for this clock is 200 MHz
31 * but painful trial-and-error has proved to me that it
32 * is actually just hanging the system above 71 MHz.
33 * Sad but true.
34 */
35 /* kHz uV */
36 operating-points = <71000 0
37 66000 0
38 60000 0
39 48000 0
40 36000 0
41 24000 0
42 12000 0>;
43 clocks = <&cmosc>;
44 clock-names = "cpu";
45 clock-latency = <1000000>; /* 1 ms */
46 };
47 };
48
49 aliases {
50 arm,timer-primary = &timer2;
51 arm,timer-secondary = &timer1;
52 };
53
54 chosen {
55 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
56 };
57
58 /* 24 MHz chrystal on the Integrator/AP development board */
59 xtal24mhz: xtal24mhz@24M {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <24000000>;
63 };
64
65 pclk: pclk@0 {
66 #clock-cells = <0>;
67 compatible = "fixed-factor-clock";
68 clock-div = <1>;
69 clock-mult = <1>;
70 clocks = <&xtal24mhz>;
71 };
72
73 /* The UART clock is 14.74 MHz divided by an ICS525 */
74 uartclk: uartclk@14.74M {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <14745600>;
78 clocks = <&xtal24mhz>;
79 };
80
81 core-module@10000000 {
82 /* 24 MHz chrystal on the core module */
83 cm24mhz: cm24mhz@24M {
84 #clock-cells = <0>;
85 compatible = "fixed-clock";
86 clock-frequency = <24000000>;
87 };
88
89 /* Oscillator on the core module, clocks the CPU core */
90 cmosc: cmosc@24M {
91 compatible = "arm,syscon-icst525-integratorap-cm";
92 #clock-cells = <0>;
93 lock-offset = <0x14>;
94 vco-offset = <0x08>;
95 clocks = <&cm24mhz>;
96 };
97
98 /* Auxilary oscillator on the core module, 32.369MHz at boot */
99 auxosc: auxosc@24M {
100 compatible = "arm,syscon-icst525";
101 #clock-cells = <0>;
102 lock-offset = <0x14>;
103 vco-offset = <0x1c>;
104 clocks = <&cm24mhz>;
105 };
106 };
107
108 syscon {
109 compatible = "arm,integrator-ap-syscon", "syscon";
110 reg = <0x11000000 0x100>;
111 interrupt-parent = <&pic>;
112 /* These are the logical module IRQs */
113 interrupts = <9>, <10>, <11>, <12>;
114
115 /*
116 * SYSCLK clocks PCIv3 bridge, system controller and the
117 * logic modules.
118 */
119 sysclk: apsys@24M {
120 compatible = "arm,syscon-icst525-integratorap-sys";
121 #clock-cells = <0>;
122 lock-offset = <0x1c>;
123 vco-offset = <0x04>;
124 clocks = <&xtal24mhz>;
125 };
126
127 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
128 pciclk: pciclk@24M {
129 compatible = "arm,syscon-icst525-integratorap-pci";
130 #clock-cells = <0>;
131 lock-offset = <0x1c>;
132 vco-offset = <0x04>;
133 clocks = <&xtal24mhz>;
134 };
135 };
136
137 timer0: timer@13000000 {
138 compatible = "arm,integrator-timer";
139 clocks = <&xtal24mhz>;
140 };
141
142 timer1: timer@13000100 {
143 compatible = "arm,integrator-timer";
144 clocks = <&xtal24mhz>;
145 };
146
147 timer2: timer@13000200 {
148 compatible = "arm,integrator-timer";
149 clocks = <&xtal24mhz>;
150 };
151
152 pic: pic@14000000 {
153 valid-mask = <0x003fffff>;
154 };
155
156 pci: pciv3@62000000 {
157 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
158 #interrupt-cells = <1>;
159 #size-cells = <2>;
160 #address-cells = <3>;
161 /* Bridge registers and config access space */
162 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
163 interrupt-parent = <&pic>;
164 interrupts = <17>; /* Bus error IRQ */
165 clocks = <&pciclk>;
166 bus-range = <0x00 0xff>;
167 ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
168 0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
169 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
170 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
171 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
172 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
173 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
174 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
175 0x02000000 0 0x80000000 /* Core module alias memory */
176 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
177 interrupt-map-mask = <0xf800 0 0 0x7>;
178 interrupt-map = <
179 /* IDSEL 9 */
180 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
181 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
182 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
183 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
184 /* IDSEL 10 */
185 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
186 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
187 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
188 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
189 /* IDSEL 11 */
190 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
191 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
192 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
193 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
194 /* IDSEL 12 */
195 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
196 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
197 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
198 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
199 >;
200 };
201
202 fpga {
203 /*
204 * The Integator/AP predates the idea to have magic numbers
205 * identifying the PrimeCell in hardware, thus we have to
206 * supply these from the device tree.
207 */
208 rtc: rtc@15000000 {
209 compatible = "arm,pl030", "arm,primecell";
210 arm,primecell-periphid = <0x00041030>;
211 clocks = <&pclk>;
212 clock-names = "apb_pclk";
213 };
214
215 uart0: uart@16000000 {
216 compatible = "arm,pl010", "arm,primecell";
217 arm,primecell-periphid = <0x00041010>;
218 clocks = <&uartclk>, <&pclk>;
219 clock-names = "uartclk", "apb_pclk";
220 };
221
222 uart1: uart@17000000 {
223 compatible = "arm,pl010", "arm,primecell";
224 arm,primecell-periphid = <0x00041010>;
225 clocks = <&uartclk>, <&pclk>;
226 clock-names = "uartclk", "apb_pclk";
227 };
228
229 kmi0: kmi@18000000 {
230 compatible = "arm,pl050", "arm,primecell";
231 arm,primecell-periphid = <0x00041050>;
232 clocks = <&xtal24mhz>, <&pclk>;
233 clock-names = "KMIREFCLK", "apb_pclk";
234 };
235
236 kmi1: kmi@19000000 {
237 compatible = "arm,pl050", "arm,primecell";
238 arm,primecell-periphid = <0x00041050>;
239 clocks = <&xtal24mhz>, <&pclk>;
240 clock-names = "KMIREFCLK", "apb_pclk";
241 };
242 };
243};
1/*
2 * Device Tree for the ARM Integrator/AP platform
3 */
4
5/dts-v1/;
6/include/ "integrator.dtsi"
7
8/ {
9 model = "ARM Integrator/AP";
10 compatible = "arm,integrator-ap";
11
12 aliases {
13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
15 };
16
17 chosen {
18 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
19 };
20
21 /* 24 MHz chrystal on the core module */
22 xtal24mhz: xtal24mhz@24M {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
26 };
27
28 pclk: pclk@0 {
29 #clock-cells = <0>;
30 compatible = "fixed-factor-clock";
31 clock-div = <1>;
32 clock-mult = <1>;
33 clocks = <&xtal24mhz>;
34 };
35
36 /* The UART clock is 14.74 MHz divided by an ICS525 */
37 uartclk: uartclk@14.74M {
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-frequency = <14745600>;
41 };
42
43 syscon {
44 compatible = "arm,integrator-ap-syscon";
45 reg = <0x11000000 0x100>;
46 interrupt-parent = <&pic>;
47 /* These are the logical module IRQs */
48 interrupts = <9>, <10>, <11>, <12>;
49 };
50
51 timer0: timer@13000000 {
52 compatible = "arm,integrator-timer";
53 clocks = <&xtal24mhz>;
54 };
55
56 timer1: timer@13000100 {
57 compatible = "arm,integrator-timer";
58 clocks = <&xtal24mhz>;
59 };
60
61 timer2: timer@13000200 {
62 compatible = "arm,integrator-timer";
63 clocks = <&xtal24mhz>;
64 };
65
66 pic: pic@14000000 {
67 valid-mask = <0x003fffff>;
68 };
69
70 pci: pciv3@62000000 {
71 compatible = "v3,v360epc-pci";
72 #interrupt-cells = <1>;
73 #size-cells = <2>;
74 #address-cells = <3>;
75 reg = <0x62000000 0x10000>;
76 interrupt-parent = <&pic>;
77 interrupts = <17>; /* Bus error IRQ */
78 ranges = <0x00000000 0 0x61000000 /* config space */
79 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
80 0x01000000 0 0x0 /* I/O space */
81 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
82 0x02000000 0 0x00000000 /* non-prefectable memory */
83 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
84 0x42000000 0 0x10000000 /* prefetchable memory */
85 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
86 interrupt-map-mask = <0xf800 0 0 0x7>;
87 interrupt-map = <
88 /* IDSEL 9 */
89 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
90 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
91 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
92 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
93 /* IDSEL 10 */
94 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
95 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
96 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
97 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
98 /* IDSEL 11 */
99 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
100 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
101 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
102 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
103 /* IDSEL 12 */
104 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
105 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
106 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
107 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
108 >;
109 };
110
111 fpga {
112 /*
113 * The Integator/AP predates the idea to have magic numbers
114 * identifying the PrimeCell in hardware, thus we have to
115 * supply these from the device tree.
116 */
117 rtc: rtc@15000000 {
118 compatible = "arm,pl030", "arm,primecell";
119 arm,primecell-periphid = <0x00041030>;
120 clocks = <&pclk>;
121 clock-names = "apb_pclk";
122 };
123
124 uart0: uart@16000000 {
125 compatible = "arm,pl010", "arm,primecell";
126 arm,primecell-periphid = <0x00041010>;
127 clocks = <&uartclk>, <&pclk>;
128 clock-names = "uartclk", "apb_pclk";
129 };
130
131 uart1: uart@17000000 {
132 compatible = "arm,pl010", "arm,primecell";
133 arm,primecell-periphid = <0x00041010>;
134 clocks = <&uartclk>, <&pclk>;
135 clock-names = "uartclk", "apb_pclk";
136 };
137
138 kmi0: kmi@18000000 {
139 compatible = "arm,pl050", "arm,primecell";
140 arm,primecell-periphid = <0x00041050>;
141 clocks = <&xtal24mhz>, <&pclk>;
142 clock-names = "KMIREFCLK", "apb_pclk";
143 };
144
145 kmi1: kmi@19000000 {
146 compatible = "arm,pl050", "arm,primecell";
147 arm,primecell-periphid = <0x00041050>;
148 clocks = <&xtal24mhz>, <&pclk>;
149 clock-names = "KMIREFCLK", "apb_pclk";
150 };
151 };
152};