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1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include "imx25-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; };
26
27 aliases {
28 ethernet0 = &fec;
29 gpio0 = &gpio1;
30 gpio1 = &gpio2;
31 gpio2 = &gpio3;
32 gpio3 = &gpio4;
33 i2c0 = &i2c1;
34 i2c1 = &i2c2;
35 i2c2 = &i2c3;
36 mmc0 = &esdhc1;
37 mmc1 = &esdhc2;
38 pwm0 = &pwm1;
39 pwm1 = &pwm2;
40 pwm2 = &pwm3;
41 pwm3 = &pwm4;
42 serial0 = &uart1;
43 serial1 = &uart2;
44 serial2 = &uart3;
45 serial3 = &uart4;
46 serial4 = &uart5;
47 spi0 = &spi1;
48 spi1 = &spi2;
49 spi2 = &spi3;
50 usb0 = &usbotg;
51 usb1 = &usbhost1;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu@0 {
59 compatible = "arm,arm926ej-s";
60 device_type = "cpu";
61 reg = <0>;
62 };
63 };
64
65 asic: asic-interrupt-controller@68000000 {
66 compatible = "fsl,imx25-asic", "fsl,avic";
67 interrupt-controller;
68 #interrupt-cells = <1>;
69 reg = <0x68000000 0x8000000>;
70 };
71
72 clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 osc {
77 compatible = "fsl,imx-osc", "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <24000000>;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&asic>;
88 ranges;
89
90 aips@43f00000 { /* AIPS1 */
91 compatible = "fsl,aips-bus", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0x43f00000 0x100000>;
95 ranges;
96
97 aips1: bridge@43f00000 {
98 compatible = "fsl,imx25-aips";
99 reg = <0x43f00000 0x4000>;
100 };
101
102 i2c1: i2c@43f80000 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
106 reg = <0x43f80000 0x4000>;
107 clocks = <&clks 48>;
108 clock-names = "";
109 interrupts = <3>;
110 status = "disabled";
111 };
112
113 i2c3: i2c@43f84000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
117 reg = <0x43f84000 0x4000>;
118 clocks = <&clks 48>;
119 clock-names = "";
120 interrupts = <10>;
121 status = "disabled";
122 };
123
124 can1: can@43f88000 {
125 compatible = "fsl,imx25-flexcan";
126 reg = <0x43f88000 0x4000>;
127 interrupts = <43>;
128 clocks = <&clks 75>, <&clks 75>;
129 clock-names = "ipg", "per";
130 status = "disabled";
131 };
132
133 can2: can@43f8c000 {
134 compatible = "fsl,imx25-flexcan";
135 reg = <0x43f8c000 0x4000>;
136 interrupts = <44>;
137 clocks = <&clks 76>, <&clks 76>;
138 clock-names = "ipg", "per";
139 status = "disabled";
140 };
141
142 uart1: serial@43f90000 {
143 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
144 reg = <0x43f90000 0x4000>;
145 interrupts = <45>;
146 clocks = <&clks 120>, <&clks 57>;
147 clock-names = "ipg", "per";
148 status = "disabled";
149 };
150
151 uart2: serial@43f94000 {
152 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
153 reg = <0x43f94000 0x4000>;
154 interrupts = <32>;
155 clocks = <&clks 121>, <&clks 57>;
156 clock-names = "ipg", "per";
157 status = "disabled";
158 };
159
160 i2c2: i2c@43f98000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
164 reg = <0x43f98000 0x4000>;
165 clocks = <&clks 48>;
166 clock-names = "";
167 interrupts = <4>;
168 status = "disabled";
169 };
170
171 owire@43f9c000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 reg = <0x43f9c000 0x4000>;
175 clocks = <&clks 51>;
176 clock-names = "";
177 interrupts = <2>;
178 status = "disabled";
179 };
180
181 spi1: cspi@43fa4000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
185 reg = <0x43fa4000 0x4000>;
186 clocks = <&clks 78>, <&clks 78>;
187 clock-names = "ipg", "per";
188 interrupts = <14>;
189 status = "disabled";
190 };
191
192 kpp: kpp@43fa8000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
196 reg = <0x43fa8000 0x4000>;
197 clocks = <&clks 102>;
198 clock-names = "";
199 interrupts = <24>;
200 status = "disabled";
201 };
202
203 iomuxc: iomuxc@43fac000 {
204 compatible = "fsl,imx25-iomuxc";
205 reg = <0x43fac000 0x4000>;
206 };
207
208 audmux: audmux@43fb0000 {
209 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
210 reg = <0x43fb0000 0x4000>;
211 status = "disabled";
212 };
213 };
214
215 spba@50000000 {
216 compatible = "fsl,spba-bus", "simple-bus";
217 #address-cells = <1>;
218 #size-cells = <1>;
219 reg = <0x50000000 0x40000>;
220 ranges;
221
222 spi3: cspi@50004000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
226 reg = <0x50004000 0x4000>;
227 interrupts = <0>;
228 clocks = <&clks 80>, <&clks 80>;
229 clock-names = "ipg", "per";
230 status = "disabled";
231 };
232
233 uart4: serial@50008000 {
234 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
235 reg = <0x50008000 0x4000>;
236 interrupts = <5>;
237 clocks = <&clks 123>, <&clks 57>;
238 clock-names = "ipg", "per";
239 status = "disabled";
240 };
241
242 uart3: serial@5000c000 {
243 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
244 reg = <0x5000c000 0x4000>;
245 interrupts = <18>;
246 clocks = <&clks 122>, <&clks 57>;
247 clock-names = "ipg", "per";
248 status = "disabled";
249 };
250
251 spi2: cspi@50010000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
255 reg = <0x50010000 0x4000>;
256 clocks = <&clks 79>, <&clks 79>;
257 clock-names = "ipg", "per";
258 interrupts = <13>;
259 status = "disabled";
260 };
261
262 ssi2: ssi@50014000 {
263 #sound-dai-cells = <0>;
264 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
265 reg = <0x50014000 0x4000>;
266 interrupts = <11>;
267 clocks = <&clks 118>;
268 clock-names = "ipg";
269 dmas = <&sdma 24 1 0>,
270 <&sdma 25 1 0>;
271 dma-names = "rx", "tx";
272 fsl,fifo-depth = <15>;
273 status = "disabled";
274 };
275
276 esai@50018000 {
277 reg = <0x50018000 0x4000>;
278 interrupts = <7>;
279 };
280
281 uart5: serial@5002c000 {
282 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
283 reg = <0x5002c000 0x4000>;
284 interrupts = <40>;
285 clocks = <&clks 124>, <&clks 57>;
286 clock-names = "ipg", "per";
287 status = "disabled";
288 };
289
290 tscadc: tscadc@50030000 {
291 compatible = "fsl,imx25-tsadc";
292 reg = <0x50030000 0xc>;
293 interrupts = <46>;
294 clocks = <&clks 119>;
295 clock-names = "ipg";
296 interrupt-controller;
297 #interrupt-cells = <1>;
298 #address-cells = <1>;
299 #size-cells = <1>;
300 status = "disabled";
301 ranges;
302
303 adc: adc@50030800 {
304 compatible = "fsl,imx25-gcq";
305 reg = <0x50030800 0x60>;
306 interrupt-parent = <&tscadc>;
307 interrupts = <1>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 status = "disabled";
311 };
312
313 tsc: tcq@50030400 {
314 compatible = "fsl,imx25-tcq";
315 reg = <0x50030400 0x60>;
316 interrupt-parent = <&tscadc>;
317 interrupts = <0>;
318 fsl,wires = <4>;
319 status = "disabled";
320 };
321 };
322
323 ssi1: ssi@50034000 {
324 #sound-dai-cells = <0>;
325 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
326 reg = <0x50034000 0x4000>;
327 interrupts = <12>;
328 clocks = <&clks 117>;
329 clock-names = "ipg";
330 dmas = <&sdma 28 1 0>,
331 <&sdma 29 1 0>;
332 dma-names = "rx", "tx";
333 fsl,fifo-depth = <15>;
334 status = "disabled";
335 };
336
337 fec: ethernet@50038000 {
338 compatible = "fsl,imx25-fec";
339 reg = <0x50038000 0x4000>;
340 interrupts = <57>;
341 clocks = <&clks 88>, <&clks 65>;
342 clock-names = "ipg", "ahb";
343 status = "disabled";
344 };
345 };
346
347 aips@53f00000 { /* AIPS2 */
348 compatible = "fsl,aips-bus", "simple-bus";
349 #address-cells = <1>;
350 #size-cells = <1>;
351 reg = <0x53f00000 0x100000>;
352 ranges;
353
354 aips2: bridge@53f00000 {
355 compatible = "fsl,imx25-aips";
356 reg = <0x53f00000 0x4000>;
357 };
358
359 clks: ccm@53f80000 {
360 compatible = "fsl,imx25-ccm";
361 reg = <0x53f80000 0x4000>;
362 interrupts = <31>;
363 #clock-cells = <1>;
364 };
365
366 gpt4: timer@53f84000 {
367 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
368 reg = <0x53f84000 0x4000>;
369 clocks = <&clks 95>, <&clks 47>;
370 clock-names = "ipg", "per";
371 interrupts = <1>;
372 };
373
374 gpt3: timer@53f88000 {
375 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
376 reg = <0x53f88000 0x4000>;
377 clocks = <&clks 94>, <&clks 47>;
378 clock-names = "ipg", "per";
379 interrupts = <29>;
380 };
381
382 gpt2: timer@53f8c000 {
383 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
384 reg = <0x53f8c000 0x4000>;
385 clocks = <&clks 93>, <&clks 47>;
386 clock-names = "ipg", "per";
387 interrupts = <53>;
388 };
389
390 gpt1: timer@53f90000 {
391 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
392 reg = <0x53f90000 0x4000>;
393 clocks = <&clks 92>, <&clks 47>;
394 clock-names = "ipg", "per";
395 interrupts = <54>;
396 };
397
398 epit1: timer@53f94000 {
399 compatible = "fsl,imx25-epit";
400 reg = <0x53f94000 0x4000>;
401 interrupts = <28>;
402 };
403
404 epit2: timer@53f98000 {
405 compatible = "fsl,imx25-epit";
406 reg = <0x53f98000 0x4000>;
407 interrupts = <27>;
408 };
409
410 gpio4: gpio@53f9c000 {
411 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
412 reg = <0x53f9c000 0x4000>;
413 interrupts = <23>;
414 gpio-controller;
415 #gpio-cells = <2>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 };
419
420 pwm2: pwm@53fa0000 {
421 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
422 #pwm-cells = <2>;
423 reg = <0x53fa0000 0x4000>;
424 clocks = <&clks 106>, <&clks 52>;
425 clock-names = "ipg", "per";
426 interrupts = <36>;
427 };
428
429 gpio3: gpio@53fa4000 {
430 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
431 reg = <0x53fa4000 0x4000>;
432 interrupts = <16>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 };
438
439 pwm3: pwm@53fa8000 {
440 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
441 #pwm-cells = <2>;
442 reg = <0x53fa8000 0x4000>;
443 clocks = <&clks 107>, <&clks 52>;
444 clock-names = "ipg", "per";
445 interrupts = <41>;
446 };
447
448 scc: crypto@53fac000 {
449 compatible = "fsl,imx25-scc";
450 reg = <0x53fac000 0x4000>;
451 clocks = <&clks 111>;
452 clock-names = "ipg";
453 interrupts = <49>, <50>;
454 interrupt-names = "scm", "smn";
455 };
456
457 rngb: rngb@53fb0000 {
458 compatible = "fsl,imx25-rngb";
459 reg = <0x53fb0000 0x4000>;
460 clocks = <&clks 109>;
461 interrupts = <22>;
462 };
463
464 esdhc1: esdhc@53fb4000 {
465 compatible = "fsl,imx25-esdhc";
466 reg = <0x53fb4000 0x4000>;
467 interrupts = <9>;
468 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
469 clock-names = "ipg", "ahb", "per";
470 status = "disabled";
471 };
472
473 esdhc2: esdhc@53fb8000 {
474 compatible = "fsl,imx25-esdhc";
475 reg = <0x53fb8000 0x4000>;
476 interrupts = <8>;
477 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
478 clock-names = "ipg", "ahb", "per";
479 status = "disabled";
480 };
481
482 lcdc: lcdc@53fbc000 {
483 compatible = "fsl,imx25-fb", "fsl,imx21-fb";
484 reg = <0x53fbc000 0x4000>;
485 interrupts = <39>;
486 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
487 clock-names = "ipg", "ahb", "per";
488 status = "disabled";
489 };
490
491 slcdc@53fc0000 {
492 reg = <0x53fc0000 0x4000>;
493 interrupts = <38>;
494 status = "disabled";
495 };
496
497 pwm4: pwm@53fc8000 {
498 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
499 #pwm-cells = <2>;
500 reg = <0x53fc8000 0x4000>;
501 clocks = <&clks 108>, <&clks 52>;
502 clock-names = "ipg", "per";
503 interrupts = <42>;
504 };
505
506 gpio1: gpio@53fcc000 {
507 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
508 reg = <0x53fcc000 0x4000>;
509 interrupts = <52>;
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 };
515
516 gpio2: gpio@53fd0000 {
517 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
518 reg = <0x53fd0000 0x4000>;
519 interrupts = <51>;
520 gpio-controller;
521 #gpio-cells = <2>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
524 };
525
526 sdma: sdma@53fd4000 {
527 compatible = "fsl,imx25-sdma";
528 reg = <0x53fd4000 0x4000>;
529 clocks = <&clks 112>, <&clks 68>;
530 clock-names = "ipg", "ahb";
531 #dma-cells = <3>;
532 interrupts = <34>;
533 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
534 };
535
536 wdog@53fdc000 {
537 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
538 reg = <0x53fdc000 0x4000>;
539 clocks = <&clks 126>;
540 clock-names = "";
541 interrupts = <55>;
542 };
543
544 pwm1: pwm@53fe0000 {
545 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
546 #pwm-cells = <2>;
547 reg = <0x53fe0000 0x4000>;
548 clocks = <&clks 105>, <&clks 52>;
549 clock-names = "ipg", "per";
550 interrupts = <26>;
551 };
552
553 iim: iim@53ff0000 {
554 compatible = "fsl,imx25-iim", "fsl,imx27-iim";
555 reg = <0x53ff0000 0x4000>;
556 interrupts = <19>;
557 clocks = <&clks 99>;
558 };
559
560 usbotg: usb@53ff4000 {
561 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
562 reg = <0x53ff4000 0x0200>;
563 interrupts = <37>;
564 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
565 clock-names = "ipg", "ahb", "per";
566 fsl,usbmisc = <&usbmisc 0>;
567 fsl,usbphy = <&usbphy0>;
568 phy_type = "utmi";
569 dr_mode = "otg";
570 status = "disabled";
571 };
572
573 usbhost1: usb@53ff4400 {
574 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
575 reg = <0x53ff4400 0x0200>;
576 interrupts = <35>;
577 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
578 clock-names = "ipg", "ahb", "per";
579 fsl,usbmisc = <&usbmisc 1>;
580 fsl,usbphy = <&usbphy1>;
581 status = "disabled";
582 };
583
584 usbmisc: usbmisc@53ff4600 {
585 #index-cells = <1>;
586 compatible = "fsl,imx25-usbmisc";
587 reg = <0x53ff4600 0x00f>;
588 };
589
590 dryice@53ffc000 {
591 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
592 reg = <0x53ffc000 0x4000>;
593 clocks = <&clks 81>;
594 clock-names = "ipg";
595 interrupts = <25 56>;
596 };
597 };
598
599 iram: sram@78000000 {
600 compatible = "mmio-sram";
601 reg = <0x78000000 0x20000>;
602 };
603
604 emi@80000000 {
605 compatible = "fsl,emi-bus", "simple-bus";
606 #address-cells = <1>;
607 #size-cells = <1>;
608 reg = <0x80000000 0x3b002000>;
609 ranges;
610
611 nfc: nand@bb000000 {
612 #address-cells = <1>;
613 #size-cells = <1>;
614
615 compatible = "fsl,imx25-nand";
616 reg = <0xbb000000 0x2000>;
617 clocks = <&clks 50>;
618 clock-names = "";
619 interrupts = <33>;
620 status = "disabled";
621 };
622 };
623 };
624
625 usbphy {
626 compatible = "simple-bus";
627 #address-cells = <1>;
628 #size-cells = <0>;
629
630 usbphy0: usb-phy@0 {
631 reg = <0>;
632 compatible = "usb-nop-xceiv";
633 #phy-cells = <0>;
634 };
635
636 usbphy1: usb-phy@1 {
637 reg = <1>;
638 compatible = "usb-nop-xceiv";
639 #phy-cells = <0>;
640 };
641 };
642};
1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "skeleton.dtsi"
13#include "imx25-pinfunc.h"
14
15/ {
16 aliases {
17 gpio0 = &gpio1;
18 gpio1 = &gpio2;
19 gpio2 = &gpio3;
20 gpio3 = &gpio4;
21 i2c0 = &i2c1;
22 i2c1 = &i2c2;
23 i2c2 = &i2c3;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 spi0 = &spi1;
30 spi1 = &spi2;
31 spi2 = &spi3;
32 usb0 = &usbotg;
33 usb1 = &usbhost1;
34 };
35
36 cpus {
37 #address-cells = <0>;
38 #size-cells = <0>;
39
40 cpu {
41 compatible = "arm,arm926ej-s";
42 device_type = "cpu";
43 };
44 };
45
46 asic: asic-interrupt-controller@68000000 {
47 compatible = "fsl,imx25-asic", "fsl,avic";
48 interrupt-controller;
49 #interrupt-cells = <1>;
50 reg = <0x68000000 0x8000000>;
51 };
52
53 clocks {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 osc {
58 compatible = "fsl,imx-osc", "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <24000000>;
61 };
62 };
63
64 soc {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "simple-bus";
68 interrupt-parent = <&asic>;
69 ranges;
70
71 aips@43f00000 { /* AIPS1 */
72 compatible = "fsl,aips-bus", "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 reg = <0x43f00000 0x100000>;
76 ranges;
77
78 i2c1: i2c@43f80000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
82 reg = <0x43f80000 0x4000>;
83 clocks = <&clks 48>;
84 clock-names = "";
85 interrupts = <3>;
86 status = "disabled";
87 };
88
89 i2c3: i2c@43f84000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
93 reg = <0x43f84000 0x4000>;
94 clocks = <&clks 48>;
95 clock-names = "";
96 interrupts = <10>;
97 status = "disabled";
98 };
99
100 can1: can@43f88000 {
101 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
102 reg = <0x43f88000 0x4000>;
103 interrupts = <43>;
104 clocks = <&clks 75>, <&clks 75>;
105 clock-names = "ipg", "per";
106 status = "disabled";
107 };
108
109 can2: can@43f8c000 {
110 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
111 reg = <0x43f8c000 0x4000>;
112 interrupts = <44>;
113 clocks = <&clks 76>, <&clks 76>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
118 uart1: serial@43f90000 {
119 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
120 reg = <0x43f90000 0x4000>;
121 interrupts = <45>;
122 clocks = <&clks 120>, <&clks 57>;
123 clock-names = "ipg", "per";
124 status = "disabled";
125 };
126
127 uart2: serial@43f94000 {
128 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
129 reg = <0x43f94000 0x4000>;
130 interrupts = <32>;
131 clocks = <&clks 121>, <&clks 57>;
132 clock-names = "ipg", "per";
133 status = "disabled";
134 };
135
136 i2c2: i2c@43f98000 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
140 reg = <0x43f98000 0x4000>;
141 clocks = <&clks 48>;
142 clock-names = "";
143 interrupts = <4>;
144 status = "disabled";
145 };
146
147 owire@43f9c000 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 reg = <0x43f9c000 0x4000>;
151 clocks = <&clks 51>;
152 clock-names = "";
153 interrupts = <2>;
154 status = "disabled";
155 };
156
157 spi1: cspi@43fa4000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
161 reg = <0x43fa4000 0x4000>;
162 clocks = <&clks 62>, <&clks 62>;
163 clock-names = "ipg", "per";
164 interrupts = <14>;
165 status = "disabled";
166 };
167
168 kpp@43fa8000 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 reg = <0x43fa8000 0x4000>;
172 clocks = <&clks 102>;
173 clock-names = "";
174 interrupts = <24>;
175 status = "disabled";
176 };
177
178 iomuxc: iomuxc@43fac000 {
179 compatible = "fsl,imx25-iomuxc";
180 reg = <0x43fac000 0x4000>;
181 };
182
183 audmux: audmux@43fb0000 {
184 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
185 reg = <0x43fb0000 0x4000>;
186 status = "disabled";
187 };
188 };
189
190 spba@50000000 {
191 compatible = "fsl,spba-bus", "simple-bus";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 reg = <0x50000000 0x40000>;
195 ranges;
196
197 spi3: cspi@50004000 {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
201 reg = <0x50004000 0x4000>;
202 interrupts = <0>;
203 clocks = <&clks 80>, <&clks 80>;
204 clock-names = "ipg", "per";
205 status = "disabled";
206 };
207
208 uart4: serial@50008000 {
209 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
210 reg = <0x50008000 0x4000>;
211 interrupts = <5>;
212 clocks = <&clks 123>, <&clks 57>;
213 clock-names = "ipg", "per";
214 status = "disabled";
215 };
216
217 uart3: serial@5000c000 {
218 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
219 reg = <0x5000c000 0x4000>;
220 interrupts = <18>;
221 clocks = <&clks 122>, <&clks 57>;
222 clock-names = "ipg", "per";
223 status = "disabled";
224 };
225
226 spi2: cspi@50010000 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
230 reg = <0x50010000 0x4000>;
231 clocks = <&clks 79>, <&clks 79>;
232 clock-names = "ipg", "per";
233 interrupts = <13>;
234 status = "disabled";
235 };
236
237 ssi2: ssi@50014000 {
238 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
239 reg = <0x50014000 0x4000>;
240 interrupts = <11>;
241 clocks = <&clks 118>;
242 clock-names = "ipg";
243 dmas = <&sdma 24 1 0>,
244 <&sdma 25 1 0>;
245 dma-names = "rx", "tx";
246 status = "disabled";
247 };
248
249 esai@50018000 {
250 reg = <0x50018000 0x4000>;
251 interrupts = <7>;
252 };
253
254 uart5: serial@5002c000 {
255 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
256 reg = <0x5002c000 0x4000>;
257 interrupts = <40>;
258 clocks = <&clks 124>, <&clks 57>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
262
263 tsc: tsc@50030000 {
264 compatible = "fsl,imx25-adc", "fsl,imx21-tsc";
265 reg = <0x50030000 0x4000>;
266 interrupts = <46>;
267 clocks = <&clks 119>;
268 clock-names = "ipg";
269 status = "disabled";
270 };
271
272 ssi1: ssi@50034000 {
273 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
274 reg = <0x50034000 0x4000>;
275 interrupts = <12>;
276 clocks = <&clks 117>;
277 clock-names = "ipg";
278 dmas = <&sdma 28 1 0>,
279 <&sdma 29 1 0>;
280 dma-names = "rx", "tx";
281 status = "disabled";
282 };
283
284 fec: ethernet@50038000 {
285 compatible = "fsl,imx25-fec";
286 reg = <0x50038000 0x4000>;
287 interrupts = <57>;
288 clocks = <&clks 88>, <&clks 65>;
289 clock-names = "ipg", "ahb";
290 status = "disabled";
291 };
292 };
293
294 aips@53f00000 { /* AIPS2 */
295 compatible = "fsl,aips-bus", "simple-bus";
296 #address-cells = <1>;
297 #size-cells = <1>;
298 reg = <0x53f00000 0x100000>;
299 ranges;
300
301 clks: ccm@53f80000 {
302 compatible = "fsl,imx25-ccm";
303 reg = <0x53f80000 0x4000>;
304 interrupts = <31>;
305 #clock-cells = <1>;
306 };
307
308 gpt4: timer@53f84000 {
309 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
310 reg = <0x53f84000 0x4000>;
311 clocks = <&clks 9>, <&clks 45>;
312 clock-names = "ipg", "per";
313 interrupts = <1>;
314 };
315
316 gpt3: timer@53f88000 {
317 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
318 reg = <0x53f88000 0x4000>;
319 clocks = <&clks 9>, <&clks 47>;
320 clock-names = "ipg", "per";
321 interrupts = <29>;
322 };
323
324 gpt2: timer@53f8c000 {
325 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
326 reg = <0x53f8c000 0x4000>;
327 clocks = <&clks 9>, <&clks 47>;
328 clock-names = "ipg", "per";
329 interrupts = <53>;
330 };
331
332 gpt1: timer@53f90000 {
333 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
334 reg = <0x53f90000 0x4000>;
335 clocks = <&clks 9>, <&clks 47>;
336 clock-names = "ipg", "per";
337 interrupts = <54>;
338 };
339
340 epit1: timer@53f94000 {
341 compatible = "fsl,imx25-epit";
342 reg = <0x53f94000 0x4000>;
343 interrupts = <28>;
344 };
345
346 epit2: timer@53f98000 {
347 compatible = "fsl,imx25-epit";
348 reg = <0x53f98000 0x4000>;
349 interrupts = <27>;
350 };
351
352 gpio4: gpio@53f9c000 {
353 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
354 reg = <0x53f9c000 0x4000>;
355 interrupts = <23>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 };
361
362 pwm2: pwm@53fa0000 {
363 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
364 #pwm-cells = <2>;
365 reg = <0x53fa0000 0x4000>;
366 clocks = <&clks 106>, <&clks 36>;
367 clock-names = "ipg", "per";
368 interrupts = <36>;
369 };
370
371 gpio3: gpio@53fa4000 {
372 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
373 reg = <0x53fa4000 0x4000>;
374 interrupts = <16>;
375 gpio-controller;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 };
380
381 pwm3: pwm@53fa8000 {
382 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
383 #pwm-cells = <2>;
384 reg = <0x53fa8000 0x4000>;
385 clocks = <&clks 107>, <&clks 36>;
386 clock-names = "ipg", "per";
387 interrupts = <41>;
388 };
389
390 esdhc1: esdhc@53fb4000 {
391 compatible = "fsl,imx25-esdhc";
392 reg = <0x53fb4000 0x4000>;
393 interrupts = <9>;
394 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
395 clock-names = "ipg", "ahb", "per";
396 status = "disabled";
397 };
398
399 esdhc2: esdhc@53fb8000 {
400 compatible = "fsl,imx25-esdhc";
401 reg = <0x53fb8000 0x4000>;
402 interrupts = <8>;
403 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
404 clock-names = "ipg", "ahb", "per";
405 status = "disabled";
406 };
407
408 lcdc: lcdc@53fbc000 {
409 compatible = "fsl,imx25-fb", "fsl,imx21-fb";
410 reg = <0x53fbc000 0x4000>;
411 interrupts = <39>;
412 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
413 clock-names = "ipg", "ahb", "per";
414 status = "disabled";
415 };
416
417 slcdc@53fc0000 {
418 reg = <0x53fc0000 0x4000>;
419 interrupts = <38>;
420 status = "disabled";
421 };
422
423 pwm4: pwm@53fc8000 {
424 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
425 reg = <0x53fc8000 0x4000>;
426 clocks = <&clks 108>, <&clks 36>;
427 clock-names = "ipg", "per";
428 interrupts = <42>;
429 };
430
431 gpio1: gpio@53fcc000 {
432 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
433 reg = <0x53fcc000 0x4000>;
434 interrupts = <52>;
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 };
440
441 gpio2: gpio@53fd0000 {
442 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
443 reg = <0x53fd0000 0x4000>;
444 interrupts = <51>;
445 gpio-controller;
446 #gpio-cells = <2>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
449 };
450
451 sdma: sdma@53fd4000 {
452 compatible = "fsl,imx25-sdma", "fsl,imx35-sdma";
453 reg = <0x53fd4000 0x4000>;
454 clocks = <&clks 112>, <&clks 68>;
455 clock-names = "ipg", "ahb";
456 #dma-cells = <3>;
457 interrupts = <34>;
458 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
459 };
460
461 wdog@53fdc000 {
462 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
463 reg = <0x53fdc000 0x4000>;
464 clocks = <&clks 126>;
465 clock-names = "";
466 interrupts = <55>;
467 };
468
469 pwm1: pwm@53fe0000 {
470 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
471 #pwm-cells = <2>;
472 reg = <0x53fe0000 0x4000>;
473 clocks = <&clks 105>, <&clks 36>;
474 clock-names = "ipg", "per";
475 interrupts = <26>;
476 };
477
478 iim: iim@53ff0000 {
479 compatible = "fsl,imx25-iim", "fsl,imx27-iim";
480 reg = <0x53ff0000 0x4000>;
481 interrupts = <19>;
482 clocks = <&clks 99>;
483 };
484
485 usbphy1: usbphy@1 {
486 compatible = "nop-usbphy";
487 status = "disabled";
488 };
489
490 usbphy2: usbphy@2 {
491 compatible = "nop-usbphy";
492 status = "disabled";
493 };
494
495 usbotg: usb@53ff4000 {
496 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
497 reg = <0x53ff4000 0x0200>;
498 interrupts = <37>;
499 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
500 clock-names = "ipg", "ahb", "per";
501 fsl,usbmisc = <&usbmisc 0>;
502 status = "disabled";
503 };
504
505 usbhost1: usb@53ff4400 {
506 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
507 reg = <0x53ff4400 0x0200>;
508 interrupts = <35>;
509 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
510 clock-names = "ipg", "ahb", "per";
511 fsl,usbmisc = <&usbmisc 1>;
512 status = "disabled";
513 };
514
515 usbmisc: usbmisc@53ff4600 {
516 #index-cells = <1>;
517 compatible = "fsl,imx25-usbmisc";
518 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
519 clock-names = "ipg", "ahb", "per";
520 reg = <0x53ff4600 0x00f>;
521 status = "disabled";
522 };
523
524 dryice@53ffc000 {
525 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
526 reg = <0x53ffc000 0x4000>;
527 clocks = <&clks 81>;
528 clock-names = "ipg";
529 interrupts = <25>;
530 };
531 };
532
533 emi@80000000 {
534 compatible = "fsl,emi-bus", "simple-bus";
535 #address-cells = <1>;
536 #size-cells = <1>;
537 reg = <0x80000000 0x3b002000>;
538 ranges;
539
540 nfc: nand@bb000000 {
541 #address-cells = <1>;
542 #size-cells = <1>;
543
544 compatible = "fsl,imx25-nand";
545 reg = <0xbb000000 0x2000>;
546 clocks = <&clks 50>;
547 clock-names = "";
548 interrupts = <33>;
549 status = "disabled";
550 };
551 };
552 };
553};