Loading...
Note: File does not exist in v3.15.
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx1-pinfunc.h"
13
14#include <dt-bindings/clock/imx1-clock.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/interrupt-controller/irq.h>
17
18/ {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 /*
22 * The decompressor and also some bootloaders rely on a
23 * pre-existing /chosen node to be available to insert the
24 * command line and merge other ATAGS info.
25 * Also for U-Boot there must be a pre-existing /memory node.
26 */
27 chosen {};
28 memory { device_type = "memory"; };
29
30 aliases {
31 gpio0 = &gpio1;
32 gpio1 = &gpio2;
33 gpio2 = &gpio3;
34 gpio3 = &gpio4;
35 i2c0 = &i2c;
36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 spi0 = &cspi1;
40 spi1 = &cspi2;
41 };
42
43 aitc: aitc-interrupt-controller@223000 {
44 compatible = "fsl,imx1-aitc", "fsl,avic";
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 reg = <0x00223000 0x1000>;
48 };
49
50 cpus {
51 #size-cells = <0>;
52 #address-cells = <1>;
53
54 cpu@0 {
55 device_type = "cpu";
56 reg = <0>;
57 compatible = "arm,arm920t";
58 operating-points = <200000 1900000>;
59 clock-latency = <62500>;
60 clocks = <&clks IMX1_CLK_MCU>;
61 voltage-tolerance = <5>;
62 };
63 };
64
65 soc {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "simple-bus";
69 interrupt-parent = <&aitc>;
70 ranges;
71
72 aipi@200000 {
73 compatible = "fsl,aipi-bus", "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x00200000 0x10000>;
77 ranges;
78
79 gpt1: timer@202000 {
80 compatible = "fsl,imx1-gpt";
81 reg = <0x00202000 0x1000>;
82 interrupts = <59>;
83 clocks = <&clks IMX1_CLK_HCLK>,
84 <&clks IMX1_CLK_PER1>;
85 clock-names = "ipg", "per";
86 };
87
88 gpt2: timer@203000 {
89 compatible = "fsl,imx1-gpt";
90 reg = <0x00203000 0x1000>;
91 interrupts = <58>;
92 clocks = <&clks IMX1_CLK_HCLK>,
93 <&clks IMX1_CLK_PER1>;
94 clock-names = "ipg", "per";
95 };
96
97 fb: fb@205000 {
98 compatible = "fsl,imx1-fb";
99 reg = <0x00205000 0x1000>;
100 interrupts = <14>;
101 clocks = <&clks IMX1_CLK_DUMMY>,
102 <&clks IMX1_CLK_DUMMY>,
103 <&clks IMX1_CLK_PER2>;
104 clock-names = "ipg", "ahb", "per";
105 status = "disabled";
106 };
107
108 uart1: serial@206000 {
109 compatible = "fsl,imx1-uart";
110 reg = <0x00206000 0x1000>;
111 interrupts = <30 29 26>;
112 clocks = <&clks IMX1_CLK_HCLK>,
113 <&clks IMX1_CLK_PER1>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
118 uart2: serial@207000 {
119 compatible = "fsl,imx1-uart";
120 reg = <0x00207000 0x1000>;
121 interrupts = <24 23 20>;
122 clocks = <&clks IMX1_CLK_HCLK>,
123 <&clks IMX1_CLK_PER1>;
124 clock-names = "ipg", "per";
125 status = "disabled";
126 };
127
128 pwm: pwm@208000 {
129 #pwm-cells = <2>;
130 compatible = "fsl,imx1-pwm";
131 reg = <0x00208000 0x1000>;
132 interrupts = <34>;
133 clocks = <&clks IMX1_CLK_DUMMY>,
134 <&clks IMX1_CLK_PER1>;
135 clock-names = "ipg", "per";
136 };
137
138 dma: dma@209000 {
139 compatible = "fsl,imx1-dma";
140 reg = <0x00209000 0x1000>;
141 interrupts = <61 60>;
142 clocks = <&clks IMX1_CLK_HCLK>,
143 <&clks IMX1_CLK_DMA_GATE>;
144 clock-names = "ipg", "ahb";
145 #dma-cells = <1>;
146 };
147
148 uart3: serial@20a000 {
149 compatible = "fsl,imx1-uart";
150 reg = <0x0020a000 0x1000>;
151 interrupts = <54 4 1>;
152 clocks = <&clks IMX1_CLK_UART3_GATE>,
153 <&clks IMX1_CLK_PER1>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
157 };
158
159 aipi@210000 {
160 compatible = "fsl,aipi-bus", "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 reg = <0x00210000 0x10000>;
164 ranges;
165
166 cspi1: cspi@213000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "fsl,imx1-cspi";
170 reg = <0x00213000 0x1000>;
171 interrupts = <41>;
172 clocks = <&clks IMX1_CLK_DUMMY>,
173 <&clks IMX1_CLK_PER1>;
174 clock-names = "ipg", "per";
175 status = "disabled";
176 };
177
178 i2c: i2c@217000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,imx1-i2c";
182 reg = <0x00217000 0x1000>;
183 interrupts = <39>;
184 clocks = <&clks IMX1_CLK_HCLK>;
185 status = "disabled";
186 };
187
188 cspi2: cspi@219000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,imx1-cspi";
192 reg = <0x00219000 0x1000>;
193 interrupts = <40>;
194 clocks = <&clks IMX1_CLK_DUMMY>,
195 <&clks IMX1_CLK_PER1>;
196 clock-names = "ipg", "per";
197 status = "disabled";
198 };
199
200 clks: ccm@21b000 {
201 compatible = "fsl,imx1-ccm";
202 reg = <0x0021b000 0x1000>;
203 #clock-cells = <1>;
204 };
205
206 iomuxc: iomuxc@21c000 {
207 compatible = "fsl,imx1-iomuxc";
208 reg = <0x0021c000 0x1000>;
209 #address-cells = <1>;
210 #size-cells = <1>;
211 ranges;
212
213 gpio1: gpio@21c000 {
214 compatible = "fsl,imx1-gpio";
215 reg = <0x0021c000 0x100>;
216 interrupts = <11>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 };
222
223 gpio2: gpio@21c100 {
224 compatible = "fsl,imx1-gpio";
225 reg = <0x0021c100 0x100>;
226 interrupts = <12>;
227 gpio-controller;
228 #gpio-cells = <2>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 };
232
233 gpio3: gpio@21c200 {
234 compatible = "fsl,imx1-gpio";
235 reg = <0x0021c200 0x100>;
236 interrupts = <13>;
237 gpio-controller;
238 #gpio-cells = <2>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 };
242
243 gpio4: gpio@21c300 {
244 compatible = "fsl,imx1-gpio";
245 reg = <0x0021c300 0x100>;
246 interrupts = <62>;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252 };
253 };
254
255 weim: weim@220000 {
256 #address-cells = <2>;
257 #size-cells = <1>;
258 compatible = "fsl,imx1-weim";
259 reg = <0x00220000 0x1000>;
260 clocks = <&clks IMX1_CLK_DUMMY>;
261 ranges = <
262 0 0 0x10000000 0x02000000
263 1 0 0x12000000 0x01000000
264 2 0 0x13000000 0x01000000
265 3 0 0x14000000 0x01000000
266 4 0 0x15000000 0x01000000
267 5 0 0x16000000 0x01000000
268 >;
269 status = "disabled";
270 };
271
272 esram: esram@300000 {
273 compatible = "mmio-sram";
274 reg = <0x00300000 0x20000>;
275 };
276 };
277};