1/*
 2 * Device Tree file for Marvell Armada 385 Reference Design board
 3 * (RD-88F6820-AP)
 4 *
 5 *  Copyright (C) 2014 Marvell
 6 *
 7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2.  This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16#include "armada-385.dtsi"
17
18/ {
19	model = "Marvell Armada 385 Reference Design";
20	compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
21
22	chosen {
23		bootargs = "console=ttyS0,115200 earlyprintk";
24	};
25
26	memory {
27		device_type = "memory";
28		reg = <0x00000000 0x10000000>; /* 256 MB */
29	};
30
31	soc {
32		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
34
35		internal-regs {
36			spi@10600 {
37				status = "okay";
38
39				spi-flash@0 {
40					#address-cells = <1>;
41					#size-cells = <1>;
42					compatible = "st,m25p128";
43					reg = <0>; /* Chip select 0 */
44					spi-max-frequency = <108000000>;
45				};
46			};
47
48			i2c@11000 {
49				status = "okay";
50				clock-frequency = <100000>;
51			};
52
53			serial@12000 {
54				clock-frequency = <200000000>;
55				status = "okay";
56			};
57
58			ethernet@30000 {
59				status = "okay";
60				phy = <&phy0>;
61				phy-mode = "rgmii-id";
62			};
63
64			ethernet@70000 {
65				status = "okay";
66				phy = <&phy1>;
67				phy-mode = "rgmii-id";
68			};
69
70
71			mdio {
72				phy0: ethernet-phy@0 {
73					reg = <0>;
74				};
75
76				phy1: ethernet-phy@1 {
77					reg = <1>;
78				};
79			};
80		};
81
82		pcie-controller {
83			status = "okay";
84			/*
85			 * One PCIe units is accessible through
86			 * standard PCIe slot on the board.
87			 */
88			pcie@1,0 {
89				/* Port 0, Lane 0 */
90				status = "okay";
91			};
92		};
93	};
94};