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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * 2011 - 2014 (C) Xilinx Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/console.h>
19#include <linux/serial_core.h>
20#include <linux/slab.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/clk.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/of.h>
27#include <linux/module.h>
28#include <linux/pm_runtime.h>
29
30#define CDNS_UART_TTY_NAME "ttyPS"
31#define CDNS_UART_NAME "xuartps"
32#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
33#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
34#define CDNS_UART_NR_PORTS 2
35#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
36#define CDNS_UART_REGISTER_SPACE 0x1000
37
38/* Rx Trigger level */
39static int rx_trigger_level = 56;
40module_param(rx_trigger_level, uint, S_IRUGO);
41MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42
43/* Rx Timeout */
44static int rx_timeout = 10;
45module_param(rx_timeout, uint, S_IRUGO);
46MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
47
48/* Register offsets for the UART. */
49#define CDNS_UART_CR 0x00 /* Control Register */
50#define CDNS_UART_MR 0x04 /* Mode Register */
51#define CDNS_UART_IER 0x08 /* Interrupt Enable */
52#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54#define CDNS_UART_ISR 0x14 /* Interrupt Status */
55#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60#define CDNS_UART_SR 0x2C /* Channel Status */
61#define CDNS_UART_FIFO 0x30 /* FIFO */
62#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
68
69/* Control Register Bit Definitions */
70#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
93
94#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96
97#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102
103#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106
107/*
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
117 */
118#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
129
130 /*
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
140 */
141
142#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
145 CDNS_UART_IXR_TOUT)
146
147/* Goes in read_status_mask for break detection as the HW doesn't do it*/
148#define CDNS_UART_IXR_BRK 0x00002000
149
150#define CDNS_UART_RXBS_SUPPORT BIT(1)
151/*
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
155 */
156#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159
160/*
161 * Channel Status Register:
162 * The channel status register (CSR) is provided to enable the control logic
163 * to monitor the status of bits in the channel interrupt status register,
164 * even if these are masked out by the interrupt mask register.
165 */
166#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
167#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
168#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
169#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
170
171/* baud dividers min/max values */
172#define CDNS_UART_BDIV_MIN 4
173#define CDNS_UART_BDIV_MAX 255
174#define CDNS_UART_CD_MAX 65535
175#define UART_AUTOSUSPEND_TIMEOUT 3000
176
177/**
178 * struct cdns_uart - device data
179 * @port: Pointer to the UART port
180 * @uartclk: Reference clock
181 * @pclk: APB clock
182 * @baud: Current baud rate
183 * @clk_rate_change_nb: Notifier block for clock changes
184 * @quirks: Flags for RXBS support.
185 */
186struct cdns_uart {
187 struct uart_port *port;
188 struct clk *uartclk;
189 struct clk *pclk;
190 unsigned int baud;
191 struct notifier_block clk_rate_change_nb;
192 u32 quirks;
193};
194struct cdns_platform_data {
195 u32 quirks;
196};
197#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
198 clk_rate_change_nb);
199
200/**
201 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
202 * @dev_id: Id of the UART port
203 * @isrstatus: The interrupt status register value as read
204 * Return: None
205 */
206static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
207{
208 struct uart_port *port = (struct uart_port *)dev_id;
209 struct cdns_uart *cdns_uart = port->private_data;
210 unsigned int data;
211 unsigned int rxbs_status = 0;
212 unsigned int status_mask;
213 unsigned int framerrprocessed = 0;
214 char status = TTY_NORMAL;
215 bool is_rxbs_support;
216
217 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
218
219 while ((readl(port->membase + CDNS_UART_SR) &
220 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
221 if (is_rxbs_support)
222 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
223 data = readl(port->membase + CDNS_UART_FIFO);
224 port->icount.rx++;
225 /*
226 * There is no hardware break detection in Zynq, so we interpret
227 * framing error with all-zeros data as a break sequence.
228 * Most of the time, there's another non-zero byte at the
229 * end of the sequence.
230 */
231 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
232 if (!data) {
233 port->read_status_mask |= CDNS_UART_IXR_BRK;
234 framerrprocessed = 1;
235 continue;
236 }
237 }
238 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
239 port->icount.brk++;
240 status = TTY_BREAK;
241 if (uart_handle_break(port))
242 continue;
243 }
244
245 isrstatus &= port->read_status_mask;
246 isrstatus &= ~port->ignore_status_mask;
247 status_mask = port->read_status_mask;
248 status_mask &= ~port->ignore_status_mask;
249
250 if (data &&
251 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
252 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
253 port->icount.brk++;
254 if (uart_handle_break(port))
255 continue;
256 }
257
258 if (uart_handle_sysrq_char(port, data))
259 continue;
260
261 if (is_rxbs_support) {
262 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
263 && (status_mask & CDNS_UART_IXR_PARITY)) {
264 port->icount.parity++;
265 status = TTY_PARITY;
266 }
267 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
268 && (status_mask & CDNS_UART_IXR_PARITY)) {
269 port->icount.frame++;
270 status = TTY_FRAME;
271 }
272 } else {
273 if (isrstatus & CDNS_UART_IXR_PARITY) {
274 port->icount.parity++;
275 status = TTY_PARITY;
276 }
277 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
278 !framerrprocessed) {
279 port->icount.frame++;
280 status = TTY_FRAME;
281 }
282 }
283 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
284 port->icount.overrun++;
285 tty_insert_flip_char(&port->state->port, 0,
286 TTY_OVERRUN);
287 }
288 tty_insert_flip_char(&port->state->port, data, status);
289 isrstatus = 0;
290 }
291 spin_unlock(&port->lock);
292 tty_flip_buffer_push(&port->state->port);
293 spin_lock(&port->lock);
294}
295
296/**
297 * cdns_uart_handle_tx - Handle the bytes to be Txed.
298 * @dev_id: Id of the UART port
299 * Return: None
300 */
301static void cdns_uart_handle_tx(void *dev_id)
302{
303 struct uart_port *port = (struct uart_port *)dev_id;
304 unsigned int numbytes;
305
306 if (uart_circ_empty(&port->state->xmit)) {
307 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
308 } else {
309 numbytes = port->fifosize;
310 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
311 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
312 /*
313 * Get the data from the UART circular buffer
314 * and write it to the cdns_uart's TX_FIFO
315 * register.
316 */
317 writel(
318 port->state->xmit.buf[port->state->xmit.
319 tail], port->membase + CDNS_UART_FIFO);
320
321 port->icount.tx++;
322
323 /*
324 * Adjust the tail of the UART buffer and wrap
325 * the buffer if it reaches limit.
326 */
327 port->state->xmit.tail =
328 (port->state->xmit.tail + 1) &
329 (UART_XMIT_SIZE - 1);
330
331 numbytes--;
332 }
333
334 if (uart_circ_chars_pending(
335 &port->state->xmit) < WAKEUP_CHARS)
336 uart_write_wakeup(port);
337 }
338}
339
340/**
341 * cdns_uart_isr - Interrupt handler
342 * @irq: Irq number
343 * @dev_id: Id of the port
344 *
345 * Return: IRQHANDLED
346 */
347static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
348{
349 struct uart_port *port = (struct uart_port *)dev_id;
350 unsigned int isrstatus;
351
352 spin_lock(&port->lock);
353
354 /* Read the interrupt status register to determine which
355 * interrupt(s) is/are active and clear them.
356 */
357 isrstatus = readl(port->membase + CDNS_UART_ISR);
358 writel(isrstatus, port->membase + CDNS_UART_ISR);
359
360 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
361 cdns_uart_handle_tx(dev_id);
362 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
363 }
364 if (isrstatus & CDNS_UART_IXR_MASK)
365 cdns_uart_handle_rx(dev_id, isrstatus);
366
367 spin_unlock(&port->lock);
368 return IRQ_HANDLED;
369}
370
371/**
372 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
373 * @clk: UART module input clock
374 * @baud: Desired baud rate
375 * @rbdiv: BDIV value (return value)
376 * @rcd: CD value (return value)
377 * @div8: Value for clk_sel bit in mod (return value)
378 * Return: baud rate, requested baud when possible, or actual baud when there
379 * was too much error, zero if no valid divisors are found.
380 *
381 * Formula to obtain baud rate is
382 * baud_tx/rx rate = clk/CD * (BDIV + 1)
383 * input_clk = (Uart User Defined Clock or Apb Clock)
384 * depends on UCLKEN in MR Reg
385 * clk = input_clk or input_clk/8;
386 * depends on CLKS in MR reg
387 * CD and BDIV depends on values in
388 * baud rate generate register
389 * baud rate clock divisor register
390 */
391static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
392 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
393{
394 u32 cd, bdiv;
395 unsigned int calc_baud;
396 unsigned int bestbaud = 0;
397 unsigned int bauderror;
398 unsigned int besterror = ~0;
399
400 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
401 *div8 = 1;
402 clk /= 8;
403 } else {
404 *div8 = 0;
405 }
406
407 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
408 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
409 if (cd < 1 || cd > CDNS_UART_CD_MAX)
410 continue;
411
412 calc_baud = clk / (cd * (bdiv + 1));
413
414 if (baud > calc_baud)
415 bauderror = baud - calc_baud;
416 else
417 bauderror = calc_baud - baud;
418
419 if (besterror > bauderror) {
420 *rbdiv = bdiv;
421 *rcd = cd;
422 bestbaud = calc_baud;
423 besterror = bauderror;
424 }
425 }
426 /* use the values when percent error is acceptable */
427 if (((besterror * 100) / baud) < 3)
428 bestbaud = baud;
429
430 return bestbaud;
431}
432
433/**
434 * cdns_uart_set_baud_rate - Calculate and set the baud rate
435 * @port: Handle to the uart port structure
436 * @baud: Baud rate to set
437 * Return: baud rate, requested baud when possible, or actual baud when there
438 * was too much error, zero if no valid divisors are found.
439 */
440static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
441 unsigned int baud)
442{
443 unsigned int calc_baud;
444 u32 cd = 0, bdiv = 0;
445 u32 mreg;
446 int div8;
447 struct cdns_uart *cdns_uart = port->private_data;
448
449 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
450 &div8);
451
452 /* Write new divisors to hardware */
453 mreg = readl(port->membase + CDNS_UART_MR);
454 if (div8)
455 mreg |= CDNS_UART_MR_CLKSEL;
456 else
457 mreg &= ~CDNS_UART_MR_CLKSEL;
458 writel(mreg, port->membase + CDNS_UART_MR);
459 writel(cd, port->membase + CDNS_UART_BAUDGEN);
460 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
461 cdns_uart->baud = baud;
462
463 return calc_baud;
464}
465
466#ifdef CONFIG_COMMON_CLK
467/**
468 * cdns_uart_clk_notitifer_cb - Clock notifier callback
469 * @nb: Notifier block
470 * @event: Notify event
471 * @data: Notifier data
472 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
473 */
474static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
475 unsigned long event, void *data)
476{
477 u32 ctrl_reg;
478 struct uart_port *port;
479 int locked = 0;
480 struct clk_notifier_data *ndata = data;
481 unsigned long flags = 0;
482 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
483
484 port = cdns_uart->port;
485 if (port->suspended)
486 return NOTIFY_OK;
487
488 switch (event) {
489 case PRE_RATE_CHANGE:
490 {
491 u32 bdiv, cd;
492 int div8;
493
494 /*
495 * Find out if current baud-rate can be achieved with new clock
496 * frequency.
497 */
498 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
499 &bdiv, &cd, &div8)) {
500 dev_warn(port->dev, "clock rate change rejected\n");
501 return NOTIFY_BAD;
502 }
503
504 spin_lock_irqsave(&cdns_uart->port->lock, flags);
505
506 /* Disable the TX and RX to set baud rate */
507 ctrl_reg = readl(port->membase + CDNS_UART_CR);
508 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
509 writel(ctrl_reg, port->membase + CDNS_UART_CR);
510
511 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
512
513 return NOTIFY_OK;
514 }
515 case POST_RATE_CHANGE:
516 /*
517 * Set clk dividers to generate correct baud with new clock
518 * frequency.
519 */
520
521 spin_lock_irqsave(&cdns_uart->port->lock, flags);
522
523 locked = 1;
524 port->uartclk = ndata->new_rate;
525
526 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
527 cdns_uart->baud);
528 /* fall through */
529 case ABORT_RATE_CHANGE:
530 if (!locked)
531 spin_lock_irqsave(&cdns_uart->port->lock, flags);
532
533 /* Set TX/RX Reset */
534 ctrl_reg = readl(port->membase + CDNS_UART_CR);
535 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
536 writel(ctrl_reg, port->membase + CDNS_UART_CR);
537
538 while (readl(port->membase + CDNS_UART_CR) &
539 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
540 cpu_relax();
541
542 /*
543 * Clear the RX disable and TX disable bits and then set the TX
544 * enable bit and RX enable bit to enable the transmitter and
545 * receiver.
546 */
547 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
548 ctrl_reg = readl(port->membase + CDNS_UART_CR);
549 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
550 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
551 writel(ctrl_reg, port->membase + CDNS_UART_CR);
552
553 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
554
555 return NOTIFY_OK;
556 default:
557 return NOTIFY_DONE;
558 }
559}
560#endif
561
562/**
563 * cdns_uart_start_tx - Start transmitting bytes
564 * @port: Handle to the uart port structure
565 */
566static void cdns_uart_start_tx(struct uart_port *port)
567{
568 unsigned int status;
569
570 if (uart_tx_stopped(port))
571 return;
572
573 /*
574 * Set the TX enable bit and clear the TX disable bit to enable the
575 * transmitter.
576 */
577 status = readl(port->membase + CDNS_UART_CR);
578 status &= ~CDNS_UART_CR_TX_DIS;
579 status |= CDNS_UART_CR_TX_EN;
580 writel(status, port->membase + CDNS_UART_CR);
581
582 if (uart_circ_empty(&port->state->xmit))
583 return;
584
585 cdns_uart_handle_tx(port);
586
587 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
588 /* Enable the TX Empty interrupt */
589 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
590}
591
592/**
593 * cdns_uart_stop_tx - Stop TX
594 * @port: Handle to the uart port structure
595 */
596static void cdns_uart_stop_tx(struct uart_port *port)
597{
598 unsigned int regval;
599
600 regval = readl(port->membase + CDNS_UART_CR);
601 regval |= CDNS_UART_CR_TX_DIS;
602 /* Disable the transmitter */
603 writel(regval, port->membase + CDNS_UART_CR);
604}
605
606/**
607 * cdns_uart_stop_rx - Stop RX
608 * @port: Handle to the uart port structure
609 */
610static void cdns_uart_stop_rx(struct uart_port *port)
611{
612 unsigned int regval;
613
614 /* Disable RX IRQs */
615 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
616
617 /* Disable the receiver */
618 regval = readl(port->membase + CDNS_UART_CR);
619 regval |= CDNS_UART_CR_RX_DIS;
620 writel(regval, port->membase + CDNS_UART_CR);
621}
622
623/**
624 * cdns_uart_tx_empty - Check whether TX is empty
625 * @port: Handle to the uart port structure
626 *
627 * Return: TIOCSER_TEMT on success, 0 otherwise
628 */
629static unsigned int cdns_uart_tx_empty(struct uart_port *port)
630{
631 unsigned int status;
632
633 status = readl(port->membase + CDNS_UART_SR) &
634 CDNS_UART_SR_TXEMPTY;
635 return status ? TIOCSER_TEMT : 0;
636}
637
638/**
639 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
640 * transmitting char breaks
641 * @port: Handle to the uart port structure
642 * @ctl: Value based on which start or stop decision is taken
643 */
644static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
645{
646 unsigned int status;
647 unsigned long flags;
648
649 spin_lock_irqsave(&port->lock, flags);
650
651 status = readl(port->membase + CDNS_UART_CR);
652
653 if (ctl == -1)
654 writel(CDNS_UART_CR_STARTBRK | status,
655 port->membase + CDNS_UART_CR);
656 else {
657 if ((status & CDNS_UART_CR_STOPBRK) == 0)
658 writel(CDNS_UART_CR_STOPBRK | status,
659 port->membase + CDNS_UART_CR);
660 }
661 spin_unlock_irqrestore(&port->lock, flags);
662}
663
664/**
665 * cdns_uart_set_termios - termios operations, handling data length, parity,
666 * stop bits, flow control, baud rate
667 * @port: Handle to the uart port structure
668 * @termios: Handle to the input termios structure
669 * @old: Values of the previously saved termios structure
670 */
671static void cdns_uart_set_termios(struct uart_port *port,
672 struct ktermios *termios, struct ktermios *old)
673{
674 unsigned int cval = 0;
675 unsigned int baud, minbaud, maxbaud;
676 unsigned long flags;
677 unsigned int ctrl_reg, mode_reg;
678
679 spin_lock_irqsave(&port->lock, flags);
680
681 /* Wait for the transmit FIFO to empty before making changes */
682 if (!(readl(port->membase + CDNS_UART_CR) &
683 CDNS_UART_CR_TX_DIS)) {
684 while (!(readl(port->membase + CDNS_UART_SR) &
685 CDNS_UART_SR_TXEMPTY)) {
686 cpu_relax();
687 }
688 }
689
690 /* Disable the TX and RX to set baud rate */
691 ctrl_reg = readl(port->membase + CDNS_UART_CR);
692 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
693 writel(ctrl_reg, port->membase + CDNS_UART_CR);
694
695 /*
696 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
697 * min and max baud should be calculated here based on port->uartclk.
698 * this way we get a valid baud and can safely call set_baud()
699 */
700 minbaud = port->uartclk /
701 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
702 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
703 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
704 baud = cdns_uart_set_baud_rate(port, baud);
705 if (tty_termios_baud_rate(termios))
706 tty_termios_encode_baud_rate(termios, baud, baud);
707
708 /* Update the per-port timeout. */
709 uart_update_timeout(port, termios->c_cflag, baud);
710
711 /* Set TX/RX Reset */
712 ctrl_reg = readl(port->membase + CDNS_UART_CR);
713 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
714 writel(ctrl_reg, port->membase + CDNS_UART_CR);
715
716 while (readl(port->membase + CDNS_UART_CR) &
717 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
718 cpu_relax();
719
720 /*
721 * Clear the RX disable and TX disable bits and then set the TX enable
722 * bit and RX enable bit to enable the transmitter and receiver.
723 */
724 ctrl_reg = readl(port->membase + CDNS_UART_CR);
725 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
726 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
727 writel(ctrl_reg, port->membase + CDNS_UART_CR);
728
729 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
730
731 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
732 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
733 port->ignore_status_mask = 0;
734
735 if (termios->c_iflag & INPCK)
736 port->read_status_mask |= CDNS_UART_IXR_PARITY |
737 CDNS_UART_IXR_FRAMING;
738
739 if (termios->c_iflag & IGNPAR)
740 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
741 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
742
743 /* ignore all characters if CREAD is not set */
744 if ((termios->c_cflag & CREAD) == 0)
745 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
746 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
747 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
748
749 mode_reg = readl(port->membase + CDNS_UART_MR);
750
751 /* Handling Data Size */
752 switch (termios->c_cflag & CSIZE) {
753 case CS6:
754 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
755 break;
756 case CS7:
757 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
758 break;
759 default:
760 case CS8:
761 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
762 termios->c_cflag &= ~CSIZE;
763 termios->c_cflag |= CS8;
764 break;
765 }
766
767 /* Handling Parity and Stop Bits length */
768 if (termios->c_cflag & CSTOPB)
769 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
770 else
771 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
772
773 if (termios->c_cflag & PARENB) {
774 /* Mark or Space parity */
775 if (termios->c_cflag & CMSPAR) {
776 if (termios->c_cflag & PARODD)
777 cval |= CDNS_UART_MR_PARITY_MARK;
778 else
779 cval |= CDNS_UART_MR_PARITY_SPACE;
780 } else {
781 if (termios->c_cflag & PARODD)
782 cval |= CDNS_UART_MR_PARITY_ODD;
783 else
784 cval |= CDNS_UART_MR_PARITY_EVEN;
785 }
786 } else {
787 cval |= CDNS_UART_MR_PARITY_NONE;
788 }
789 cval |= mode_reg & 1;
790 writel(cval, port->membase + CDNS_UART_MR);
791
792 spin_unlock_irqrestore(&port->lock, flags);
793}
794
795/**
796 * cdns_uart_startup - Called when an application opens a cdns_uart port
797 * @port: Handle to the uart port structure
798 *
799 * Return: 0 on success, negative errno otherwise
800 */
801static int cdns_uart_startup(struct uart_port *port)
802{
803 struct cdns_uart *cdns_uart = port->private_data;
804 bool is_brk_support;
805 int ret;
806 unsigned long flags;
807 unsigned int status = 0;
808
809 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
810
811 spin_lock_irqsave(&port->lock, flags);
812
813 /* Disable the TX and RX */
814 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
815 port->membase + CDNS_UART_CR);
816
817 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
818 * no break chars.
819 */
820 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
821 port->membase + CDNS_UART_CR);
822
823 while (readl(port->membase + CDNS_UART_CR) &
824 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
825 cpu_relax();
826
827 /*
828 * Clear the RX disable bit and then set the RX enable bit to enable
829 * the receiver.
830 */
831 status = readl(port->membase + CDNS_UART_CR);
832 status &= CDNS_UART_CR_RX_DIS;
833 status |= CDNS_UART_CR_RX_EN;
834 writel(status, port->membase + CDNS_UART_CR);
835
836 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
837 * no parity.
838 */
839 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
840 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
841 port->membase + CDNS_UART_MR);
842
843 /*
844 * Set the RX FIFO Trigger level to use most of the FIFO, but it
845 * can be tuned with a module parameter
846 */
847 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
848
849 /*
850 * Receive Timeout register is enabled but it
851 * can be tuned with a module parameter
852 */
853 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
854
855 /* Clear out any pending interrupts before enabling them */
856 writel(readl(port->membase + CDNS_UART_ISR),
857 port->membase + CDNS_UART_ISR);
858
859 spin_unlock_irqrestore(&port->lock, flags);
860
861 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
862 if (ret) {
863 dev_err(port->dev, "request_irq '%d' failed with %d\n",
864 port->irq, ret);
865 return ret;
866 }
867
868 /* Set the Interrupt Registers with desired interrupts */
869 if (is_brk_support)
870 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
871 port->membase + CDNS_UART_IER);
872 else
873 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
874
875 return 0;
876}
877
878/**
879 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
880 * @port: Handle to the uart port structure
881 */
882static void cdns_uart_shutdown(struct uart_port *port)
883{
884 int status;
885 unsigned long flags;
886
887 spin_lock_irqsave(&port->lock, flags);
888
889 /* Disable interrupts */
890 status = readl(port->membase + CDNS_UART_IMR);
891 writel(status, port->membase + CDNS_UART_IDR);
892 writel(0xffffffff, port->membase + CDNS_UART_ISR);
893
894 /* Disable the TX and RX */
895 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
896 port->membase + CDNS_UART_CR);
897
898 spin_unlock_irqrestore(&port->lock, flags);
899
900 free_irq(port->irq, port);
901}
902
903/**
904 * cdns_uart_type - Set UART type to cdns_uart port
905 * @port: Handle to the uart port structure
906 *
907 * Return: string on success, NULL otherwise
908 */
909static const char *cdns_uart_type(struct uart_port *port)
910{
911 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
912}
913
914/**
915 * cdns_uart_verify_port - Verify the port params
916 * @port: Handle to the uart port structure
917 * @ser: Handle to the structure whose members are compared
918 *
919 * Return: 0 on success, negative errno otherwise.
920 */
921static int cdns_uart_verify_port(struct uart_port *port,
922 struct serial_struct *ser)
923{
924 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
925 return -EINVAL;
926 if (port->irq != ser->irq)
927 return -EINVAL;
928 if (ser->io_type != UPIO_MEM)
929 return -EINVAL;
930 if (port->iobase != ser->port)
931 return -EINVAL;
932 if (ser->hub6 != 0)
933 return -EINVAL;
934 return 0;
935}
936
937/**
938 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
939 * called when the driver adds a cdns_uart port via
940 * uart_add_one_port()
941 * @port: Handle to the uart port structure
942 *
943 * Return: 0 on success, negative errno otherwise.
944 */
945static int cdns_uart_request_port(struct uart_port *port)
946{
947 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
948 CDNS_UART_NAME)) {
949 return -ENOMEM;
950 }
951
952 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
953 if (!port->membase) {
954 dev_err(port->dev, "Unable to map registers\n");
955 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
956 return -ENOMEM;
957 }
958 return 0;
959}
960
961/**
962 * cdns_uart_release_port - Release UART port
963 * @port: Handle to the uart port structure
964 *
965 * Release the memory region attached to a cdns_uart port. Called when the
966 * driver removes a cdns_uart port via uart_remove_one_port().
967 */
968static void cdns_uart_release_port(struct uart_port *port)
969{
970 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
971 iounmap(port->membase);
972 port->membase = NULL;
973}
974
975/**
976 * cdns_uart_config_port - Configure UART port
977 * @port: Handle to the uart port structure
978 * @flags: If any
979 */
980static void cdns_uart_config_port(struct uart_port *port, int flags)
981{
982 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
983 port->type = PORT_XUARTPS;
984}
985
986/**
987 * cdns_uart_get_mctrl - Get the modem control state
988 * @port: Handle to the uart port structure
989 *
990 * Return: the modem control state
991 */
992static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
993{
994 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
995}
996
997static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
998{
999 u32 val;
1000 u32 mode_reg;
1001
1002 val = readl(port->membase + CDNS_UART_MODEMCR);
1003 mode_reg = readl(port->membase + CDNS_UART_MR);
1004
1005 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1006 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1007
1008 if (mctrl & TIOCM_RTS)
1009 val |= CDNS_UART_MODEMCR_RTS;
1010 if (mctrl & TIOCM_DTR)
1011 val |= CDNS_UART_MODEMCR_DTR;
1012 if (mctrl & TIOCM_LOOP)
1013 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1014 else
1015 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1016
1017 writel(val, port->membase + CDNS_UART_MODEMCR);
1018 writel(mode_reg, port->membase + CDNS_UART_MR);
1019}
1020
1021#ifdef CONFIG_CONSOLE_POLL
1022static int cdns_uart_poll_get_char(struct uart_port *port)
1023{
1024 int c;
1025 unsigned long flags;
1026
1027 spin_lock_irqsave(&port->lock, flags);
1028
1029 /* Check if FIFO is empty */
1030 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1031 c = NO_POLL_CHAR;
1032 else /* Read a character */
1033 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1034
1035 spin_unlock_irqrestore(&port->lock, flags);
1036
1037 return c;
1038}
1039
1040static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1041{
1042 unsigned long flags;
1043
1044 spin_lock_irqsave(&port->lock, flags);
1045
1046 /* Wait until FIFO is empty */
1047 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1048 cpu_relax();
1049
1050 /* Write a character */
1051 writel(c, port->membase + CDNS_UART_FIFO);
1052
1053 /* Wait until FIFO is empty */
1054 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1055 cpu_relax();
1056
1057 spin_unlock_irqrestore(&port->lock, flags);
1058
1059 return;
1060}
1061#endif
1062
1063static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1064 unsigned int oldstate)
1065{
1066 switch (state) {
1067 case UART_PM_STATE_OFF:
1068 pm_runtime_mark_last_busy(port->dev);
1069 pm_runtime_put_autosuspend(port->dev);
1070 break;
1071 default:
1072 pm_runtime_get_sync(port->dev);
1073 break;
1074 }
1075}
1076
1077static const struct uart_ops cdns_uart_ops = {
1078 .set_mctrl = cdns_uart_set_mctrl,
1079 .get_mctrl = cdns_uart_get_mctrl,
1080 .start_tx = cdns_uart_start_tx,
1081 .stop_tx = cdns_uart_stop_tx,
1082 .stop_rx = cdns_uart_stop_rx,
1083 .tx_empty = cdns_uart_tx_empty,
1084 .break_ctl = cdns_uart_break_ctl,
1085 .set_termios = cdns_uart_set_termios,
1086 .startup = cdns_uart_startup,
1087 .shutdown = cdns_uart_shutdown,
1088 .pm = cdns_uart_pm,
1089 .type = cdns_uart_type,
1090 .verify_port = cdns_uart_verify_port,
1091 .request_port = cdns_uart_request_port,
1092 .release_port = cdns_uart_release_port,
1093 .config_port = cdns_uart_config_port,
1094#ifdef CONFIG_CONSOLE_POLL
1095 .poll_get_char = cdns_uart_poll_get_char,
1096 .poll_put_char = cdns_uart_poll_put_char,
1097#endif
1098};
1099
1100static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1101
1102/**
1103 * cdns_uart_get_port - Configure the port from platform device resource info
1104 * @id: Port id
1105 *
1106 * Return: a pointer to a uart_port or NULL for failure
1107 */
1108static struct uart_port *cdns_uart_get_port(int id)
1109{
1110 struct uart_port *port;
1111
1112 /* Try the given port id if failed use default method */
1113 if (id < CDNS_UART_NR_PORTS && cdns_uart_port[id].mapbase != 0) {
1114 /* Find the next unused port */
1115 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1116 if (cdns_uart_port[id].mapbase == 0)
1117 break;
1118 }
1119
1120 if (id >= CDNS_UART_NR_PORTS)
1121 return NULL;
1122
1123 port = &cdns_uart_port[id];
1124
1125 /* At this point, we've got an empty uart_port struct, initialize it */
1126 spin_lock_init(&port->lock);
1127 port->membase = NULL;
1128 port->irq = 0;
1129 port->type = PORT_UNKNOWN;
1130 port->iotype = UPIO_MEM32;
1131 port->flags = UPF_BOOT_AUTOCONF;
1132 port->ops = &cdns_uart_ops;
1133 port->fifosize = CDNS_UART_FIFO_SIZE;
1134 port->line = id;
1135 port->dev = NULL;
1136 return port;
1137}
1138
1139#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1140/**
1141 * cdns_uart_console_wait_tx - Wait for the TX to be full
1142 * @port: Handle to the uart port structure
1143 */
1144static void cdns_uart_console_wait_tx(struct uart_port *port)
1145{
1146 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1147 barrier();
1148}
1149
1150/**
1151 * cdns_uart_console_putchar - write the character to the FIFO buffer
1152 * @port: Handle to the uart port structure
1153 * @ch: Character to be written
1154 */
1155static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1156{
1157 cdns_uart_console_wait_tx(port);
1158 writel(ch, port->membase + CDNS_UART_FIFO);
1159}
1160
1161static void cdns_early_write(struct console *con, const char *s,
1162 unsigned n)
1163{
1164 struct earlycon_device *dev = con->data;
1165
1166 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1167}
1168
1169static int __init cdns_early_console_setup(struct earlycon_device *device,
1170 const char *opt)
1171{
1172 struct uart_port *port = &device->port;
1173
1174 if (!port->membase)
1175 return -ENODEV;
1176
1177 /* initialise control register */
1178 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1179 port->membase + CDNS_UART_CR);
1180
1181 /* only set baud if specified on command line - otherwise
1182 * assume it has been initialized by a boot loader.
1183 */
1184 if (port->uartclk && device->baud) {
1185 u32 cd = 0, bdiv = 0;
1186 u32 mr;
1187 int div8;
1188
1189 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1190 &bdiv, &cd, &div8);
1191 mr = CDNS_UART_MR_PARITY_NONE;
1192 if (div8)
1193 mr |= CDNS_UART_MR_CLKSEL;
1194
1195 writel(mr, port->membase + CDNS_UART_MR);
1196 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1197 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1198 }
1199
1200 device->con->write = cdns_early_write;
1201
1202 return 0;
1203}
1204OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1205OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1206OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1207OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1208
1209/**
1210 * cdns_uart_console_write - perform write operation
1211 * @co: Console handle
1212 * @s: Pointer to character array
1213 * @count: No of characters
1214 */
1215static void cdns_uart_console_write(struct console *co, const char *s,
1216 unsigned int count)
1217{
1218 struct uart_port *port = &cdns_uart_port[co->index];
1219 unsigned long flags;
1220 unsigned int imr, ctrl;
1221 int locked = 1;
1222
1223 if (port->sysrq)
1224 locked = 0;
1225 else if (oops_in_progress)
1226 locked = spin_trylock_irqsave(&port->lock, flags);
1227 else
1228 spin_lock_irqsave(&port->lock, flags);
1229
1230 /* save and disable interrupt */
1231 imr = readl(port->membase + CDNS_UART_IMR);
1232 writel(imr, port->membase + CDNS_UART_IDR);
1233
1234 /*
1235 * Make sure that the tx part is enabled. Set the TX enable bit and
1236 * clear the TX disable bit to enable the transmitter.
1237 */
1238 ctrl = readl(port->membase + CDNS_UART_CR);
1239 ctrl &= ~CDNS_UART_CR_TX_DIS;
1240 ctrl |= CDNS_UART_CR_TX_EN;
1241 writel(ctrl, port->membase + CDNS_UART_CR);
1242
1243 uart_console_write(port, s, count, cdns_uart_console_putchar);
1244 cdns_uart_console_wait_tx(port);
1245
1246 writel(ctrl, port->membase + CDNS_UART_CR);
1247
1248 /* restore interrupt state */
1249 writel(imr, port->membase + CDNS_UART_IER);
1250
1251 if (locked)
1252 spin_unlock_irqrestore(&port->lock, flags);
1253}
1254
1255/**
1256 * cdns_uart_console_setup - Initialize the uart to default config
1257 * @co: Console handle
1258 * @options: Initial settings of uart
1259 *
1260 * Return: 0 on success, negative errno otherwise.
1261 */
1262static int __init cdns_uart_console_setup(struct console *co, char *options)
1263{
1264 struct uart_port *port = &cdns_uart_port[co->index];
1265 int baud = 9600;
1266 int bits = 8;
1267 int parity = 'n';
1268 int flow = 'n';
1269
1270 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1271 return -EINVAL;
1272
1273 if (!port->membase) {
1274 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1275 co->index);
1276 return -ENODEV;
1277 }
1278
1279 if (options)
1280 uart_parse_options(options, &baud, &parity, &bits, &flow);
1281
1282 return uart_set_options(port, co, baud, parity, bits, flow);
1283}
1284
1285static struct uart_driver cdns_uart_uart_driver;
1286
1287static struct console cdns_uart_console = {
1288 .name = CDNS_UART_TTY_NAME,
1289 .write = cdns_uart_console_write,
1290 .device = uart_console_device,
1291 .setup = cdns_uart_console_setup,
1292 .flags = CON_PRINTBUFFER,
1293 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1294 .data = &cdns_uart_uart_driver,
1295};
1296
1297/**
1298 * cdns_uart_console_init - Initialization call
1299 *
1300 * Return: 0 on success, negative errno otherwise
1301 */
1302static int __init cdns_uart_console_init(void)
1303{
1304 register_console(&cdns_uart_console);
1305 return 0;
1306}
1307
1308console_initcall(cdns_uart_console_init);
1309
1310#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1311
1312static struct uart_driver cdns_uart_uart_driver = {
1313 .owner = THIS_MODULE,
1314 .driver_name = CDNS_UART_NAME,
1315 .dev_name = CDNS_UART_TTY_NAME,
1316 .major = CDNS_UART_MAJOR,
1317 .minor = CDNS_UART_MINOR,
1318 .nr = CDNS_UART_NR_PORTS,
1319#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1320 .cons = &cdns_uart_console,
1321#endif
1322};
1323
1324#ifdef CONFIG_PM_SLEEP
1325/**
1326 * cdns_uart_suspend - suspend event
1327 * @device: Pointer to the device structure
1328 *
1329 * Return: 0
1330 */
1331static int cdns_uart_suspend(struct device *device)
1332{
1333 struct uart_port *port = dev_get_drvdata(device);
1334 struct tty_struct *tty;
1335 struct device *tty_dev;
1336 int may_wake = 0;
1337
1338 /* Get the tty which could be NULL so don't assume it's valid */
1339 tty = tty_port_tty_get(&port->state->port);
1340 if (tty) {
1341 tty_dev = tty->dev;
1342 may_wake = device_may_wakeup(tty_dev);
1343 tty_kref_put(tty);
1344 }
1345
1346 /*
1347 * Call the API provided in serial_core.c file which handles
1348 * the suspend.
1349 */
1350 uart_suspend_port(&cdns_uart_uart_driver, port);
1351 if (!(console_suspend_enabled && !may_wake)) {
1352 unsigned long flags = 0;
1353
1354 spin_lock_irqsave(&port->lock, flags);
1355 /* Empty the receive FIFO 1st before making changes */
1356 while (!(readl(port->membase + CDNS_UART_SR) &
1357 CDNS_UART_SR_RXEMPTY))
1358 readl(port->membase + CDNS_UART_FIFO);
1359 /* set RX trigger level to 1 */
1360 writel(1, port->membase + CDNS_UART_RXWM);
1361 /* disable RX timeout interrups */
1362 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1363 spin_unlock_irqrestore(&port->lock, flags);
1364 }
1365
1366 return 0;
1367}
1368
1369/**
1370 * cdns_uart_resume - Resume after a previous suspend
1371 * @device: Pointer to the device structure
1372 *
1373 * Return: 0
1374 */
1375static int cdns_uart_resume(struct device *device)
1376{
1377 struct uart_port *port = dev_get_drvdata(device);
1378 unsigned long flags = 0;
1379 u32 ctrl_reg;
1380 struct tty_struct *tty;
1381 struct device *tty_dev;
1382 int may_wake = 0;
1383
1384 /* Get the tty which could be NULL so don't assume it's valid */
1385 tty = tty_port_tty_get(&port->state->port);
1386 if (tty) {
1387 tty_dev = tty->dev;
1388 may_wake = device_may_wakeup(tty_dev);
1389 tty_kref_put(tty);
1390 }
1391
1392 if (console_suspend_enabled && !may_wake) {
1393 struct cdns_uart *cdns_uart = port->private_data;
1394
1395 clk_enable(cdns_uart->pclk);
1396 clk_enable(cdns_uart->uartclk);
1397
1398 spin_lock_irqsave(&port->lock, flags);
1399
1400 /* Set TX/RX Reset */
1401 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1402 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1403 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1404 while (readl(port->membase + CDNS_UART_CR) &
1405 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1406 cpu_relax();
1407
1408 /* restore rx timeout value */
1409 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1410 /* Enable Tx/Rx */
1411 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1412 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1413 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1414 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1415
1416 clk_disable(cdns_uart->uartclk);
1417 clk_disable(cdns_uart->pclk);
1418 spin_unlock_irqrestore(&port->lock, flags);
1419 } else {
1420 spin_lock_irqsave(&port->lock, flags);
1421 /* restore original rx trigger level */
1422 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1423 /* enable RX timeout interrupt */
1424 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1425 spin_unlock_irqrestore(&port->lock, flags);
1426 }
1427
1428 return uart_resume_port(&cdns_uart_uart_driver, port);
1429}
1430#endif /* ! CONFIG_PM_SLEEP */
1431static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1432{
1433 struct platform_device *pdev = to_platform_device(dev);
1434 struct uart_port *port = platform_get_drvdata(pdev);
1435 struct cdns_uart *cdns_uart = port->private_data;
1436
1437 clk_disable(cdns_uart->uartclk);
1438 clk_disable(cdns_uart->pclk);
1439 return 0;
1440};
1441
1442static int __maybe_unused cdns_runtime_resume(struct device *dev)
1443{
1444 struct platform_device *pdev = to_platform_device(dev);
1445 struct uart_port *port = platform_get_drvdata(pdev);
1446 struct cdns_uart *cdns_uart = port->private_data;
1447
1448 clk_enable(cdns_uart->pclk);
1449 clk_enable(cdns_uart->uartclk);
1450 return 0;
1451};
1452
1453static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1454 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1455 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1456 cdns_runtime_resume, NULL)
1457};
1458
1459static const struct cdns_platform_data zynqmp_uart_def = {
1460 .quirks = CDNS_UART_RXBS_SUPPORT, };
1461
1462/* Match table for of_platform binding */
1463static const struct of_device_id cdns_uart_of_match[] = {
1464 { .compatible = "xlnx,xuartps", },
1465 { .compatible = "cdns,uart-r1p8", },
1466 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1467 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1468 {}
1469};
1470MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1471
1472/**
1473 * cdns_uart_probe - Platform driver probe
1474 * @pdev: Pointer to the platform device structure
1475 *
1476 * Return: 0 on success, negative errno otherwise
1477 */
1478static int cdns_uart_probe(struct platform_device *pdev)
1479{
1480 int rc, id, irq;
1481 struct uart_port *port;
1482 struct resource *res;
1483 struct cdns_uart *cdns_uart_data;
1484 const struct of_device_id *match;
1485
1486 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1487 GFP_KERNEL);
1488 if (!cdns_uart_data)
1489 return -ENOMEM;
1490
1491 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1492 if (match && match->data) {
1493 const struct cdns_platform_data *data = match->data;
1494
1495 cdns_uart_data->quirks = data->quirks;
1496 }
1497
1498 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1499 if (IS_ERR(cdns_uart_data->pclk)) {
1500 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1501 if (!IS_ERR(cdns_uart_data->pclk))
1502 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1503 }
1504 if (IS_ERR(cdns_uart_data->pclk)) {
1505 dev_err(&pdev->dev, "pclk clock not found.\n");
1506 return PTR_ERR(cdns_uart_data->pclk);
1507 }
1508
1509 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1510 if (IS_ERR(cdns_uart_data->uartclk)) {
1511 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1512 if (!IS_ERR(cdns_uart_data->uartclk))
1513 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1514 }
1515 if (IS_ERR(cdns_uart_data->uartclk)) {
1516 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1517 return PTR_ERR(cdns_uart_data->uartclk);
1518 }
1519
1520 rc = clk_prepare_enable(cdns_uart_data->pclk);
1521 if (rc) {
1522 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1523 return rc;
1524 }
1525 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1526 if (rc) {
1527 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1528 goto err_out_clk_dis_pclk;
1529 }
1530
1531 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1532 if (!res) {
1533 rc = -ENODEV;
1534 goto err_out_clk_disable;
1535 }
1536
1537 irq = platform_get_irq(pdev, 0);
1538 if (irq <= 0) {
1539 rc = -ENXIO;
1540 goto err_out_clk_disable;
1541 }
1542
1543#ifdef CONFIG_COMMON_CLK
1544 cdns_uart_data->clk_rate_change_nb.notifier_call =
1545 cdns_uart_clk_notifier_cb;
1546 if (clk_notifier_register(cdns_uart_data->uartclk,
1547 &cdns_uart_data->clk_rate_change_nb))
1548 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1549#endif
1550 /* Look for a serialN alias */
1551 id = of_alias_get_id(pdev->dev.of_node, "serial");
1552 if (id < 0)
1553 id = 0;
1554
1555 /* Initialize the port structure */
1556 port = cdns_uart_get_port(id);
1557
1558 if (!port) {
1559 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1560 rc = -ENODEV;
1561 goto err_out_notif_unreg;
1562 }
1563
1564 /*
1565 * Register the port.
1566 * This function also registers this device with the tty layer
1567 * and triggers invocation of the config_port() entry point.
1568 */
1569 port->mapbase = res->start;
1570 port->irq = irq;
1571 port->dev = &pdev->dev;
1572 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1573 port->private_data = cdns_uart_data;
1574 cdns_uart_data->port = port;
1575 platform_set_drvdata(pdev, port);
1576
1577 pm_runtime_use_autosuspend(&pdev->dev);
1578 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1579 pm_runtime_set_active(&pdev->dev);
1580 pm_runtime_enable(&pdev->dev);
1581
1582 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1583 if (rc) {
1584 dev_err(&pdev->dev,
1585 "uart_add_one_port() failed; err=%i\n", rc);
1586 goto err_out_pm_disable;
1587 }
1588
1589 return 0;
1590
1591err_out_pm_disable:
1592 pm_runtime_disable(&pdev->dev);
1593 pm_runtime_set_suspended(&pdev->dev);
1594 pm_runtime_dont_use_autosuspend(&pdev->dev);
1595err_out_notif_unreg:
1596#ifdef CONFIG_COMMON_CLK
1597 clk_notifier_unregister(cdns_uart_data->uartclk,
1598 &cdns_uart_data->clk_rate_change_nb);
1599#endif
1600err_out_clk_disable:
1601 clk_disable_unprepare(cdns_uart_data->uartclk);
1602err_out_clk_dis_pclk:
1603 clk_disable_unprepare(cdns_uart_data->pclk);
1604
1605 return rc;
1606}
1607
1608/**
1609 * cdns_uart_remove - called when the platform driver is unregistered
1610 * @pdev: Pointer to the platform device structure
1611 *
1612 * Return: 0 on success, negative errno otherwise
1613 */
1614static int cdns_uart_remove(struct platform_device *pdev)
1615{
1616 struct uart_port *port = platform_get_drvdata(pdev);
1617 struct cdns_uart *cdns_uart_data = port->private_data;
1618 int rc;
1619
1620 /* Remove the cdns_uart port from the serial core */
1621#ifdef CONFIG_COMMON_CLK
1622 clk_notifier_unregister(cdns_uart_data->uartclk,
1623 &cdns_uart_data->clk_rate_change_nb);
1624#endif
1625 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1626 port->mapbase = 0;
1627 clk_disable_unprepare(cdns_uart_data->uartclk);
1628 clk_disable_unprepare(cdns_uart_data->pclk);
1629 pm_runtime_disable(&pdev->dev);
1630 pm_runtime_set_suspended(&pdev->dev);
1631 pm_runtime_dont_use_autosuspend(&pdev->dev);
1632 return rc;
1633}
1634
1635static struct platform_driver cdns_uart_platform_driver = {
1636 .probe = cdns_uart_probe,
1637 .remove = cdns_uart_remove,
1638 .driver = {
1639 .name = CDNS_UART_NAME,
1640 .of_match_table = cdns_uart_of_match,
1641 .pm = &cdns_uart_dev_pm_ops,
1642 },
1643};
1644
1645static int __init cdns_uart_init(void)
1646{
1647 int retval = 0;
1648
1649 /* Register the cdns_uart driver with the serial core */
1650 retval = uart_register_driver(&cdns_uart_uart_driver);
1651 if (retval)
1652 return retval;
1653
1654 /* Register the platform driver */
1655 retval = platform_driver_register(&cdns_uart_platform_driver);
1656 if (retval)
1657 uart_unregister_driver(&cdns_uart_uart_driver);
1658
1659 return retval;
1660}
1661
1662static void __exit cdns_uart_exit(void)
1663{
1664 /* Unregister the platform driver */
1665 platform_driver_unregister(&cdns_uart_platform_driver);
1666
1667 /* Unregister the cdns_uart driver */
1668 uart_unregister_driver(&cdns_uart_uart_driver);
1669}
1670
1671arch_initcall(cdns_uart_init);
1672module_exit(cdns_uart_exit);
1673
1674MODULE_DESCRIPTION("Driver for Cadence UART");
1675MODULE_AUTHOR("Xilinx Inc.");
1676MODULE_LICENSE("GPL");
1/*
2 * Xilinx PS UART driver
3 *
4 * 2011 - 2013 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 */
13
14#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15#define SUPPORT_SYSRQ
16#endif
17
18#include <linux/platform_device.h>
19#include <linux/serial.h>
20#include <linux/console.h>
21#include <linux/serial_core.h>
22#include <linux/slab.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/clk.h>
26#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/module.h>
30
31#define XUARTPS_TTY_NAME "ttyPS"
32#define XUARTPS_NAME "xuartps"
33#define XUARTPS_MAJOR 0 /* use dynamic node allocation */
34#define XUARTPS_MINOR 0 /* works best with devtmpfs */
35#define XUARTPS_NR_PORTS 2
36#define XUARTPS_FIFO_SIZE 64 /* FIFO size */
37#define XUARTPS_REGISTER_SPACE 0xFFF
38
39#define xuartps_readl(offset) ioread32(port->membase + offset)
40#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
41
42/* Rx Trigger level */
43static int rx_trigger_level = 56;
44module_param(rx_trigger_level, uint, S_IRUGO);
45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47/* Rx Timeout */
48static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52/********************************Register Map********************************/
53/** UART
54 *
55 * Register offsets for the UART.
56 *
57 */
58#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
59#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
60#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
61#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
62#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
63#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
64#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
65#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
66#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
67#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
68#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
69#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
70#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
71#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
72#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
73#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
74 Width [15:0] */
75#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
76 Width [7:0] */
77#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
78
79/** Control Register
80 *
81 * The Control register (CR) controls the major functions of the device.
82 *
83 * Control Register Bit Definitions
84 */
85#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
86#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
87#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
88#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
89#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
90#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
91#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
92#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
93#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
94
95/** Mode Register
96 *
97 * The mode register (MR) defines the mode of transfer as well as the data
98 * format. If this register is modified during transmission or reception,
99 * data validity cannot be guaranteed.
100 *
101 * Mode Register Bit Definitions
102 *
103 */
104#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
105#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
106#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
107
108#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
109#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
110
111#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
112#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
113#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
114#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
115#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
116
117#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
118#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
119#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
120
121/** Interrupt Registers
122 *
123 * Interrupt control logic uses the interrupt enable register (IER) and the
124 * interrupt disable register (IDR) to set the value of the bits in the
125 * interrupt mask register (IMR). The IMR determines whether to pass an
126 * interrupt to the interrupt status register (ISR).
127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129 * Reading either IER or IDR returns 0x00.
130 *
131 * All four registers have the same bit definitions.
132 */
133#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
134#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
135#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
136#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
137#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
138#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
139#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
140#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
141#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
142#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
143#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
144
145/* Goes in read_status_mask for break detection as the HW doesn't do it*/
146#define XUARTPS_IXR_BRK 0x80000000
147
148/** Channel Status Register
149 *
150 * The channel status register (CSR) is provided to enable the control logic
151 * to monitor the status of bits in the channel interrupt status register,
152 * even if these are masked out by the interrupt mask register.
153 */
154#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
155#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
156#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
157#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
158
159/* baud dividers min/max values */
160#define XUARTPS_BDIV_MIN 4
161#define XUARTPS_BDIV_MAX 255
162#define XUARTPS_CD_MAX 65535
163
164/**
165 * struct xuartps - device data
166 * @port Pointer to the UART port
167 * @refclk Reference clock
168 * @aperclk APB clock
169 * @baud Current baud rate
170 * @clk_rate_change_nb Notifier block for clock changes
171 */
172struct xuartps {
173 struct uart_port *port;
174 struct clk *refclk;
175 struct clk *aperclk;
176 unsigned int baud;
177 struct notifier_block clk_rate_change_nb;
178};
179#define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb);
180
181/**
182 * xuartps_isr - Interrupt handler
183 * @irq: Irq number
184 * @dev_id: Id of the port
185 *
186 * Returns IRQHANDLED
187 **/
188static irqreturn_t xuartps_isr(int irq, void *dev_id)
189{
190 struct uart_port *port = (struct uart_port *)dev_id;
191 unsigned long flags;
192 unsigned int isrstatus, numbytes;
193 unsigned int data;
194 char status = TTY_NORMAL;
195
196 spin_lock_irqsave(&port->lock, flags);
197
198 /* Read the interrupt status register to determine which
199 * interrupt(s) is/are active.
200 */
201 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
202
203 /*
204 * There is no hardware break detection, so we interpret framing
205 * error with all-zeros data as a break sequence. Most of the time,
206 * there's another non-zero byte at the end of the sequence.
207 */
208
209 if (isrstatus & XUARTPS_IXR_FRAMING) {
210 while (!(xuartps_readl(XUARTPS_SR_OFFSET) &
211 XUARTPS_SR_RXEMPTY)) {
212 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) {
213 port->read_status_mask |= XUARTPS_IXR_BRK;
214 isrstatus &= ~XUARTPS_IXR_FRAMING;
215 }
216 }
217 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET);
218 }
219
220 /* drop byte with parity error if IGNPAR specified */
221 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
222 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
223
224 isrstatus &= port->read_status_mask;
225 isrstatus &= ~port->ignore_status_mask;
226
227 if ((isrstatus & XUARTPS_IXR_TOUT) ||
228 (isrstatus & XUARTPS_IXR_RXTRIG)) {
229 /* Receive Timeout Interrupt */
230 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
231 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
232 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
233
234 /* Non-NULL byte after BREAK is garbage (99%) */
235 if (data && (port->read_status_mask &
236 XUARTPS_IXR_BRK)) {
237 port->read_status_mask &= ~XUARTPS_IXR_BRK;
238 port->icount.brk++;
239 if (uart_handle_break(port))
240 continue;
241 }
242
243#ifdef SUPPORT_SYSRQ
244 /*
245 * uart_handle_sysrq_char() doesn't work if
246 * spinlocked, for some reason
247 */
248 if (port->sysrq) {
249 spin_unlock(&port->lock);
250 if (uart_handle_sysrq_char(port,
251 (unsigned char)data)) {
252 spin_lock(&port->lock);
253 continue;
254 }
255 spin_lock(&port->lock);
256 }
257#endif
258
259 port->icount.rx++;
260
261 if (isrstatus & XUARTPS_IXR_PARITY) {
262 port->icount.parity++;
263 status = TTY_PARITY;
264 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
265 port->icount.frame++;
266 status = TTY_FRAME;
267 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
268 port->icount.overrun++;
269
270 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
271 data, status);
272 }
273 spin_unlock(&port->lock);
274 tty_flip_buffer_push(&port->state->port);
275 spin_lock(&port->lock);
276 }
277
278 /* Dispatch an appropriate handler */
279 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
280 if (uart_circ_empty(&port->state->xmit)) {
281 xuartps_writel(XUARTPS_IXR_TXEMPTY,
282 XUARTPS_IDR_OFFSET);
283 } else {
284 numbytes = port->fifosize;
285 /* Break if no more data available in the UART buffer */
286 while (numbytes--) {
287 if (uart_circ_empty(&port->state->xmit))
288 break;
289 /* Get the data from the UART circular buffer
290 * and write it to the xuartps's TX_FIFO
291 * register.
292 */
293 xuartps_writel(
294 port->state->xmit.buf[port->state->xmit.
295 tail], XUARTPS_FIFO_OFFSET);
296
297 port->icount.tx++;
298
299 /* Adjust the tail of the UART buffer and wrap
300 * the buffer if it reaches limit.
301 */
302 port->state->xmit.tail =
303 (port->state->xmit.tail + 1) & \
304 (UART_XMIT_SIZE - 1);
305 }
306
307 if (uart_circ_chars_pending(
308 &port->state->xmit) < WAKEUP_CHARS)
309 uart_write_wakeup(port);
310 }
311 }
312
313 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
314
315 /* be sure to release the lock and tty before leaving */
316 spin_unlock_irqrestore(&port->lock, flags);
317
318 return IRQ_HANDLED;
319}
320
321/**
322 * xuartps_calc_baud_divs - Calculate baud rate divisors
323 * @clk: UART module input clock
324 * @baud: Desired baud rate
325 * @rbdiv: BDIV value (return value)
326 * @rcd: CD value (return value)
327 * @div8: Value for clk_sel bit in mod (return value)
328 * Returns baud rate, requested baud when possible, or actual baud when there
329 * was too much error, zero if no valid divisors are found.
330 *
331 * Formula to obtain baud rate is
332 * baud_tx/rx rate = clk/CD * (BDIV + 1)
333 * input_clk = (Uart User Defined Clock or Apb Clock)
334 * depends on UCLKEN in MR Reg
335 * clk = input_clk or input_clk/8;
336 * depends on CLKS in MR reg
337 * CD and BDIV depends on values in
338 * baud rate generate register
339 * baud rate clock divisor register
340 */
341static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud,
342 u32 *rbdiv, u32 *rcd, int *div8)
343{
344 u32 cd, bdiv;
345 unsigned int calc_baud;
346 unsigned int bestbaud = 0;
347 unsigned int bauderror;
348 unsigned int besterror = ~0;
349
350 if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) {
351 *div8 = 1;
352 clk /= 8;
353 } else {
354 *div8 = 0;
355 }
356
357 for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) {
358 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
359 if (cd < 1 || cd > XUARTPS_CD_MAX)
360 continue;
361
362 calc_baud = clk / (cd * (bdiv + 1));
363
364 if (baud > calc_baud)
365 bauderror = baud - calc_baud;
366 else
367 bauderror = calc_baud - baud;
368
369 if (besterror > bauderror) {
370 *rbdiv = bdiv;
371 *rcd = cd;
372 bestbaud = calc_baud;
373 besterror = bauderror;
374 }
375 }
376 /* use the values when percent error is acceptable */
377 if (((besterror * 100) / baud) < 3)
378 bestbaud = baud;
379
380 return bestbaud;
381}
382
383/**
384 * xuartps_set_baud_rate - Calculate and set the baud rate
385 * @port: Handle to the uart port structure
386 * @baud: Baud rate to set
387 * Returns baud rate, requested baud when possible, or actual baud when there
388 * was too much error, zero if no valid divisors are found.
389 */
390static unsigned int xuartps_set_baud_rate(struct uart_port *port,
391 unsigned int baud)
392{
393 unsigned int calc_baud;
394 u32 cd = 0, bdiv = 0;
395 u32 mreg;
396 int div8;
397 struct xuartps *xuartps = port->private_data;
398
399 calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
400 &div8);
401
402 /* Write new divisors to hardware */
403 mreg = xuartps_readl(XUARTPS_MR_OFFSET);
404 if (div8)
405 mreg |= XUARTPS_MR_CLKSEL;
406 else
407 mreg &= ~XUARTPS_MR_CLKSEL;
408 xuartps_writel(mreg, XUARTPS_MR_OFFSET);
409 xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET);
410 xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET);
411 xuartps->baud = baud;
412
413 return calc_baud;
414}
415
416#ifdef CONFIG_COMMON_CLK
417/**
418 * xuartps_clk_notitifer_cb - Clock notifier callback
419 * @nb: Notifier block
420 * @event: Notify event
421 * @data: Notifier data
422 * Returns NOTIFY_OK on success, NOTIFY_BAD on error.
423 */
424static int xuartps_clk_notifier_cb(struct notifier_block *nb,
425 unsigned long event, void *data)
426{
427 u32 ctrl_reg;
428 struct uart_port *port;
429 int locked = 0;
430 struct clk_notifier_data *ndata = data;
431 unsigned long flags = 0;
432 struct xuartps *xuartps = to_xuartps(nb);
433
434 port = xuartps->port;
435 if (port->suspended)
436 return NOTIFY_OK;
437
438 switch (event) {
439 case PRE_RATE_CHANGE:
440 {
441 u32 bdiv;
442 u32 cd;
443 int div8;
444
445 /*
446 * Find out if current baud-rate can be achieved with new clock
447 * frequency.
448 */
449 if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud,
450 &bdiv, &cd, &div8))
451 return NOTIFY_BAD;
452
453 spin_lock_irqsave(&xuartps->port->lock, flags);
454
455 /* Disable the TX and RX to set baud rate */
456 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
457 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
458 XUARTPS_CR_OFFSET);
459
460 spin_unlock_irqrestore(&xuartps->port->lock, flags);
461
462 return NOTIFY_OK;
463 }
464 case POST_RATE_CHANGE:
465 /*
466 * Set clk dividers to generate correct baud with new clock
467 * frequency.
468 */
469
470 spin_lock_irqsave(&xuartps->port->lock, flags);
471
472 locked = 1;
473 port->uartclk = ndata->new_rate;
474
475 xuartps->baud = xuartps_set_baud_rate(xuartps->port,
476 xuartps->baud);
477 /* fall through */
478 case ABORT_RATE_CHANGE:
479 if (!locked)
480 spin_lock_irqsave(&xuartps->port->lock, flags);
481
482 /* Set TX/RX Reset */
483 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
484 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
485 XUARTPS_CR_OFFSET);
486
487 while (xuartps_readl(XUARTPS_CR_OFFSET) &
488 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
489 cpu_relax();
490
491 /*
492 * Clear the RX disable and TX disable bits and then set the TX
493 * enable bit and RX enable bit to enable the transmitter and
494 * receiver.
495 */
496 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
497 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
498 xuartps_writel(
499 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
500 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
501 XUARTPS_CR_OFFSET);
502
503 spin_unlock_irqrestore(&xuartps->port->lock, flags);
504
505 return NOTIFY_OK;
506 default:
507 return NOTIFY_DONE;
508 }
509}
510#endif
511
512/*----------------------Uart Operations---------------------------*/
513
514/**
515 * xuartps_start_tx - Start transmitting bytes
516 * @port: Handle to the uart port structure
517 *
518 **/
519static void xuartps_start_tx(struct uart_port *port)
520{
521 unsigned int status, numbytes = port->fifosize;
522
523 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
524 return;
525
526 status = xuartps_readl(XUARTPS_CR_OFFSET);
527 /* Set the TX enable bit and clear the TX disable bit to enable the
528 * transmitter.
529 */
530 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
531 XUARTPS_CR_OFFSET);
532
533 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
534 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
535
536 /* Break if no more data available in the UART buffer */
537 if (uart_circ_empty(&port->state->xmit))
538 break;
539
540 /* Get the data from the UART circular buffer and
541 * write it to the xuartps's TX_FIFO register.
542 */
543 xuartps_writel(
544 port->state->xmit.buf[port->state->xmit.tail],
545 XUARTPS_FIFO_OFFSET);
546 port->icount.tx++;
547
548 /* Adjust the tail of the UART buffer and wrap
549 * the buffer if it reaches limit.
550 */
551 port->state->xmit.tail = (port->state->xmit.tail + 1) &
552 (UART_XMIT_SIZE - 1);
553 }
554 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET);
555 /* Enable the TX Empty interrupt */
556 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
557
558 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(port);
560}
561
562/**
563 * xuartps_stop_tx - Stop TX
564 * @port: Handle to the uart port structure
565 *
566 **/
567static void xuartps_stop_tx(struct uart_port *port)
568{
569 unsigned int regval;
570
571 regval = xuartps_readl(XUARTPS_CR_OFFSET);
572 regval |= XUARTPS_CR_TX_DIS;
573 /* Disable the transmitter */
574 xuartps_writel(regval, XUARTPS_CR_OFFSET);
575}
576
577/**
578 * xuartps_stop_rx - Stop RX
579 * @port: Handle to the uart port structure
580 *
581 **/
582static void xuartps_stop_rx(struct uart_port *port)
583{
584 unsigned int regval;
585
586 regval = xuartps_readl(XUARTPS_CR_OFFSET);
587 regval |= XUARTPS_CR_RX_DIS;
588 /* Disable the receiver */
589 xuartps_writel(regval, XUARTPS_CR_OFFSET);
590}
591
592/**
593 * xuartps_tx_empty - Check whether TX is empty
594 * @port: Handle to the uart port structure
595 *
596 * Returns TIOCSER_TEMT on success, 0 otherwise
597 **/
598static unsigned int xuartps_tx_empty(struct uart_port *port)
599{
600 unsigned int status;
601
602 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
603 return status ? TIOCSER_TEMT : 0;
604}
605
606/**
607 * xuartps_break_ctl - Based on the input ctl we have to start or stop
608 * transmitting char breaks
609 * @port: Handle to the uart port structure
610 * @ctl: Value based on which start or stop decision is taken
611 *
612 **/
613static void xuartps_break_ctl(struct uart_port *port, int ctl)
614{
615 unsigned int status;
616 unsigned long flags;
617
618 spin_lock_irqsave(&port->lock, flags);
619
620 status = xuartps_readl(XUARTPS_CR_OFFSET);
621
622 if (ctl == -1)
623 xuartps_writel(XUARTPS_CR_STARTBRK | status,
624 XUARTPS_CR_OFFSET);
625 else {
626 if ((status & XUARTPS_CR_STOPBRK) == 0)
627 xuartps_writel(XUARTPS_CR_STOPBRK | status,
628 XUARTPS_CR_OFFSET);
629 }
630 spin_unlock_irqrestore(&port->lock, flags);
631}
632
633/**
634 * xuartps_set_termios - termios operations, handling data length, parity,
635 * stop bits, flow control, baud rate
636 * @port: Handle to the uart port structure
637 * @termios: Handle to the input termios structure
638 * @old: Values of the previously saved termios structure
639 *
640 **/
641static void xuartps_set_termios(struct uart_port *port,
642 struct ktermios *termios, struct ktermios *old)
643{
644 unsigned int cval = 0;
645 unsigned int baud, minbaud, maxbaud;
646 unsigned long flags;
647 unsigned int ctrl_reg, mode_reg;
648
649 spin_lock_irqsave(&port->lock, flags);
650
651 /* Empty the receive FIFO 1st before making changes */
652 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
653 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
654 xuartps_readl(XUARTPS_FIFO_OFFSET);
655 }
656
657 /* Disable the TX and RX to set baud rate */
658 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
659 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
660 XUARTPS_CR_OFFSET);
661
662 /*
663 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
664 * min and max baud should be calculated here based on port->uartclk.
665 * this way we get a valid baud and can safely call set_baud()
666 */
667 minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8);
668 maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1);
669 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
670 baud = xuartps_set_baud_rate(port, baud);
671 if (tty_termios_baud_rate(termios))
672 tty_termios_encode_baud_rate(termios, baud, baud);
673
674 /*
675 * Update the per-port timeout.
676 */
677 uart_update_timeout(port, termios->c_cflag, baud);
678
679 /* Set TX/RX Reset */
680 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
681 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
682 XUARTPS_CR_OFFSET);
683
684 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
685
686 /* Clear the RX disable and TX disable bits and then set the TX enable
687 * bit and RX enable bit to enable the transmitter and receiver.
688 */
689 xuartps_writel(
690 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
691 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
692 XUARTPS_CR_OFFSET);
693
694 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
695
696 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
697 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
698 port->ignore_status_mask = 0;
699
700 if (termios->c_iflag & INPCK)
701 port->read_status_mask |= XUARTPS_IXR_PARITY |
702 XUARTPS_IXR_FRAMING;
703
704 if (termios->c_iflag & IGNPAR)
705 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
706 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
707
708 /* ignore all characters if CREAD is not set */
709 if ((termios->c_cflag & CREAD) == 0)
710 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
711 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
712 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
713
714 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
715
716 /* Handling Data Size */
717 switch (termios->c_cflag & CSIZE) {
718 case CS6:
719 cval |= XUARTPS_MR_CHARLEN_6_BIT;
720 break;
721 case CS7:
722 cval |= XUARTPS_MR_CHARLEN_7_BIT;
723 break;
724 default:
725 case CS8:
726 cval |= XUARTPS_MR_CHARLEN_8_BIT;
727 termios->c_cflag &= ~CSIZE;
728 termios->c_cflag |= CS8;
729 break;
730 }
731
732 /* Handling Parity and Stop Bits length */
733 if (termios->c_cflag & CSTOPB)
734 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
735 else
736 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
737
738 if (termios->c_cflag & PARENB) {
739 /* Mark or Space parity */
740 if (termios->c_cflag & CMSPAR) {
741 if (termios->c_cflag & PARODD)
742 cval |= XUARTPS_MR_PARITY_MARK;
743 else
744 cval |= XUARTPS_MR_PARITY_SPACE;
745 } else {
746 if (termios->c_cflag & PARODD)
747 cval |= XUARTPS_MR_PARITY_ODD;
748 else
749 cval |= XUARTPS_MR_PARITY_EVEN;
750 }
751 } else {
752 cval |= XUARTPS_MR_PARITY_NONE;
753 }
754 cval |= mode_reg & 1;
755 xuartps_writel(cval, XUARTPS_MR_OFFSET);
756
757 spin_unlock_irqrestore(&port->lock, flags);
758}
759
760/**
761 * xuartps_startup - Called when an application opens a xuartps port
762 * @port: Handle to the uart port structure
763 *
764 * Returns 0 on success, negative error otherwise
765 **/
766static int xuartps_startup(struct uart_port *port)
767{
768 unsigned int retval = 0, status = 0;
769
770 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
771 (void *)port);
772 if (retval)
773 return retval;
774
775 /* Disable the TX and RX */
776 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
777 XUARTPS_CR_OFFSET);
778
779 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
780 * no break chars.
781 */
782 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
783 XUARTPS_CR_OFFSET);
784
785 status = xuartps_readl(XUARTPS_CR_OFFSET);
786
787 /* Clear the RX disable and TX disable bits and then set the TX enable
788 * bit and RX enable bit to enable the transmitter and receiver.
789 */
790 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
791 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
792 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
793
794 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
795 * no parity.
796 */
797 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
798 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
799 XUARTPS_MR_OFFSET);
800
801 /*
802 * Set the RX FIFO Trigger level to use most of the FIFO, but it
803 * can be tuned with a module parameter
804 */
805 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
806
807 /*
808 * Receive Timeout register is enabled but it
809 * can be tuned with a module parameter
810 */
811 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
812
813 /* Clear out any pending interrupts before enabling them */
814 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
815
816 /* Set the Interrupt Registers with desired interrupts */
817 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
818 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
819 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
820
821 return retval;
822}
823
824/**
825 * xuartps_shutdown - Called when an application closes a xuartps port
826 * @port: Handle to the uart port structure
827 *
828 **/
829static void xuartps_shutdown(struct uart_port *port)
830{
831 int status;
832
833 /* Disable interrupts */
834 status = xuartps_readl(XUARTPS_IMR_OFFSET);
835 xuartps_writel(status, XUARTPS_IDR_OFFSET);
836
837 /* Disable the TX and RX */
838 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
839 XUARTPS_CR_OFFSET);
840 free_irq(port->irq, port);
841}
842
843/**
844 * xuartps_type - Set UART type to xuartps port
845 * @port: Handle to the uart port structure
846 *
847 * Returns string on success, NULL otherwise
848 **/
849static const char *xuartps_type(struct uart_port *port)
850{
851 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
852}
853
854/**
855 * xuartps_verify_port - Verify the port params
856 * @port: Handle to the uart port structure
857 * @ser: Handle to the structure whose members are compared
858 *
859 * Returns 0 if success otherwise -EINVAL
860 **/
861static int xuartps_verify_port(struct uart_port *port,
862 struct serial_struct *ser)
863{
864 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
865 return -EINVAL;
866 if (port->irq != ser->irq)
867 return -EINVAL;
868 if (ser->io_type != UPIO_MEM)
869 return -EINVAL;
870 if (port->iobase != ser->port)
871 return -EINVAL;
872 if (ser->hub6 != 0)
873 return -EINVAL;
874 return 0;
875}
876
877/**
878 * xuartps_request_port - Claim the memory region attached to xuartps port,
879 * called when the driver adds a xuartps port via
880 * uart_add_one_port()
881 * @port: Handle to the uart port structure
882 *
883 * Returns 0, -ENOMEM if request fails
884 **/
885static int xuartps_request_port(struct uart_port *port)
886{
887 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
888 XUARTPS_NAME)) {
889 return -ENOMEM;
890 }
891
892 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
893 if (!port->membase) {
894 dev_err(port->dev, "Unable to map registers\n");
895 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
896 return -ENOMEM;
897 }
898 return 0;
899}
900
901/**
902 * xuartps_release_port - Release the memory region attached to a xuartps
903 * port, called when the driver removes a xuartps
904 * port via uart_remove_one_port().
905 * @port: Handle to the uart port structure
906 *
907 **/
908static void xuartps_release_port(struct uart_port *port)
909{
910 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
911 iounmap(port->membase);
912 port->membase = NULL;
913}
914
915/**
916 * xuartps_config_port - Configure xuartps, called when the driver adds a
917 * xuartps port
918 * @port: Handle to the uart port structure
919 * @flags: If any
920 *
921 **/
922static void xuartps_config_port(struct uart_port *port, int flags)
923{
924 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
925 port->type = PORT_XUARTPS;
926}
927
928/**
929 * xuartps_get_mctrl - Get the modem control state
930 *
931 * @port: Handle to the uart port structure
932 *
933 * Returns the modem control state
934 *
935 **/
936static unsigned int xuartps_get_mctrl(struct uart_port *port)
937{
938 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
939}
940
941static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
942{
943 /* N/A */
944}
945
946static void xuartps_enable_ms(struct uart_port *port)
947{
948 /* N/A */
949}
950
951#ifdef CONFIG_CONSOLE_POLL
952static int xuartps_poll_get_char(struct uart_port *port)
953{
954 u32 imr;
955 int c;
956
957 /* Disable all interrupts */
958 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
959 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
960
961 /* Check if FIFO is empty */
962 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)
963 c = NO_POLL_CHAR;
964 else /* Read a character */
965 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET);
966
967 /* Enable interrupts */
968 xuartps_writel(imr, XUARTPS_IER_OFFSET);
969
970 return c;
971}
972
973static void xuartps_poll_put_char(struct uart_port *port, unsigned char c)
974{
975 u32 imr;
976
977 /* Disable all interrupts */
978 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
979 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
980
981 /* Wait until FIFO is empty */
982 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
983 cpu_relax();
984
985 /* Write a character */
986 xuartps_writel(c, XUARTPS_FIFO_OFFSET);
987
988 /* Wait until FIFO is empty */
989 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
990 cpu_relax();
991
992 /* Enable interrupts */
993 xuartps_writel(imr, XUARTPS_IER_OFFSET);
994
995 return;
996}
997#endif
998
999/** The UART operations structure
1000 */
1001static struct uart_ops xuartps_ops = {
1002 .set_mctrl = xuartps_set_mctrl,
1003 .get_mctrl = xuartps_get_mctrl,
1004 .enable_ms = xuartps_enable_ms,
1005
1006 .start_tx = xuartps_start_tx, /* Start transmitting */
1007 .stop_tx = xuartps_stop_tx, /* Stop transmission */
1008 .stop_rx = xuartps_stop_rx, /* Stop reception */
1009 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
1010 .break_ctl = xuartps_break_ctl, /* Start/stop
1011 * transmitting break
1012 */
1013 .set_termios = xuartps_set_termios, /* Set termios */
1014 .startup = xuartps_startup, /* App opens xuartps */
1015 .shutdown = xuartps_shutdown, /* App closes xuartps */
1016 .type = xuartps_type, /* Set UART type */
1017 .verify_port = xuartps_verify_port, /* Verification of port
1018 * params
1019 */
1020 .request_port = xuartps_request_port, /* Claim resources
1021 * associated with a
1022 * xuartps port
1023 */
1024 .release_port = xuartps_release_port, /* Release resources
1025 * associated with a
1026 * xuartps port
1027 */
1028 .config_port = xuartps_config_port, /* Configure when driver
1029 * adds a xuartps port
1030 */
1031#ifdef CONFIG_CONSOLE_POLL
1032 .poll_get_char = xuartps_poll_get_char,
1033 .poll_put_char = xuartps_poll_put_char,
1034#endif
1035};
1036
1037static struct uart_port xuartps_port[2];
1038
1039/**
1040 * xuartps_get_port - Configure the port from the platform device resource
1041 * info
1042 *
1043 * Returns a pointer to a uart_port or NULL for failure
1044 **/
1045static struct uart_port *xuartps_get_port(void)
1046{
1047 struct uart_port *port;
1048 int id;
1049
1050 /* Find the next unused port */
1051 for (id = 0; id < XUARTPS_NR_PORTS; id++)
1052 if (xuartps_port[id].mapbase == 0)
1053 break;
1054
1055 if (id >= XUARTPS_NR_PORTS)
1056 return NULL;
1057
1058 port = &xuartps_port[id];
1059
1060 /* At this point, we've got an empty uart_port struct, initialize it */
1061 spin_lock_init(&port->lock);
1062 port->membase = NULL;
1063 port->iobase = 1; /* mark port in use */
1064 port->irq = 0;
1065 port->type = PORT_UNKNOWN;
1066 port->iotype = UPIO_MEM32;
1067 port->flags = UPF_BOOT_AUTOCONF;
1068 port->ops = &xuartps_ops;
1069 port->fifosize = XUARTPS_FIFO_SIZE;
1070 port->line = id;
1071 port->dev = NULL;
1072 return port;
1073}
1074
1075/*-----------------------Console driver operations--------------------------*/
1076
1077#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1078/**
1079 * xuartps_console_wait_tx - Wait for the TX to be full
1080 * @port: Handle to the uart port structure
1081 *
1082 **/
1083static void xuartps_console_wait_tx(struct uart_port *port)
1084{
1085 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
1086 != XUARTPS_SR_TXEMPTY)
1087 barrier();
1088}
1089
1090/**
1091 * xuartps_console_putchar - write the character to the FIFO buffer
1092 * @port: Handle to the uart port structure
1093 * @ch: Character to be written
1094 *
1095 **/
1096static void xuartps_console_putchar(struct uart_port *port, int ch)
1097{
1098 xuartps_console_wait_tx(port);
1099 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
1100}
1101
1102/**
1103 * xuartps_console_write - perform write operation
1104 * @port: Handle to the uart port structure
1105 * @s: Pointer to character array
1106 * @count: No of characters
1107 **/
1108static void xuartps_console_write(struct console *co, const char *s,
1109 unsigned int count)
1110{
1111 struct uart_port *port = &xuartps_port[co->index];
1112 unsigned long flags;
1113 unsigned int imr, ctrl;
1114 int locked = 1;
1115
1116 if (oops_in_progress)
1117 locked = spin_trylock_irqsave(&port->lock, flags);
1118 else
1119 spin_lock_irqsave(&port->lock, flags);
1120
1121 /* save and disable interrupt */
1122 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
1123 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
1124
1125 /*
1126 * Make sure that the tx part is enabled. Set the TX enable bit and
1127 * clear the TX disable bit to enable the transmitter.
1128 */
1129 ctrl = xuartps_readl(XUARTPS_CR_OFFSET);
1130 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
1131 XUARTPS_CR_OFFSET);
1132
1133 uart_console_write(port, s, count, xuartps_console_putchar);
1134 xuartps_console_wait_tx(port);
1135
1136 xuartps_writel(ctrl, XUARTPS_CR_OFFSET);
1137
1138 /* restore interrupt state, it seems like there may be a h/w bug
1139 * in that the interrupt enable register should not need to be
1140 * written based on the data sheet
1141 */
1142 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
1143 xuartps_writel(imr, XUARTPS_IER_OFFSET);
1144
1145 if (locked)
1146 spin_unlock_irqrestore(&port->lock, flags);
1147}
1148
1149/**
1150 * xuartps_console_setup - Initialize the uart to default config
1151 * @co: Console handle
1152 * @options: Initial settings of uart
1153 *
1154 * Returns 0, -ENODEV if no device
1155 **/
1156static int __init xuartps_console_setup(struct console *co, char *options)
1157{
1158 struct uart_port *port = &xuartps_port[co->index];
1159 int baud = 9600;
1160 int bits = 8;
1161 int parity = 'n';
1162 int flow = 'n';
1163
1164 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
1165 return -EINVAL;
1166
1167 if (!port->mapbase) {
1168 pr_debug("console on ttyPS%i not present\n", co->index);
1169 return -ENODEV;
1170 }
1171
1172 if (options)
1173 uart_parse_options(options, &baud, &parity, &bits, &flow);
1174
1175 return uart_set_options(port, co, baud, parity, bits, flow);
1176}
1177
1178static struct uart_driver xuartps_uart_driver;
1179
1180static struct console xuartps_console = {
1181 .name = XUARTPS_TTY_NAME,
1182 .write = xuartps_console_write,
1183 .device = uart_console_device,
1184 .setup = xuartps_console_setup,
1185 .flags = CON_PRINTBUFFER,
1186 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1187 .data = &xuartps_uart_driver,
1188};
1189
1190/**
1191 * xuartps_console_init - Initialization call
1192 *
1193 * Returns 0 on success, negative error otherwise
1194 **/
1195static int __init xuartps_console_init(void)
1196{
1197 register_console(&xuartps_console);
1198 return 0;
1199}
1200
1201console_initcall(xuartps_console_init);
1202
1203#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1204
1205/** Structure Definitions
1206 */
1207static struct uart_driver xuartps_uart_driver = {
1208 .owner = THIS_MODULE, /* Owner */
1209 .driver_name = XUARTPS_NAME, /* Driver name */
1210 .dev_name = XUARTPS_TTY_NAME, /* Node name */
1211 .major = XUARTPS_MAJOR, /* Major number */
1212 .minor = XUARTPS_MINOR, /* Minor number */
1213 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
1214#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1215 .cons = &xuartps_console, /* Console */
1216#endif
1217};
1218
1219#ifdef CONFIG_PM_SLEEP
1220/**
1221 * xuartps_suspend - suspend event
1222 * @device: Pointer to the device structure
1223 *
1224 * Returns 0
1225 */
1226static int xuartps_suspend(struct device *device)
1227{
1228 struct uart_port *port = dev_get_drvdata(device);
1229 struct tty_struct *tty;
1230 struct device *tty_dev;
1231 int may_wake = 0;
1232
1233 /* Get the tty which could be NULL so don't assume it's valid */
1234 tty = tty_port_tty_get(&port->state->port);
1235 if (tty) {
1236 tty_dev = tty->dev;
1237 may_wake = device_may_wakeup(tty_dev);
1238 tty_kref_put(tty);
1239 }
1240
1241 /*
1242 * Call the API provided in serial_core.c file which handles
1243 * the suspend.
1244 */
1245 uart_suspend_port(&xuartps_uart_driver, port);
1246 if (console_suspend_enabled && !may_wake) {
1247 struct xuartps *xuartps = port->private_data;
1248
1249 clk_disable(xuartps->refclk);
1250 clk_disable(xuartps->aperclk);
1251 } else {
1252 unsigned long flags = 0;
1253
1254 spin_lock_irqsave(&port->lock, flags);
1255 /* Empty the receive FIFO 1st before making changes */
1256 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY))
1257 xuartps_readl(XUARTPS_FIFO_OFFSET);
1258 /* set RX trigger level to 1 */
1259 xuartps_writel(1, XUARTPS_RXWM_OFFSET);
1260 /* disable RX timeout interrups */
1261 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET);
1262 spin_unlock_irqrestore(&port->lock, flags);
1263 }
1264
1265 return 0;
1266}
1267
1268/**
1269 * xuartps_resume - Resume after a previous suspend
1270 * @device: Pointer to the device structure
1271 *
1272 * Returns 0
1273 */
1274static int xuartps_resume(struct device *device)
1275{
1276 struct uart_port *port = dev_get_drvdata(device);
1277 unsigned long flags = 0;
1278 u32 ctrl_reg;
1279 struct tty_struct *tty;
1280 struct device *tty_dev;
1281 int may_wake = 0;
1282
1283 /* Get the tty which could be NULL so don't assume it's valid */
1284 tty = tty_port_tty_get(&port->state->port);
1285 if (tty) {
1286 tty_dev = tty->dev;
1287 may_wake = device_may_wakeup(tty_dev);
1288 tty_kref_put(tty);
1289 }
1290
1291 if (console_suspend_enabled && !may_wake) {
1292 struct xuartps *xuartps = port->private_data;
1293
1294 clk_enable(xuartps->aperclk);
1295 clk_enable(xuartps->refclk);
1296
1297 spin_lock_irqsave(&port->lock, flags);
1298
1299 /* Set TX/RX Reset */
1300 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
1301 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
1302 XUARTPS_CR_OFFSET);
1303 while (xuartps_readl(XUARTPS_CR_OFFSET) &
1304 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
1305 cpu_relax();
1306
1307 /* restore rx timeout value */
1308 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
1309 /* Enable Tx/Rx */
1310 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
1311 xuartps_writel(
1312 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
1313 (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
1314 XUARTPS_CR_OFFSET);
1315
1316 spin_unlock_irqrestore(&port->lock, flags);
1317 } else {
1318 spin_lock_irqsave(&port->lock, flags);
1319 /* restore original rx trigger level */
1320 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
1321 /* enable RX timeout interrupt */
1322 xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
1323 spin_unlock_irqrestore(&port->lock, flags);
1324 }
1325
1326 return uart_resume_port(&xuartps_uart_driver, port);
1327}
1328#endif /* ! CONFIG_PM_SLEEP */
1329
1330static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume);
1331
1332/* ---------------------------------------------------------------------
1333 * Platform bus binding
1334 */
1335/**
1336 * xuartps_probe - Platform driver probe
1337 * @pdev: Pointer to the platform device structure
1338 *
1339 * Returns 0 on success, negative error otherwise
1340 **/
1341static int xuartps_probe(struct platform_device *pdev)
1342{
1343 int rc;
1344 struct uart_port *port;
1345 struct resource *res, *res2;
1346 struct xuartps *xuartps_data;
1347
1348 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data),
1349 GFP_KERNEL);
1350 if (!xuartps_data)
1351 return -ENOMEM;
1352
1353 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk");
1354 if (IS_ERR(xuartps_data->aperclk)) {
1355 dev_err(&pdev->dev, "aper_clk clock not found.\n");
1356 return PTR_ERR(xuartps_data->aperclk);
1357 }
1358 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1359 if (IS_ERR(xuartps_data->refclk)) {
1360 dev_err(&pdev->dev, "ref_clk clock not found.\n");
1361 return PTR_ERR(xuartps_data->refclk);
1362 }
1363
1364 rc = clk_prepare_enable(xuartps_data->aperclk);
1365 if (rc) {
1366 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
1367 return rc;
1368 }
1369 rc = clk_prepare_enable(xuartps_data->refclk);
1370 if (rc) {
1371 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1372 goto err_out_clk_dis_aper;
1373 }
1374
1375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1376 if (!res) {
1377 rc = -ENODEV;
1378 goto err_out_clk_disable;
1379 }
1380
1381 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1382 if (!res2) {
1383 rc = -ENODEV;
1384 goto err_out_clk_disable;
1385 }
1386
1387#ifdef CONFIG_COMMON_CLK
1388 xuartps_data->clk_rate_change_nb.notifier_call =
1389 xuartps_clk_notifier_cb;
1390 if (clk_notifier_register(xuartps_data->refclk,
1391 &xuartps_data->clk_rate_change_nb))
1392 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1393#endif
1394
1395 /* Initialize the port structure */
1396 port = xuartps_get_port();
1397
1398 if (!port) {
1399 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1400 rc = -ENODEV;
1401 goto err_out_notif_unreg;
1402 } else {
1403 /* Register the port.
1404 * This function also registers this device with the tty layer
1405 * and triggers invocation of the config_port() entry point.
1406 */
1407 port->mapbase = res->start;
1408 port->irq = res2->start;
1409 port->dev = &pdev->dev;
1410 port->uartclk = clk_get_rate(xuartps_data->refclk);
1411 port->private_data = xuartps_data;
1412 xuartps_data->port = port;
1413 platform_set_drvdata(pdev, port);
1414 rc = uart_add_one_port(&xuartps_uart_driver, port);
1415 if (rc) {
1416 dev_err(&pdev->dev,
1417 "uart_add_one_port() failed; err=%i\n", rc);
1418 goto err_out_notif_unreg;
1419 }
1420 return 0;
1421 }
1422
1423err_out_notif_unreg:
1424#ifdef CONFIG_COMMON_CLK
1425 clk_notifier_unregister(xuartps_data->refclk,
1426 &xuartps_data->clk_rate_change_nb);
1427#endif
1428err_out_clk_disable:
1429 clk_disable_unprepare(xuartps_data->refclk);
1430err_out_clk_dis_aper:
1431 clk_disable_unprepare(xuartps_data->aperclk);
1432
1433 return rc;
1434}
1435
1436/**
1437 * xuartps_remove - called when the platform driver is unregistered
1438 * @pdev: Pointer to the platform device structure
1439 *
1440 * Returns 0 on success, negative error otherwise
1441 **/
1442static int xuartps_remove(struct platform_device *pdev)
1443{
1444 struct uart_port *port = platform_get_drvdata(pdev);
1445 struct xuartps *xuartps_data = port->private_data;
1446 int rc;
1447
1448 /* Remove the xuartps port from the serial core */
1449#ifdef CONFIG_COMMON_CLK
1450 clk_notifier_unregister(xuartps_data->refclk,
1451 &xuartps_data->clk_rate_change_nb);
1452#endif
1453 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1454 port->mapbase = 0;
1455 clk_disable_unprepare(xuartps_data->refclk);
1456 clk_disable_unprepare(xuartps_data->aperclk);
1457 return rc;
1458}
1459
1460/* Match table for of_platform binding */
1461static struct of_device_id xuartps_of_match[] = {
1462 { .compatible = "xlnx,xuartps", },
1463 {}
1464};
1465MODULE_DEVICE_TABLE(of, xuartps_of_match);
1466
1467static struct platform_driver xuartps_platform_driver = {
1468 .probe = xuartps_probe, /* Probe method */
1469 .remove = xuartps_remove, /* Detach method */
1470 .driver = {
1471 .owner = THIS_MODULE,
1472 .name = XUARTPS_NAME, /* Driver name */
1473 .of_match_table = xuartps_of_match,
1474 .pm = &xuartps_dev_pm_ops,
1475 },
1476};
1477
1478/* ---------------------------------------------------------------------
1479 * Module Init and Exit
1480 */
1481/**
1482 * xuartps_init - Initial driver registration call
1483 *
1484 * Returns whether the registration was successful or not
1485 **/
1486static int __init xuartps_init(void)
1487{
1488 int retval = 0;
1489
1490 /* Register the xuartps driver with the serial core */
1491 retval = uart_register_driver(&xuartps_uart_driver);
1492 if (retval)
1493 return retval;
1494
1495 /* Register the platform driver */
1496 retval = platform_driver_register(&xuartps_platform_driver);
1497 if (retval)
1498 uart_unregister_driver(&xuartps_uart_driver);
1499
1500 return retval;
1501}
1502
1503/**
1504 * xuartps_exit - Driver unregistration call
1505 **/
1506static void __exit xuartps_exit(void)
1507{
1508 /* The order of unregistration is important. Unregister the
1509 * UART driver before the platform driver crashes the system.
1510 */
1511
1512 /* Unregister the platform driver */
1513 platform_driver_unregister(&xuartps_platform_driver);
1514
1515 /* Unregister the xuartps driver */
1516 uart_unregister_driver(&xuartps_uart_driver);
1517}
1518
1519module_init(xuartps_init);
1520module_exit(xuartps_exit);
1521
1522MODULE_DESCRIPTION("Driver for PS UART");
1523MODULE_AUTHOR("Xilinx Inc.");
1524MODULE_LICENSE("GPL");